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/*****************************************************************************/
 
/*
 *      (C) Copyright 1999, Greg Ungerer.
 *      (C) Copyright 1999, D. Jeff Dionne
 *
 *      1999/02/24 Modified for the 5307 processor David W. Miller
 *      1999/11/20 Support for the 5204 by D. Jeff Dionne
 */
 
/*****************************************************************************/
 
.global _start
.global _stext
.global out_char
 
/*****************************************************************************/
 
.section .ramvec
.long 0
 
.text
/*
 *      This is the codes first entry point. This is where it all
 *      begins...
 */
 
_start:
_stext:
        nop                                     /* Filler */
        move.w  #0x2700, %sr                    /* No interrupts */
#if 0
        /*
         * Setup vbr here, otherwise buserror remap will not work.
         * if dBug was active before (on my SBC with dBug 1.1 of Dec 16 1996)
         *
         * bkr@cut.de 19990306
         *
         * Note: this is because dBUG points VBR to ROM, making vectors read
         * only, so the bus trap can't be changed. (RS)
         */
        move.l  #VBR_BASE, %a7                  /* Note VBR can't be read */
        movec   %a7, %VBR
        move.l  %a7, _ramvec                    /* Set up vector addr */
        move.l  %a7, _rambase                   /* Set up base RAM addr */
#endif
        pea     65
        jsr     out_char
        pea     65
        jsr     out_char
        pea     65
        jsr     out_char
        pea     65
        jsr     out_char
        jsr start_kernel
_exit:
        rte
 
out_char:
        move.l  4(%sp), %d1
        move.l  #0x13, %d0
        trap #15
        rts
 
/*****************************************************************************/

Line No.	Rev	Author	Line
1	199	simons	`/*****************************************************************************/`
2
3			`/*`
4			`* (C) Copyright 1999, Greg Ungerer.`
5			`* (C) Copyright 1999, D. Jeff Dionne`
6			`*`
7			`* 1999/02/24 Modified for the 5307 processor David W. Miller`
8			`* 1999/11/20 Support for the 5204 by D. Jeff Dionne`
9			`*/`
10
11			`/*****************************************************************************/`
12
13			`.global _start`
14			`.global _stext`
15			`.global out_char`
16
17			`/*****************************************************************************/`
18
19			`.section .ramvec`
20			`.long 0`
21
22			`.text`
23			`/*`
24			`* This is the codes first entry point. This is where it all`
25			`* begins...`
26			`*/`
27
28			`_start:`
29			`_stext:`
30			`nop /* Filler */`
31			`move.w #0x2700, %sr /* No interrupts */`
32			`#if 0`
33			`/*`
34			`* Setup vbr here, otherwise buserror remap will not work.`
35			`* if dBug was active before (on my SBC with dBug 1.1 of Dec 16 1996)`
36			`*`
37			`* bkr@cut.de 19990306`
38			`*`
39			`* Note: this is because dBUG points VBR to ROM, making vectors read`
40			`* only, so the bus trap can't be changed. (RS)`
41			`*/`
42			`move.l #VBR_BASE, %a7 /* Note VBR can't be read */`
43			`movec %a7, %VBR`
44			`move.l %a7, _ramvec /* Set up vector addr */`
45			`move.l %a7, _rambase /* Set up base RAM addr */`
46			`#endif`
47			`pea 65`
48			`jsr out_char`
49			`pea 65`
50			`jsr out_char`
51			`pea 65`
52			`jsr out_char`
53			`pea 65`
54			`jsr out_char`
55			`jsr start_kernel`
56			`_exit:`
57			`rte`
58
59			`out_char:`
60			`move.l 4(%sp), %d1`
61			`move.l #0x13, %d0`
62			`trap #15`
63			`rts`
64
65			`/*****************************************************************************/`

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[/] [or1k/] [trunk/] [uclinux/] [uClinux-2.0.x/] [arch/] [m68knommu/] [platform/] [5204/] [SBC5204/] [crt0_ram.S] - Blame information for rev 1765