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/*****************************************************************************/
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/*
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* crt0_ram.S -- startup code for MCF5206e ColdFire based eLITE boards.
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*
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* (C) Copyright 1999, Greg Ungerer.
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* Copyright (C) 1999 Rob Scott (rscott@mtrob.fdns.net)
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*
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* 1999/02/24 Modified for the 5307 processor David W. Miller
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*/
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/*****************************************************************************/
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#include "linux/autoconf.h"
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#include "asm/coldfire.h"
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#include "asm/mcfsim.h"
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/*****************************************************************************/
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/*
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* M5206eLITE ColdFire eval board, chip select and memory setup.
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*/
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#ifdef CONFIG_SMALL
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#define MEM_BASE 0x30000000 /* Base memory for M5206eLITE */
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#define MEM_RESERVED 0x00020000 /* Don't use memory reserved by dBUG */
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#define MEM_SIZE 0x00100000 /* 1 MB of SRAM on M5206eLITE */
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#else
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#define MEM_BASE 0x00000000 /* Base memory for M5206eLITE */
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#define MEM_RESERVED 0x00010000 /* Skip first MEM_LUMP for colilo */
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#define MEM_SIZE 0x02000000 /* Max DRAM 32Mb */
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#endif
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#define MEM_MIN MEM_BASE+MEM_RESERVED
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/* Define end of probeable memory space */
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#define MEM_MAX MEM_BASE+MEM_SIZE
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#define MEM_BUILTIN 0x20000000 /* Put built in SRAM at dBUG loc */
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#define MEM_TMPSTACK MEM_BUILTIN+0x800 /* Use built in SRAM for tmp stack */
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#define MEM_LUMP 0x00010000 /* 64 Kb chunks */
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#define VBR_BASE MEM_BUILTIN /* Use built in SRAM for vectors */
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#define CS0_ADDR 0x0000ffe0 /* CS0 connected to Flash ROM */
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#define CS0_MASK 0x000f0000 /* is 1Mbyte */
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#define CS0_CTRL 0x00001da3 /* read-write (for flash) */
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#define CS1_ADDR 0x00000000 /* CS1 not connected */
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#define CS1_MASK 0x00000000
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#define CS1_CTRL 0x00000000
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#define CS2_ADDR 0x00003000 /* CS2 connected to SRAM */
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#define CS2_MASK 0x000f0000 /* is 1Mbyte */
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#define CS2_CTRL 0x00001903 /* read-write */
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#define CS3_ADDR 0x00004000 /* CS3 connected to LED, par port */
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#define CS3_MASK 0x000f0000 /* is 1Mbyte */
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#define CS3_CTRL 0x00000183 /* read-write */
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#define CS4_ADDR 0x00000000 /* CS4 not connected */
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#define CS4_MASK 0x00000000
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#define CS4_CTRL 0x00000000
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#define CS5_ADDR 0x00000000 /* CS5 not connected */
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#define CS5_MASK 0x00000000
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#define CS5_CTRL 0x00000000
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#define CS6_ADDR 0x00000000 /* CS6 not connected */
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#define CS6_MASK 0x00000000
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#define CS6_CTRL 0x00000000
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#define CS7_ADDR 0x00000000 /* CS7 not connected */
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#define CS7_MASK 0x00000000
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#define CS7_CTRL 0x00000000
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#define DMC_CTRL 0x00000000 /* default memory control */
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#define DCRR 0x00000034 /* Refresh period */
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/* DCTR definition:
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<15>: DAEM, 1 = Drive Multiplexed Address During External Master DRAM xfer
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<14>: EDO, 1 = EDO, 0 = Normal
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<12>: RCD, 1 = 2 clk RAS-to-CAS, 0 = 1.0 clk RAS-to-CAS
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<10:09>: RSH, 10 = 3.5 clk RAS low, 01 = 2.5 clk, 00 = 1.5 clk
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<06:05>: RP, 10 = 3.5 clk RAS Precharge, 01 = 2.5 clk, 00 = 1.5 clk
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<03>: CAS, 1 = 2.5 clk CAS assertion, 0 = 1.5 clk
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<01>: CP, 1 = 1.5 CAS clk precharge, 0 = .5 clk
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<00>: CSR, 1 = 2.0 clk CAS before RAS setup, 0 = 1.0 clk
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*/
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#define DCTR 0x0000144B /* Slow DRAM */
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#define DCAR0 0x00000000 /* DRAM0 address, 0 base addr */
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#define DCMR0 0x003e0000 /* DRAM0 mask, 4Mb DRAM */
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#define DCCR0 0x00000007 /* DRAM0 control, R/W, burst pg mde */
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#define DCAR1 0x00000000 /* DRAM1 address, 0 base addr */
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#define DCMR1 0x00000000 /* DRAM1 mask, no DRAM */
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#define DCCR1 0x00000000 /* DRAM1 control, off */
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/*****************************************************************************/
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.global _start
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.global _rambase
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.global _ramvec
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.global _ramstart
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.global _ramend
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/*****************************************************************************/
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.data
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/*
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* Set up the usable of RAM stuff. Size of RAM is determined then
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* an initial stack set up at the end.
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*/
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_rambase:
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.long 0
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_ramvec:
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.long 0
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_ramstart:
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.long 0
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_ramend:
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.long 0
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/*****************************************************************************/
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.text
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/*
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* This is the codes first entry point. This is where it all
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* begins...
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*/
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_start:
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nop /* Filler */
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move.w #0x2700, %sr /* No interrupts */
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move.l #MCF_MBAR+1, %a0 /* Set I/O base addr */
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movec %a0, %MBAR /* Note: bit 0 is Validate */
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move.l #MEM_BUILTIN+1,%a0 /* Set SRAM base addr */
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movec %a0, %RAMBAR0 /* Note: bit 0 is Validate */
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move.l #MCF_MBAR, %a0 /* Get I/O base addr */
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/* ----------------------- CS1 ----------------------- */
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move.w #CS1_ADDR, %d0 /* CS1 address */
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move.w %d0, MCFSIM_CSAR1(%a0) /* CS1 address */
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move.l #CS1_MASK, %d0 /* CS1 mask */
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move.l %d0, MCFSIM_CSMR1(%a0) /* CS1 mask */
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move.w #CS1_CTRL, %d0 /* CS1 control */
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move.w %d0, MCFSIM_CSCR1(%a0) /* CS1 control */
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/* ----------------------- CS2 ----------------------- */
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move.w #CS2_ADDR, %d0 /* CS2 address */
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move.w %d0, MCFSIM_CSAR2(%a0) /* CS2 address */
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move.l #CS2_MASK, %d0 /* CS2 mask */
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move.l %d0, MCFSIM_CSMR2(%a0) /* CS2 mask */
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move.w #CS2_CTRL, %d0 /* CS2 control */
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move.w %d0, MCFSIM_CSCR2(%a0) /* CS2 control */
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/* ----------------------- CS3 ----------------------- */
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move.w #CS3_ADDR, %d0 /* CS3 address */
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move.w %d0, MCFSIM_CSAR3(%a0) /* CS3 address */
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move.l #CS3_MASK, %d0 /* CS3 mask */
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move.l %d0, MCFSIM_CSMR3(%a0) /* CS3 mask */
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move.w #CS3_CTRL, %d0 /* CS3 control */
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move.w %d0, MCFSIM_CSCR3(%a0) /* CS3 control */
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/* ----------------------- CS4 ----------------------- */
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move.w #CS4_ADDR, %d0 /* CS4 address */
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move.w %d0, MCFSIM_CSAR4(%a0) /* CS4 address */
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move.l #CS4_MASK, %d0 /* CS4 mask */
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move.l %d0, MCFSIM_CSMR4(%a0) /* CS4 mask */
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move.w #CS4_CTRL, %d0 /* CS4 control */
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move.w %d0, MCFSIM_CSCR4(%a0) /* CS4 control */
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/* ----------------------- CS5 ----------------------- */
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move.w #CS5_ADDR, %d0 /* CS5 address */
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move.w %d0, MCFSIM_CSAR5(%a0) /* CS5 address */
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move.l #CS5_MASK, %d0 /* CS5 mask */
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move.l %d0, MCFSIM_CSMR5(%a0) /* CS5 mask */
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move.w #CS5_CTRL, %d0 /* CS5 control */
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move.w %d0, MCFSIM_CSCR5(%a0) /* CS5 control */
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/* ----------------------- CS6 ----------------------- */
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move.w #CS6_ADDR, %d0 /* CS6 address */
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move.w %d0, MCFSIM_CSAR6(%a0) /* CS6 address */
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move.l #CS6_MASK, %d0 /* CS6 mask */
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move.l %d0, MCFSIM_CSMR6(%a0) /* CS6 mask */
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move.w #CS6_CTRL, %d0 /* CS6 control */
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move.w %d0, MCFSIM_CSCR6(%a0) /* CS6 control */
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/* ----------------------- CS7 ----------------------- */
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move.w #CS7_ADDR, %d0 /* CS7 address */
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move.w %d0, MCFSIM_CSAR7(%a0) /* CS7 address */
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move.l #CS7_MASK, %d0 /* CS7 mask */
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move.l %d0, MCFSIM_CSMR7(%a0) /* CS7 mask */
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move.w #CS7_CTRL, %d0 /* CS7 control */
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move.w %d0, MCFSIM_CSCR7(%a0) /* CS7 control */
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/* --------------------- Default --------------------- */
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move.w #DMC_CTRL, %d0 /* Default control */
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move.w %d0, MCFSIM_DMCR(%a0) /* Default control */
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/* ----------------------- DRAM ------------------------ */
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move.w #DCRR, %d0 /* Refresh period */
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move.w %d0, MCFSIM_DCRR(%a0) /* Refresh period */
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move.w #DCTR, %d0 /* Timing address */
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move.w %d0, MCFSIM_DCTR(%a0) /* Timing address */
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move.w #DCAR0, %d0 /* DRAM0 base address */
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move.w %d0, MCFSIM_DCAR0(%a0) /* DRAM0 base address */
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move.l #DCMR0, %d0 /* DRAM0 mask */
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move.l %d0, MCFSIM_DCMR0(%a0) /* DRAM0 mask */
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move.b #DCCR0, %d0 /* DRAM0 control */
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move.b %d0, MCFSIM_DCCR0(%a0) /* DRAM0 control */
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move.w #DCAR1, %d0 /* DRAM1 base address */
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move.w %d0, MCFSIM_DCAR1(%a0) /* DRAM1 base address */
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move.l #DCMR1, %d0 /* DRAM1 mask */
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move.l %d0, MCFSIM_DCMR1(%a0) /* DRAM1 mask */
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move.b #DCCR1, %d0 /* DRAM1 control */
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move.b %d0, MCFSIM_DCCR1(%a0) /* DRAM1 control */
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/*
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* ChipSelect 0 - ROM cs
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*
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* ChipSelect 0 is the global chip select coming out of system reset.
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* CS0 is asserted for every access until CSMR0 is written. Therefore,
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* the entire ChipSelect must be properly set prior to asserting
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* CSCR0_V.
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*/
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move.w #CS0_ADDR, %d0 /* CS0 address */
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move.w %d0, MCFSIM_CSAR0(%a0) /* CS0 address */
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move.l #CS0_MASK, %d0 /* CS0 mask */
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move.l %d0, MCFSIM_CSMR0(%a0) /* CS0 mask */
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move.w #CS0_CTRL, %d0 /* CS0 control */
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move.w %d0, MCFSIM_CSCR0(%a0) /* CS0 control */
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/*
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* Setup VBR here, otherwise buserror remap will not work.
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* if dBug was active before (on my SBC with dBug 1.1 of Dec 16 1996)
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*
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* bkr@cut.de 19990306
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*
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* Note: this is because dBUG points VBR to ROM, making vectors read
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* only, so the bus trap can't be changed. (RS)
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*/
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move.l #VBR_BASE, %a7 /* Note VBR can't be read */
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movec %a7, %VBR
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move.l %a7, _ramvec /* Set up vector addr */
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move.l %a7, _rambase /* Set up base RAM addr */
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/*
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* Determine size of RAM, then set up initial stack
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* Done differently for different eval boards and cpus.
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*/
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| 246 |
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#if defined(CONFIG_SMALL)
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/*
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| 248 |
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* Set to SRAM size when configuring a minimal system
|
| 249 |
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*/
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move.l #MEM_MAX, %a0
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| 252 |
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#else
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/*
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| 254 |
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* On the Arnewsh 5206 board and the Motorola m5206eLITE board
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* we can probe for the amount of DRAM present...
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*/
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| 257 |
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move.l #MEM_MIN, %a0 /* Start at bottom */
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move.l #MEM_MAX, %a1 /* Set stop point */
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lea.l MEM_TMPSTACK, %sp /* Set up tmp stack ptr */
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move.l #VBR_BASE+8, %a2 /* Address of bus trap */
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lea.l _ram_buserr, %a3 /* Get RAM trap address */
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| 263 |
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move.l %a3, (%a2) /* Set trap to local ptr */
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| 264 |
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| 265 |
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_find_ram:
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| 266 |
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move.l (%a0), %d0 /* Attempt read */
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| 267 |
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add.l #MEM_LUMP, %a0 /* Try next bank */
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| 268 |
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cmp.l %a1, %a0 /* Check more? */
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| 269 |
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bne _find_ram
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| 270 |
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| 271 |
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/*
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| 272 |
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* BUS error trap handler - used for RAM probing.
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| 273 |
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*/
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| 274 |
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_ram_buserr:
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| 275 |
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bra _found_ram
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| 276 |
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| 277 |
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_found_ram: /* Vectored here on bus err */
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| 278 |
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#endif
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| 279 |
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| 280 |
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move.l %a0, %d0 /* Mem end addr is in a0 */
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| 281 |
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move.l %d0, %sp /* Set up initial stack ptr */
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| 282 |
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move.l %d0, _ramend /* Set end ram addr */
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| 283 |
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| 284 |
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| 285 |
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/*
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| 286 |
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* Enable CPU internal cache.
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| 287 |
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*/
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| 288 |
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move.l #0x01000000, %d0 /* Invalidate cache cmd */
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| 289 |
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movec %d0, %CACR /* Invalidate cache */
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| 290 |
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move.l #0x80000100, %d0 /* Setup cache mask */
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| 291 |
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movec %d0, %CACR /* Enable cache */
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| 292 |
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| 293 |
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| 294 |
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/*
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| 295 |
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* Move ROM filesystem above bss :-)
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| 296 |
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*/
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| 297 |
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lea.l _sbss, %a0 /* Get start of bss */
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| 298 |
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lea.l _ebss, %a1 /* Set up destination */
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| 299 |
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move.l %a0, %a2 /* Copy of bss start */
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| 300 |
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| 301 |
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move.l 8(%a0), %d0 /* Get size of ROMFS */
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| 302 |
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addq.l #8, %d0 /* Allow for rounding */
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| 303 |
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and.l #0xfffffffc, %d0 /* Whole words */
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| 304 |
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| 305 |
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add.l %d0, %a0 /* Copy from end */
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| 306 |
|
|
add.l %d0, %a1 /* Copy from end */
|
| 307 |
|
|
move.l %a1, _ramstart /* Set start of ram */
|
| 308 |
|
|
|
| 309 |
|
|
_copy_romfs:
|
| 310 |
|
|
move.l -(%a0), %d0 /* Copy dword */
|
| 311 |
|
|
move.l %d0, -(%a1)
|
| 312 |
|
|
cmp.l %a0, %a2 /* Check if at end */
|
| 313 |
|
|
bne _copy_romfs
|
| 314 |
|
|
|
| 315 |
|
|
/*
|
| 316 |
|
|
* Zero out the bss region.
|
| 317 |
|
|
*/
|
| 318 |
|
|
lea.l _sbss, %a0 /* Get start of bss */
|
| 319 |
|
|
lea.l _ebss, %a1 /* Get end of bss */
|
| 320 |
|
|
clr.l %d0 /* Set value */
|
| 321 |
|
|
_clear_bss:
|
| 322 |
|
|
move.l %d0, (%a0)+ /* Clear each word */
|
| 323 |
|
|
cmp.l %a0, %a1 /* Check if at end */
|
| 324 |
|
|
bne _clear_bss
|
| 325 |
|
|
|
| 326 |
|
|
/*
|
| 327 |
|
|
* Assember start up done, start code proper.
|
| 328 |
|
|
*/
|
| 329 |
|
|
jsr start_kernel /* Start Linux kernel */
|
| 330 |
|
|
|
| 331 |
|
|
_exit:
|
| 332 |
|
|
jmp _exit /* Should never get here */
|
| 333 |
|
|
|
| 334 |
|
|
/*****************************************************************************/
|
