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[/] [or1k/] [trunk/] [uclinux/] [uClinux-2.0.x/] [arch/] [m68knommu/] [platform/] [5307/] [NETtel/] [crt0_ram.S] - Blame information for rev 1765

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/*****************************************************************************/
 
/*
 *      crt0_ram.S -- startup code for MCF5307 ColdFire based NETtel.
 *
 *      (C) Copyright 1999, Greg Ungerer.
 *
 *      1999/02/24 Modified for the 5307 processor David W. Miller
 */
 
/*****************************************************************************/
 
#include "linux/autoconf.h"
#include "asm/coldfire.h"
#include "asm/mcfsim.h"
#include "asm/nettel.h"
 
/*****************************************************************************/
 
/*
 *      Moreton Bay NETtel board, chip select and memory setup.
 */
 
#define MEM_BASE        0x00000000      /* Memory base at address 0 */
#define MEM_SIZE        0x00400000      /* Memory size 4Mb */
#define VBR_BASE        MEM_BASE        /* Vector address */
 
/*****************************************************************************/
 
.global _start
.global _rambase
.global _ramvec
.global _ramstart
.global _ramend
 
/*****************************************************************************/
 
.data
 
/*
 *      Set up the usable of RAM stuff. Size of RAM is determined then
 *      an initial stack set up at the end.
 */
_rambase:
.long   0
_ramvec:
.long   0
_ramstart:
.long   0
_ramend:
.long   0
 
/*****************************************************************************/
 
/*
 *      The NETtel platform has some funky LEDs!
 */
.global ppdata
ppdata:
.short  0x0000
 
.global ledbank
ledbank:
.byte   0xff
 
/*****************************************************************************/
 
.text
 
/*
 *      This is the codes first entry point. This is where it all
 *      begins...
 */
 
_start:
        nop                                     /* Filler */
        move.w  #0x2700, %sr                    /* No interrupts */
 
        /*
         *      Set LEDs to known startup state.
         */
        move.l  #NETtel_LEDADDR, %a5            /* Addr of LED bank */
        move.b  #0xff, (%a5)                    /* Turn them all off */
 
 
        /*
         *      Disable watchdog timer.
         */
        move.l  #MCF_MBAR, %a0                  /* Get MBAR address */
        clr.l   %d0                             /* Disable SWT */
        move.b  %d0, MCFSIM_SYPCR(%a0)
        move.b  #0x55, %d0                      /* Clear SWT as well */
        move.b  %d0, MCFSIM_SWSR(%a0)
        move.b  #0xaa, %d0
        move.b  %d0, MCFSIM_SWSR(%a0)
        move.l  #0xffffffff, %d0                /* Mask out all interrupts */
        move.l  %d0, MCFSIM_IMR(%a0)
 
        /*
         * Setup VBR here, otherwise buserror remap will not work.
         * if dBug was active before (on my SBC with dBug 1.1 of Dec 16 1996)
         *
         * bkr@cut.de 19990306
         *
         * Note: this is because dBUG points VBR to ROM, making vectors read
         * only, so the bus trap can't be changed. (RS)
         */
        move.l  #VBR_BASE, %a7                  /* Note VBR can't be read */
        movec   %a7, %VBR
        move.l  %a7, _ramvec                    /* Set up vector addr */
        move.l  %a7, _rambase                   /* Set up base RAM addr */
 
 
        /*
         *      Determine size of RAM, then set up initial stack.
         */
        move.l  #MEM_SIZE, %a0
 
        move.l  %a0, %d0                        /* Mem end addr is in a0 */
        move.l  %d0, %sp                        /* Set up initial stack ptr */
        move.l  %d0, _ramend                    /* Set end ram addr */
 
        /*
         *      Enable CPU internal cache.
         */
        move.l  #0x01000000, %d0                /* invalidate whole cache */
        movec   %d0,%CACR
        nop
        move.l  #0x0000c000, %d0                /* Set SDRAM cached only */
        movec   %d0, %ACR0
        move.l  #0x00000000, %d0                /* No other regions cached */
        movec   %d0, %ACR1
 
        /* Enable cache */
        move.l  #0xa0000200, %d0
        movec   %d0,%CACR
        nop
 
        /*
         *      Move ROM filesystem above bss :-)
         */
        lea.l   _sbss, %a0                      /* Get start of bss */
        lea.l   _ebss, %a1                      /* Set up destination  */
        move.l  %a0, %a2                        /* Copy of bss start */
 
        move.l  8(%a0), %d0                     /* Get size of ROMFS */
        addq.l  #8, %d0                         /* Allow for rounding */
        and.l   #0xfffffffc, %d0                /* Whole words */
 
        add.l   %d0, %a0                        /* Copy from end */
        add.l   %d0, %a1                        /* Copy from end */
        move.l  %a1, _ramstart                  /* Set start of ram */
 
_copy_romfs:
        move.l  -(%a0), %d0                     /* Copy dword */
        move.l  %d0, -(%a1)
        cmp.l   %a0, %a2                        /* Check if at end */
        bne     _copy_romfs
 
        /*
         *      Zero out the bss region.
         */
        lea.l   _sbss, %a0                      /* Get start of bss */
        lea.l   _ebss, %a1                      /* Get end of bss */
        clr.l   %d0                             /* Set value */
_clear_bss:
        move.l  %d0, (%a0)+                     /* Clear each word */
        cmp.l   %a0, %a1                        /* Check if at end */
        bne     _clear_bss
 
        /*
         *      Assember start up done, start code proper.
         */
        jsr     start_kernel                    /* Start Linux kernel */
 
_exit:
        jmp     _exit                           /* Should never get here */
 
/*****************************************************************************/

Line No.	Rev	Author	Line
1	199	simons	`/*****************************************************************************/`
2
3			`/*`
4			`* crt0_ram.S -- startup code for MCF5307 ColdFire based NETtel.`
5			`*`
6			`* (C) Copyright 1999, Greg Ungerer.`
7			`*`
8			`* 1999/02/24 Modified for the 5307 processor David W. Miller`
9			`*/`
10
11			`/*****************************************************************************/`
12
13			`#include "linux/autoconf.h"`
14			`#include "asm/coldfire.h"`
15			`#include "asm/mcfsim.h"`
16			`#include "asm/nettel.h"`
17
18			`/*****************************************************************************/`
19
20			`/*`
21			`* Moreton Bay NETtel board, chip select and memory setup.`
22			`*/`
23
24			`#define MEM_BASE 0x00000000 /* Memory base at address 0 */`
25			`#define MEM_SIZE 0x00400000 /* Memory size 4Mb */`
26			`#define VBR_BASE MEM_BASE /* Vector address */`
27
28			`/*****************************************************************************/`
29
30			`.global _start`
31			`.global _rambase`
32			`.global _ramvec`
33			`.global _ramstart`
34			`.global _ramend`
35
36			`/*****************************************************************************/`
37
38			`.data`
39
40			`/*`
41			`* Set up the usable of RAM stuff. Size of RAM is determined then`
42			`* an initial stack set up at the end.`
43			`*/`
44			`_rambase:`
45			`.long 0`
46			`_ramvec:`
47			`.long 0`
48			`_ramstart:`
49			`.long 0`
50			`_ramend:`
51			`.long 0`
52
53			`/*****************************************************************************/`
54
55			`/*`
56			`* The NETtel platform has some funky LEDs!`
57			`*/`
58			`.global ppdata`
59			`ppdata:`
60			`.short 0x0000`
61
62			`.global ledbank`
63			`ledbank:`
64			`.byte 0xff`
65
66			`/*****************************************************************************/`
67
68			`.text`
69
70			`/*`
71			`* This is the codes first entry point. This is where it all`
72			`* begins...`
73			`*/`
74
75			`_start:`
76			`nop /* Filler */`
77			`move.w #0x2700, %sr /* No interrupts */`
78
79			`/*`
80			`* Set LEDs to known startup state.`
81			`*/`
82			`move.l #NETtel_LEDADDR, %a5 /* Addr of LED bank */`
83			`move.b #0xff, (%a5) /* Turn them all off */`
84
85
86			`/*`
87			`* Disable watchdog timer.`
88			`*/`
89			`move.l #MCF_MBAR, %a0 /* Get MBAR address */`
90			`clr.l %d0 /* Disable SWT */`
91			`move.b %d0, MCFSIM_SYPCR(%a0)`
92			`move.b #0x55, %d0 /* Clear SWT as well */`
93			`move.b %d0, MCFSIM_SWSR(%a0)`
94			`move.b #0xaa, %d0`
95			`move.b %d0, MCFSIM_SWSR(%a0)`
96			`move.l #0xffffffff, %d0 /* Mask out all interrupts */`
97			`move.l %d0, MCFSIM_IMR(%a0)`
98
99			`/*`
100			`* Setup VBR here, otherwise buserror remap will not work.`
101			`* if dBug was active before (on my SBC with dBug 1.1 of Dec 16 1996)`
102			`*`
103			`* bkr@cut.de 19990306`
104			`*`
105			`* Note: this is because dBUG points VBR to ROM, making vectors read`
106			`* only, so the bus trap can't be changed. (RS)`
107			`*/`
108			`move.l #VBR_BASE, %a7 /* Note VBR can't be read */`
109			`movec %a7, %VBR`
110			`move.l %a7, _ramvec /* Set up vector addr */`
111			`move.l %a7, _rambase /* Set up base RAM addr */`
112
113
114			`/*`
115			`* Determine size of RAM, then set up initial stack.`
116			`*/`
117			`move.l #MEM_SIZE, %a0`
118
119			`move.l %a0, %d0 /* Mem end addr is in a0 */`
120			`move.l %d0, %sp /* Set up initial stack ptr */`
121			`move.l %d0, _ramend /* Set end ram addr */`
122
123			`/*`
124			`* Enable CPU internal cache.`
125			`*/`
126			`move.l #0x01000000, %d0 /* invalidate whole cache */`
127			`movec %d0,%CACR`
128			`nop`
129			`move.l #0x0000c000, %d0 /* Set SDRAM cached only */`
130			`movec %d0, %ACR0`
131			`move.l #0x00000000, %d0 /* No other regions cached */`
132			`movec %d0, %ACR1`
133
134			`/* Enable cache */`
135			`move.l #0xa0000200, %d0`
136			`movec %d0,%CACR`
137			`nop`
138
139			`/*`
140			`* Move ROM filesystem above bss :-)`
141			`*/`
142			`lea.l _sbss, %a0 /* Get start of bss */`
143			`lea.l _ebss, %a1 /* Set up destination */`
144			`move.l %a0, %a2 /* Copy of bss start */`
145
146			`move.l 8(%a0), %d0 /* Get size of ROMFS */`
147			`addq.l #8, %d0 /* Allow for rounding */`
148			`and.l #0xfffffffc, %d0 /* Whole words */`
149
150			`add.l %d0, %a0 /* Copy from end */`
151			`add.l %d0, %a1 /* Copy from end */`
152			`move.l %a1, _ramstart /* Set start of ram */`
153
154			`_copy_romfs:`
155			`move.l -(%a0), %d0 /* Copy dword */`
156			`move.l %d0, -(%a1)`
157			`cmp.l %a0, %a2 /* Check if at end */`
158			`bne _copy_romfs`
159
160			`/*`
161			`* Zero out the bss region.`
162			`*/`
163			`lea.l _sbss, %a0 /* Get start of bss */`
164			`lea.l _ebss, %a1 /* Get end of bss */`
165			`clr.l %d0 /* Set value */`
166			`_clear_bss:`
167			`move.l %d0, (%a0)+ /* Clear each word */`
168			`cmp.l %a0, %a1 /* Check if at end */`
169			`bne _clear_bss`
170
171			`/*`
172			`* Assember start up done, start code proper.`
173			`*/`
174			`jsr start_kernel /* Start Linux kernel */`
175
176			`_exit:`
177			`jmp _exit /* Should never get here */`
178
179			`/*****************************************************************************/`

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[/] [or1k/] [trunk/] [uclinux/] [uClinux-2.0.x/] [arch/] [m68knommu/] [platform/] [5307/] [NETtel/] [crt0_ram.S] - Blame information for rev 1765