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[/] [or1k/] [trunk/] [uclinux/] [uClinux-2.0.x/] [arch/] [m68knommu/] [platform/] [68EZ328/] [ads/] [crt0_rom.S] - Blame information for rev 1775

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/* arch/m68knommu/platform/68EZ328/ads_flash-head.S
 *
 * Copyright (C) 1999  Vladimir Gurevich 
 *                     Bear & Hare Software, Inc.
 *
 * Based on: arch/m68knommu/platform/68EZ328/pilot-head.S
 * Copyright (C) 1998  D. Jeff Dionne ,
 *                     Kenneth Albanowski ,
 *                     The Silver Hammer Group, Ltd.
 */
 
        .global _stext
        .global _start
        .global __bss_start
        .global _ramend
 
#define ASSEMBLY
 
#include 
#include 
 
        .text
_start:
_stext:
        /*
         * Program the basic registers. Only those registers that
         * are required at startup should be initialized with the
         * values required for startup. All other registers should
         * be initialized by related components.
         */
/*
 * Use dual mapping of the CPU register space and allow access to them
 * from the user mode (this is the default, anyway). Also enable bus
 * timeout watchdog.
 */
#define SCR_INIT (SCR_DMAP | SCR_BETEN)
 
/*
 * Disable the watchdog timer for now
 */
#define WATCHDOG_INIT 0
 
/*
 * Connect internal chip functions to those pins that are required for
 * startup. Device drivers will do the rest
 */
 
/*
 * Port B. We need:
 *       CSC[01]/RAS[01] and CSD[01]/CAS[01] for our 2 DRAM  chips
 */
#define PBSEL_INIT (~(PB_CSC0_RAS0 | \
                      PB_CSC1_RAS1 | \
                      PB_CSD0_CAS0 | \
                      PB_CSD1_CAS1))
 
/*
 * Port E. We need
 *      DWE    for DRAM Write Enable
 *      RXD    RS-232 receive
 *      TXD    RS-232 Transmit
 *      RTS    RS-232 RTS
 *      CTS    RS-232 CTS
 */
#define PESEL_INIT (~(PE_DWE | PE_RXD | PE_TXD | PE_RTS | PE_CTS))
 
/*
 * Port F. We need
 *      CSA1    to address the second FLASH chip
 */
#define PFSEL_INIT (~(PF_CSA1))
 
/*
 * In-circuit emulation should be disabled
 */
#define ICEMCR_INIT (ICEMCR_HMDIS)
 
        moveb   #SCR_INIT,      SCR_ADDR
        movew   #WATCHDOG_INIT, WATCHDOG_ADDR
        moveb   #PBSEL_INIT,    PBSEL_ADDR
        moveb   #PESEL_INIT,    PESEL_ADDR
        moveb   #PFSEL_INIT,    PFSEL_ADDR
        movew   #ICEMCR_INIT,   ICEMCR_ADDR
        moveb   #0x40,          IVR_ADDR    /* Use 0x40-0x47 for IRQ 0-7 */
        movel   #0x00FFFFFF,    IMR_ADDR    /* Mask all h/w interrupts */
 
        /*
         * Program Chip selects & DRAM controller
         *
         * CSA[01]           FLASH      10200000 -- 10200000
         * CAS[01]/RAS[01]   DRAM       00000000 -- 00400000
         */
 
#define CSGBA_INIT (0x10000000 >> 13)      /* FLASH starts at 0x10000000 */
#define CSGBD_INIT (0x00000000 >> 13)      /* DRAM  starts at 0x00000000 */
 
#define CSA_INIT \
        (CSA_FLASH              |       /* CSA controls FLASH memory */ \
         CSA_BSW                |       /* 16-bit bus Width */          \
         PUT_FIELD(CSA_WS, 2)   |       /* 2 Wait States */             \
         PUT_FIELD(CSA_SIZ, 3)  |       /* Total FLASH size is 2*1M */  \
         CSA_EN)                        /* Enable it */
 
#define CSD_INIT \
        (CSD_DRAM               |       /* CSD Controls DRAM */         \
         CSD_BSW                |       /* 16-bit bus width */          \
         PUT_FIELD(CSD_WS, 1)   |       /* 1 Wait State */              \
         PUT_FIELD(CSD_SIZ, 6)  |       /* The board has 2*2MB DRAM*/   \
         CSD_EN)                        /* Enable it */
 
#define DRAMMC_INIT \
        (DRAMMC_ROW12_PA23      |       /* PA23 -> MD12 */      \
         DRAMMC_ROW11           |       /* PA22 -> MD11 */      \
         DRAMMC_ROW10           |       /* PA21 -> MD10 */      \
         DRAMMC_ROW9            |       /* PA19 -> MD9  */      \
         DRAMMC_ROW8)                   /* PA20 -> MD8  */
 
#define DRAMC_INIT \
        (DRAMC_EN               |       /* Enable DRAM controller */    \
         DRAMC_EDO              |       /* We have EDO DRAM */          \
         PUT_FIELD(DRAMC_WS, 1) |       /* 1 Wait State */              \
         DRAMC_LPR              |       /* Low-Power Refresh Enable */  \
         DRAMC_RST              |       /* Reset Burst Refresh Enable */\
         DRAMC_DWE)                     /* DRAM Write Enable */
 
        movew   #CSGBA_INIT,  CSGBA_ADDR        /* FLASH */
        movew   #CSA_INIT,    CSA_ADDR
 
        movew   #DRAMMC_INIT, DRAMMC_ADDR       /* DRAM */
        movew   #DRAMC_INIT,  DRAMC_ADDR
        movew   #CSGBD_INIT,  CSGBD_ADDR
        movew   #CSD_INIT,    CSD_ADDR
 
        /*
         * Program the UART (115200 cs8 -parenb -cstopb -crtscts */
         */
#define PLLCR_INIT \
        (PUT_FIELD(PLLCR_SYSCLK_SEL, 4) | PUT_FIELD(PLLCR_LCDCLK_SEL, 4))
 
#define USTCNT_INIT \
        (USTCNT_UEN | USTCNT_RXEN | USTCNT_TXEN | USTCNT_8_7)
 
#define UBAUD_INIT \
        (PUT_FIELD(UBAUD_DIVIDE, 0) | PUT_FIELD(UBAUD_PRESCALER, 0x38))
 
#define UTX_INIT \
        (UTX_NOCTS)
 
        movew   #(USTCNT_UEN | USTCNT_RXEN), USTCNT_ADDR
        tstw    USTCNT_ADDR
        movew   #USTCNT_INIT, USTCNT_ADDR
        movew   #PLLCR_INIT,  PLLCR_ADDR
        movew   #UBAUD_INIT,  UBAUD_ADDR
        moveb   #(UTX_INIT>>8),    UTX_ADDR
 
        movew   #0x2700, %sr
 
        /*
         * Here we start doing some real things
         */
        moveq   #13, %d7                /* '\r' */
        jsr putc
 
        moveq   #10, %d7                /* '\n' */
        jsr putc
 
        moveq   #65, %d7                /* 'A' */
        jsr putc
 
        movew   #16384, %d0  /* PLL settle wait loop */
L0:
        subw    #1, %d0
        bne     L0
 
        moveq   #66, %d7                /* 'B' */
        jsr     putc
 
        moveal  #__bss_start, %a0
        moveal  #end, %a1
 
        /* Copy 0 to %a0 until %a0 == %a1 */
L1:
        movel   #0, %a0@+
        cmpal   %a0, %a1
        bhi     L1
 
        moveq   #67, %d7                /* 'C' */
        jsr     putc
 
        /* Copy data segment from ROM to RAM */
        moveal  #__data_rom_start, %a0
        moveal  #__data_start, %a1
        moveal  #__data_end, %a2
        moveq   #68, %d7
        jsr     putc                    /* 'D' */
 
        /* Copy %a0 to %a1 until %a1 == %a2 */
L2:
        movel   %a0@+, %d0
        movel   %d0, %a1@+
        cmpal   %a1, %a2
        bhi     L2
 
        moveq   #69, %d7                /* 'E' */
        jsr     putc
 
        pea     0
        pea     env
        pea     %sp@(4)
        pea     0
 
        moveq   #70, %d7                /* 'F' */
        jsr     putc
 
 
lp:
        jsr     start_kernel
        jmp lp
_exit:
 
        jmp     _exit
 
 
putc:
        moveb   %d7,UTX_TXDATA_ADDR
pclp:
        movew   UTX_ADDR, %d7
        andw    #UTX_TX_AVAIL, %d7
        beq     pclp
        rts
 
        .data
env:
        .long   0
        .text

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[/] [or1k/] [trunk/] [uclinux/] [uClinux-2.0.x/] [arch/] [m68knommu/] [platform/] [68EZ328/] [ads/] [crt0_rom.S] - Blame information for rev 1775

Line No.	Rev	Author	Line
1	199	simons	`/* arch/m68knommu/platform/68EZ328/ads_flash-head.S`
2			`*`
3			`* Copyright (C) 1999 Vladimir Gurevich`
4			`* Bear & Hare Software, Inc.`
5			`*`
6			`* Based on: arch/m68knommu/platform/68EZ328/pilot-head.S`
7			`* Copyright (C) 1998 D. Jeff Dionne ,`
8			`* Kenneth Albanowski ,`
9			`* The Silver Hammer Group, Ltd.`
10			`*/`
11
12			`.global _stext`
13			`.global _start`
14			`.global __bss_start`
15			`.global _ramend`
16
17			`#define ASSEMBLY`
18
19			`#include`
20			`#include`
21
22			`.text`
23			`_start:`
24			`_stext:`
25			`/*`
26			`* Program the basic registers. Only those registers that`
27			`* are required at startup should be initialized with the`
28			`* values required for startup. All other registers should`
29			`* be initialized by related components.`
30			`*/`
31			`/*`
32			`* Use dual mapping of the CPU register space and allow access to them`
33			`* from the user mode (this is the default, anyway). Also enable bus`
34			`* timeout watchdog.`
35			`*/`
36			`#define SCR_INIT (SCR_DMAP \| SCR_BETEN)`
37
38			`/*`
39			`* Disable the watchdog timer for now`
40			`*/`
41			`#define WATCHDOG_INIT 0`
42
43			`/*`
44			`* Connect internal chip functions to those pins that are required for`
45			`* startup. Device drivers will do the rest`
46			`*/`
47
48			`/*`
49			`* Port B. We need:`
50			`* CSC[01]/RAS[01] and CSD[01]/CAS[01] for our 2 DRAM chips`
51			`*/`
52			`#define PBSEL_INIT (~(PB_CSC0_RAS0 \| \`
53			`PB_CSC1_RAS1 \| \`
54			`PB_CSD0_CAS0 \| \`
55			`PB_CSD1_CAS1))`
56
57			`/*`
58			`* Port E. We need`
59			`* DWE for DRAM Write Enable`
60			`* RXD RS-232 receive`
61			`* TXD RS-232 Transmit`
62			`* RTS RS-232 RTS`
63			`* CTS RS-232 CTS`
64			`*/`
65			`#define PESEL_INIT (~(PE_DWE \| PE_RXD \| PE_TXD \| PE_RTS \| PE_CTS))`
66
67			`/*`
68			`* Port F. We need`
69			`* CSA1 to address the second FLASH chip`
70			`*/`
71			`#define PFSEL_INIT (~(PF_CSA1))`
72
73			`/*`
74			`* In-circuit emulation should be disabled`
75			`*/`
76			`#define ICEMCR_INIT (ICEMCR_HMDIS)`
77
78			`moveb #SCR_INIT, SCR_ADDR`
79			`movew #WATCHDOG_INIT, WATCHDOG_ADDR`
80			`moveb #PBSEL_INIT, PBSEL_ADDR`
81			`moveb #PESEL_INIT, PESEL_ADDR`
82			`moveb #PFSEL_INIT, PFSEL_ADDR`
83			`movew #ICEMCR_INIT, ICEMCR_ADDR`
84			`moveb #0x40, IVR_ADDR /* Use 0x40-0x47 for IRQ 0-7 */`
85			`movel #0x00FFFFFF, IMR_ADDR /* Mask all h/w interrupts */`
86
87			`/*`
88			`* Program Chip selects & DRAM controller`
89			`*`
90			`* CSA[01] FLASH 10200000 -- 10200000`
91			`* CAS[01]/RAS[01] DRAM 00000000 -- 00400000`
92			`*/`
93
94			`#define CSGBA_INIT (0x10000000 >> 13) /* FLASH starts at 0x10000000 */`
95			`#define CSGBD_INIT (0x00000000 >> 13) /* DRAM starts at 0x00000000 */`
96
97			`#define CSA_INIT \`
98			`(CSA_FLASH \| /* CSA controls FLASH memory */ \`
99			`CSA_BSW \| /* 16-bit bus Width */ \`
100			`PUT_FIELD(CSA_WS, 2) \| /* 2 Wait States */ \`
101			`PUT_FIELD(CSA_SIZ, 3) \| /* Total FLASH size is 21M / \`
102			`CSA_EN) /* Enable it */`
103
104			`#define CSD_INIT \`
105			`(CSD_DRAM \| /* CSD Controls DRAM */ \`
106			`CSD_BSW \| /* 16-bit bus width */ \`
107			`PUT_FIELD(CSD_WS, 1) \| /* 1 Wait State */ \`
108			`PUT_FIELD(CSD_SIZ, 6) \| /* The board has 22MB DRAM/ \`
109			`CSD_EN) /* Enable it */`
110
111			`#define DRAMMC_INIT \`
112			`(DRAMMC_ROW12_PA23 \| /* PA23 -> MD12 */ \`
113			`DRAMMC_ROW11 \| /* PA22 -> MD11 */ \`
114			`DRAMMC_ROW10 \| /* PA21 -> MD10 */ \`
115			`DRAMMC_ROW9 \| /* PA19 -> MD9 */ \`
116			`DRAMMC_ROW8) /* PA20 -> MD8 */`
117
118			`#define DRAMC_INIT \`
119			`(DRAMC_EN \| /* Enable DRAM controller */ \`
120			`DRAMC_EDO \| /* We have EDO DRAM */ \`
121			`PUT_FIELD(DRAMC_WS, 1) \| /* 1 Wait State */ \`
122			`DRAMC_LPR \| /* Low-Power Refresh Enable */ \`
123			`DRAMC_RST \| /* Reset Burst Refresh Enable */\`
124			`DRAMC_DWE) /* DRAM Write Enable */`
125
126			`movew #CSGBA_INIT, CSGBA_ADDR /* FLASH */`
127			`movew #CSA_INIT, CSA_ADDR`
128
129			`movew #DRAMMC_INIT, DRAMMC_ADDR /* DRAM */`
130			`movew #DRAMC_INIT, DRAMC_ADDR`
131			`movew #CSGBD_INIT, CSGBD_ADDR`
132			`movew #CSD_INIT, CSD_ADDR`
133
134			`/*`
135			`* Program the UART (115200 cs8 -parenb -cstopb -crtscts */`
136			`*/`
137			`#define PLLCR_INIT \`
138			`(PUT_FIELD(PLLCR_SYSCLK_SEL, 4) \| PUT_FIELD(PLLCR_LCDCLK_SEL, 4))`
139
140			`#define USTCNT_INIT \`
141			`(USTCNT_UEN \| USTCNT_RXEN \| USTCNT_TXEN \| USTCNT_8_7)`
142
143			`#define UBAUD_INIT \`
144			`(PUT_FIELD(UBAUD_DIVIDE, 0) \| PUT_FIELD(UBAUD_PRESCALER, 0x38))`
145
146			`#define UTX_INIT \`
147			`(UTX_NOCTS)`
148
149			`movew #(USTCNT_UEN \| USTCNT_RXEN), USTCNT_ADDR`
150			`tstw USTCNT_ADDR`
151			`movew #USTCNT_INIT, USTCNT_ADDR`
152			`movew #PLLCR_INIT, PLLCR_ADDR`
153			`movew #UBAUD_INIT, UBAUD_ADDR`
154			`moveb #(UTX_INIT>>8), UTX_ADDR`
155
156			`movew #0x2700, %sr`
157
158			`/*`
159			`* Here we start doing some real things`
160			`*/`
161			`moveq #13, %d7 /* '\r' */`
162			`jsr putc`
163
164			`moveq #10, %d7 /* '\n' */`
165			`jsr putc`
166
167			`moveq #65, %d7 /* 'A' */`
168			`jsr putc`
169
170			`movew #16384, %d0 /* PLL settle wait loop */`
171			`L0:`
172			`subw #1, %d0`
173			`bne L0`
174
175			`moveq #66, %d7 /* 'B' */`
176			`jsr putc`
177
178			`moveal #__bss_start, %a0`
179			`moveal #end, %a1`
180
181			`/* Copy 0 to %a0 until %a0 == %a1 */`
182			`L1:`
183			`movel #0, %a0@+`
184			`cmpal %a0, %a1`
185			`bhi L1`
186
187			`moveq #67, %d7 /* 'C' */`
188			`jsr putc`
189
190			`/* Copy data segment from ROM to RAM */`
191			`moveal #__data_rom_start, %a0`
192			`moveal #__data_start, %a1`
193			`moveal #__data_end, %a2`
194			`moveq #68, %d7`
195			`jsr putc /* 'D' */`
196
197			`/* Copy %a0 to %a1 until %a1 == %a2 */`
198			`L2:`
199			`movel %a0@+, %d0`
200			`movel %d0, %a1@+`
201			`cmpal %a1, %a2`
202			`bhi L2`
203
204			`moveq #69, %d7 /* 'E' */`
205			`jsr putc`
206
207			`pea 0`
208			`pea env`
209			`pea %sp@(4)`
210			`pea 0`
211
212			`moveq #70, %d7 /* 'F' */`
213			`jsr putc`
214
215
216			`lp:`
217			`jsr start_kernel`
218			`jmp lp`
219			`_exit:`
220
221			`jmp _exit`
222
223
224			`putc:`
225			`moveb %d7,UTX_TXDATA_ADDR`
226			`pclp:`
227			`movew UTX_ADDR, %d7`
228			`andw #UTX_TX_AVAIL, %d7`
229			`beq pclp`
230			`rts`
231
232			`.data`
233			`env:`
234			`.long 0`
235			`.text`