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199 |
simons |
/*
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* arch/mips/kernel/head.S
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*
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* Copyright (C) 1994, 1995 Waldorf Electronics
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* Written by Ralf Baechle and Andreas Busse
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*
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* Head.S contains the MIPS exception handler and startup code.
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*/
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#include
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#include
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#include
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#include
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#include
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#include
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#include
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#include
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#define PAGE_SIZE 0x1000
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#define MODE_GLOBAL 0x0001 /* shared for all processes */
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#define MODE_ALIAS 0x0016 /* uncachable */
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.text
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.set mips3
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/*
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* This is space for the interrupt handlers.
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* They are located at virtual address KSEG[01] (physical 0x0)
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*/
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/*
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* TLB refill, EXL == 0
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*/
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.set noreorder
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.set noat
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LEAF(except_vec0)
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dmfc0 k1,CP0_CONTEXT
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dsra k1,1
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lwu k0,(k1) # May cause another exception
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lwu k1,4(k1)
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dsrl k0,6 # Convert to EntryLo format
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dsrl k1,6 # Convert to EntryLo format
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dmtc0 k0,CP0_ENTRYLO0
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dmtc0 k1,CP0_ENTRYLO1
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nop # Needed for R4[04]00 pipeline
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tlbwr
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nop # Needed for R4[04]00 pipeline
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nop
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nop
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eret
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/*
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* Workaround for R4000 bug. For explanation see MIPS
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* docs. Note that this is so obscure that it will almost
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* never happen. Well, but Mips writes about its bugs.
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*/
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nop
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eret
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END(except_vec0)
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/*
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* XTLB refill, EXL == 0
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* Should never be reached
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*/
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.org except_vec0+0x80
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LEAF(except_vec1)
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PANIC("XTLB Refill exception.\n")
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1: j 1b
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nop
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END(except_vec1)
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/*
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* Cache Error
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*/
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.org except_vec1+0x80
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LEAF(except_vec2)
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/*
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* Famous last words: unreached
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*/
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mfc0 a1,CP0_ERROREPC
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PRINT("Cache error exception: c0_errorepc == %08x\n")
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1: j 1b
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nop
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END(except_vec2)
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/*
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* General exception vector.
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*/
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.org except_vec2+0x80
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NESTED(except_vec3, 0, sp)
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.set noat
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/*
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* Register saving is delayed as long as we don't know
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* which registers really need to be saved.
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*/
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mfc0 k1,CP0_CAUSE
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la k0,exception_handlers
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/*
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* Next lines assumes that the used CPU type has max.
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* 32 different types of exceptions. We might use this
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* to implement software exceptions in the future.
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*/
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andi k1,0x7c
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addu k0,k1
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lw k0,(k0)
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NOP
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jr k0
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nop
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END(except_vec3)
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.set at
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/******************************************************************************/
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/*
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* Kernel entry
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*/
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.set noreorder
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NESTED(kernel_entry, 16, sp)
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/*
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* The following two symbols are used for kernel profiling.
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*/
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EXPORT(stext)
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EXPORT(_stext)
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#ifdef CONF_DISABLE_KSEG0_CACHING
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/*
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* Disable all caching for KSEG0. This option is useful
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* when cache trouble with drivers is suspected
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*/
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mfc0 t0,CP0_CONFIG
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ori t0,7
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xori t0,5
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mtc0 t0,CP0_CONFIG
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#endif
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/*
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* Clear BSS first so that there are no surprises...
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*/
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la t0,_edata
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la t1,_end
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sw zero,(t0)
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1: addiu t0,4
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bnel t0,t1,1b
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sw zero,(t0)
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/*
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* Initialize low level part of memory management
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* First flush the TLB to make sure that we don't get a
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* TLB shutdown during wire_mappings.
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*/
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jal tlbflush
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mtc0 zero,CP0_WIRED # delay slot
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jal wire_mappings
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nop
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/*
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* Stack for kernel and init
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*/
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la sp,init_user_stack+PAGE_SIZE-24
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la t0,init_kernel_stack+PAGE_SIZE
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sw t0,kernelsp
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/*
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* Disable coprocessors; set ST0_CU0 to indicate that
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* we're running on the kernel stack
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*/
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mfc0 t0,CP0_STATUS
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li t1,~(ST0_CU1|ST0_CU2|ST0_CU3)
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and t0,t1
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li t1,ST0_CU0
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or t0,ST0_CU0
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mtc0 t0,CP0_STATUS
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1: jal start_kernel
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nop # delay slot
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/*
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* Main should never return here, but
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* just in case, we know what happens.
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*/
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b 1b
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nop # delay slot
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END(kernel_entry)
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/*
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* wire_mappings - used to map hardware registers
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*/
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LEAF(wire_mappings)
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/*
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* Get base address of map0 table for the
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* the board we're running on
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*/
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la t0,boot_info
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lw t1,OFFSET_BOOTINFO_MACHTYPE(t0)
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la t0,map0table
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sll t1,PTRLOG # machtype used as index
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addu t0,t1
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lw t0,(t0) # get base address
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/*
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* Get number of wired TLB entries and
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* loop over selected map0 table.
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*/
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lw t1,(t0) # number of wired TLB entries
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move t2,zero # TLB entry counter
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addiu t3,t1,1 # wire one additional entry
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beqz t1,2f # null, exit
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mtc0 t3,CP0_WIRED # delay slot
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addiu t0,8
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1: lw t4,24(t0) # PageMask
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ld t5,0(t0) # entryHi
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ld t6,8(t0) # entryLo0
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ld t7,16(t0) # entryLo1
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addiu t2,1 # increment ctr
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mtc0 t2,CP0_INDEX # set TLB entry
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mtc0 t4,CP0_PAGEMASK
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dmtc0 t5,CP0_ENTRYHI
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dmtc0 t6,CP0_ENTRYLO0
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dmtc0 t7,CP0_ENTRYLO1
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addiu t0,32
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bne t1,t2,1b # next TLB entry
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tlbwi # delay slot
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/*
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* We use only 4k pages. Therefore the PageMask register
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* is expected to be setup for 4k pages.
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*/
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2: li t0,PM_4K
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mtc0 t0,CP0_PAGEMASK
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/*
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* Now map the pagetables
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*/
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mtc0 zero,CP0_INDEX
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la t0,TLB_ROOT
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dmtc0 t0,CP0_ENTRYHI
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la t0,swapper_pg_dir-KSEG1
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srl t0,6
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ori t0,(MODE_ALIAS|MODE_GLOBAL) # uncachable, dirty, valid
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dmtc0 t0,CP0_ENTRYLO0
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li t0,MODE_GLOBAL
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dmtc0 t0,CP0_ENTRYLO1
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nop
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tlbwi # delayed
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/*
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* Load the context register with a value that allows
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* it to be used as fast as possible in tlb exceptions.
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* It is expected that this register's content will
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* NEVER be changed.
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*/
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li t0,TLBMAP
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dsll t0,1
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dmtc0 t0,CP0_CONTEXT
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jr ra # delay slot
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nop
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END(wire_mappings)
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.data
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/*
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* Build an entry for table of wired entries
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*/
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#define MAPDATA(q1,q2,q3,w1) \
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.quad q1; \
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.quad q2; \
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.quad q3; \
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.word w1; \
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.word 0
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| 265 |
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| 266 |
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/*
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* Initial mapping tables for supported Mips boards.
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* First item is always the number of wired TLB entries,
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* following by EntryHi/EntryLo pairs and page mask.
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* Since everything must be quad-aligned (8) we insert
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* some dummy zeros.
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*/
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| 273 |
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| 274 |
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/*
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| 275 |
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* Address table of mapping tables for supported Mips boards.
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| 276 |
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* Add your own stuff here but don't forget to define your
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| 277 |
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* target system in bootinfo.h
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| 278 |
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*/
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| 279 |
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| 280 |
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map0table: PTR map0_dummy # machtype = unknown
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| 281 |
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PTR map0_rpc # Deskstation rPC44
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| 282 |
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PTR map0_tyne # Deskstation Tyne
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| 283 |
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PTR map0_pica61 # Acer Pica-61
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| 284 |
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PTR map0_magnum4000 # MIPS Magnum 4000PC (RC4030)
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| 285 |
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| 286 |
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map0_dummy: .word 0 # 0 entries
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| 287 |
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| 288 |
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.align 3
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| 289 |
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/*
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| 290 |
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* Initial mappings for Deskstation rPC boards.
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* RB: Untested goodie - I don't have such a board.
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| 292 |
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*/
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| 293 |
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map0_rpc: .word 2 # no. of wired TLB entries
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| 294 |
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.word 0 # pad for alignment
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| 295 |
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| 296 |
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MAPDATA(0xffffffffe0000000, 0x04020017, 0x00000001, PM_1M) # VESA DMA cache
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| 297 |
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MAPDATA(0xffffffffe2000000, 0x24000017, 0x04000017, PM_16M) # VESA I/O and memory space
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| 298 |
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| 299 |
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/*
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| 300 |
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* Initial mappings for Deskstation Tyne boards.
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| 301 |
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*/
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| 302 |
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map0_tyne: .word 2 # no. of wired TLB entries
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| 303 |
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.word 0 # pad for alignment
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| 304 |
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| 305 |
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MAPDATA(0xffffffffe0000000, 0x04020017, 0x00000001, PM_1M) # VESA DMA cache
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| 306 |
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MAPDATA(0xffffffffe2000000, 0x24000017, 0x04000017, PM_16M) # VESA I/O and memory space
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| 307 |
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| 308 |
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/*
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| 309 |
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* Initial mapping for ACER PICA-61 boards.
|
| 310 |
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* FIXME: These are rather preliminary since many drivers, such as serial,
|
| 311 |
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* parallel, scsi and ethernet need some changes to distinguish between "local"
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| 312 |
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* (built-in) and "optional" (ISA/PCI) I/O hardware. Local video ram is mapped
|
| 313 |
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* to the same location as the bios maps it to. Console driver has been changed
|
| 314 |
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* accordingly (new video type: VIDEO_TYPE_PICA_S3).
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| 315 |
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* FIXME: Remove or merge some of the mappings.
|
| 316 |
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*/
|
| 317 |
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map0_pica61: .word 7 # no. wired TLB entries
|
| 318 |
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.word 0 # dummy
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| 319 |
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| 320 |
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MAPDATA(0xffffffffe0000000, 0x02000017, 0x00000001, PM_64K) # Local I/O space
|
| 321 |
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MAPDATA(0xffffffffe0100000, 0x03c00017, 0x00000001, PM_4K) # Interrupt source register
|
| 322 |
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MAPDATA(0xffffffffe0200000, 0x01800017, 0x01804017, PM_1M) # Local video control
|
| 323 |
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MAPDATA(0xffffffffe0400000, 0x01808017, 0x0180c017, PM_1M) # Extended video control
|
| 324 |
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MAPDATA(0xffffffffe0800000, 0x01000017, 0x01010017, PM_4M) # Local video memory (BIOS mapping)
|
| 325 |
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MAPDATA(0xffffffffe2000000, 0x02400017, 0x02440017, PM_16M) # ISA I/O and ISA memory space (both 16M)
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| 326 |
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MAPDATA(0xffffffffffffe000, 0x00000001, 0x0001ffd7, PM_4K) # PCR (???)
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| 327 |
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|
| 328 |
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/*
|
| 329 |
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* Initial mapping for Mips Magnum 4000PC systems.
|
| 330 |
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* Do you believe me now that the Acer and Mips boxes are nearly the same ? :-)
|
| 331 |
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* FIXME: Remove or merge some of the mappings.
|
| 332 |
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*/
|
| 333 |
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| 334 |
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map0_magnum4000:
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| 335 |
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.word 8 # no. wired TLB entries
|
| 336 |
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.word 0 # dummy
|
| 337 |
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|
| 338 |
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MAPDATA(0xffffffffe1000000, 0x03ffc013, 0x00000001, 0x7e000) # 0
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| 339 |
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MAPDATA(0xffffffffe0000000, 0x02000017, 0x00000001, 0x1e000) # 1 local I/O
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| 340 |
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MAPDATA(0xffffffffe0100000, 0x03c00017, 0x00000001, 0) # 2 IRQ source
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| 341 |
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MAPDATA(0xffffffffe0200000, 0x01800017, 0x01804017, 0x1fe000) # 3 local video ctrl
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| 342 |
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MAPDATA(0xffffffffe0400000, 0x01808017, 0x0180c017, 0x1fe000) # 4 ext. video ctrl
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| 343 |
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MAPDATA(0xffffffffe0800000, 0x01000017, 0x01010017, 0x7fe000) # 5 local video mem.
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| 344 |
|
|
MAPDATA(0xffffffffe2000000, 0x02400017, 0x02440017, 0x1ffe000) # 6 ISA I/O and mem.
|
| 345 |
|
|
MAPDATA(0xffffffffffffe000, 0x00000001, 0x0001ffd7, 0) # 7 PCR
|
| 346 |
|
|
|
| 347 |
|
|
|
| 348 |
|
|
.text
|
| 349 |
|
|
|
| 350 |
|
|
.org 0x1000
|
| 351 |
|
|
.globl swapper_pg_dir
|
| 352 |
|
|
swapper_pg_dir = . + (KSEG1-KSEG0)
|
| 353 |
|
|
|
| 354 |
|
|
/*
|
| 355 |
|
|
* The page tables are initialized to only 4MB here - the final page
|
| 356 |
|
|
* tables are set up later depending on memory size.
|
| 357 |
|
|
*/
|
| 358 |
|
|
.org 0x2000
|
| 359 |
|
|
EXPORT(pg0)
|
| 360 |
|
|
|
| 361 |
|
|
.org 0x3000
|
| 362 |
|
|
EXPORT(empty_bad_page)
|
| 363 |
|
|
|
| 364 |
|
|
.org 0x4000
|
| 365 |
|
|
EXPORT(empty_bad_page_table)
|
| 366 |
|
|
|
| 367 |
|
|
.org 0x5000
|
| 368 |
|
|
EXPORT(empty_zero_page)
|
| 369 |
|
|
|
| 370 |
|
|
.org 0x6000
|
| 371 |
|
|
EXPORT(invalid_pte_table)
|
| 372 |
|
|
|
| 373 |
|
|
.org 0x7000
|
| 374 |
|
|
|
| 375 |
|
|
EXPORT(cache_error_buffer)
|
| 376 |
|
|
.fill 32*4,1,0
|
| 377 |
|
|
|
| 378 |
|
|
.data
|
| 379 |
|
|
EXPORT(kernelsp)
|
| 380 |
|
|
PTR 0
|
