OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [uclinux/] [uClinux-2.0.x/] [arch/] [or32/] [board/] [reset.S] - Blame information for rev 862

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 862 simons 
#include
2 
#include
3 
#include
4 
 
5 
#undef IC_ENABLE
6 
#define IC_ENABLE 1
7 
 
8 
        .extern _reset_support
9 
        .extern _src_beg
10 
        .extern _dst_beg
11 
        .extern _dst_end
12 
        .extern _c_reset
13 
 
14 
        .global start
15 
        .global _lolev_ie
16 
        .global _str
17 
 
18 
        .section .stack
19 
        .space 0x30000
20 
_stack:
21 
 
22 
        .section .reset, "a"
23 
 
24 
        .org 0x100
25 
start:
26 
_reset:
27 
        l.addi  r3,r0,SPR_SR_SM
28 
        l.mtspr r0,r3,SPR_SR
29 
        l.movhi r3,hi(_start)
30 
        l.ori   r3,r3,lo(_start)
31 
        l.jr    r3
32 
        l.nop
33 
 
34 
        .section .text
35 
 
36 
_start:
37 
        l.jal   init_mc
38 
        l.nop
39 
 
40 
.if IC_ENABLE
41 
        l.jal   _ic_enable
42 
        l.nop
43 
.endif
44 
 
45 
        /* Copy form flash to sram */
46 
.if 1
47 
        l.movhi r3,hi(_src_beg)
48 
        l.ori   r3,r3,lo(_src_beg)
49 
        l.movhi r4,hi(_dst_beg)
50 
        l.ori   r4,r4,lo(_dst_beg)
51 
        l.movhi r5,hi(_dst_end)
52 
        l.ori   r5,r5,lo(_dst_end)
53 
        l.sub   r5,r5,r4
54 
        l.sfeqi r5,0
55 
        l.bf    2f
56 
        l.nop
57 
1:      l.lwz   r6,0(r3)
58 
        l.sw    0(r4),r6
59 
        l.addi  r3,r3,4
60 
        l.addi  r4,r4,4
61 
        l.addi  r5,r5,-4
62 
        l.sfgtsi r5,0
63 
        l.bf    1b
64 
        l.nop
65 
2:
66 
.endif
67 
 
68 
        l.movhi r1,hi(_stack)
69 
        l.addi  r1,r1,lo(_stack)
70 
        l.addi  r1,r1,-4
71 
 
72 
        l.movhi r3,hi(_linux_start)
73 
        l.ori   r3,r3,lo(_linux_start)
74 
        l.addi  r4,r0,0
75 
        l.jal   _decompress
76 
        l.nop
77 
 
78 
        l.addi  r2,r0,0x100
79 
        l.jr    r2
80 
        l.addi  r2,r0,0
81 
 
82 
init_mc:
83 
 
84 
        l.movhi r3,hi(MC_BASE_ADD)
85 
        l.ori   r3,r3,lo(MC_BASE_ADD)
86 
 
87 
        l.addi  r4,r3,MC_CSC(0)
88 
        l.movhi r5,hi(FLASH_BASE_ADD)
89 
        l.srai  r5,r5,5
90 
        l.ori   r5,r5,0x0025
91 
        l.sw    0(r4),r5
92 
 
93 
        l.addi  r4,r3,MC_TMS(0)
94 
        l.movhi r5,hi(FLASH_TMS_VAL)
95 
        l.ori   r5,r5,lo(FLASH_TMS_VAL)
96 
        l.sw    0(r4),r5
97 
 
98 
        l.addi  r4,r3,MC_BA_MASK
99 
        l.addi  r5,r0,MC_MASK_VAL
100 
        l.sw    0(r4),r5
101 
 
102 
        l.addi  r4,r3,MC_CSR
103 
        l.movhi r5,hi(MC_CSR_VAL)
104 
        l.ori   r5,r5,lo(MC_CSR_VAL)
105 
        l.sw    0(r4),r5
106 
 
107 
        l.addi  r4,r3,MC_TMS(1)
108 
        l.movhi r5,hi(SDRAM_TMS_VAL)
109 
        l.ori   r5,r5,lo(SDRAM_TMS_VAL)
110 
        l.sw    0(r4),r5
111 
 
112 
        l.addi  r4,r3,MC_CSC(1)
113 
        l.movhi r5,hi(SDRAM_BASE_ADD)
114 
        l.srai  r5,r5,5
115 
        l.ori   r5,r5,0x0411
116 
        l.sw    0(r4),r5
117 
 
118 
        l.jr    r9
119 
        l.nop
120 
 
121 
_ic_enable:
122 
        /* Disable IC */
123 
        l.mfspr r13,r0,SPR_SR
124 
        l.addi  r11,r0,-1
125 
        l.xori  r11,r11,SPR_SR_ICE
126 
        l.and   r11,r13,r11
127 
        l.mtspr r0,r11,SPR_SR
128 
 
129 
        /* Invalidate IC */
130 
        l.addi  r13,r0,0
131 
        l.addi  r11,r0,IC_SIZE
132 
1:
133 
        l.mtspr r0,r13,SPR_ICBIR
134 
        l.sfne  r13,r11
135 
        l.bf    1b
136 
        l.addi  r13,r13,IC_LINE
137 
 
138 
        /* Enable IC */
139 
        l.mfspr r13,r0,SPR_SR
140 
        l.ori   r13,r13,SPR_SR_ICE
141 
        l.mtspr r0,r13,SPR_SR
142 
        l.nop
143 
        l.nop
144 
        l.nop
145 
        l.nop
146 
        l.nop
147 
 
148 
        l.jr    r9
149 
        l.nop
150 
 
151 
        .global __print
152 
__print:
153 
        l.lwz   r3,0(r1)
154 
        l.addi  r4,r1,4
155 
#       l.sys   202
156 
        l.nop 3
157 
        l.jr    r9
158 
        l.nop
159 
 
160 
 
161 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.