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MEMORY
        {
        romvec : ORIGIN = 0x04000000, LENGTH = 0x2000
        flash  : ORIGIN = 0x04002000, LENGTH = 0x00800000 - 0x2000
        eflash : ORIGIN = 0x04800000, LENGTH = 0
        ramvec : ORIGIN = 0x00000000, LENGTH = 0x00002000
        ram    : ORIGIN = 0x00002000, LENGTH = 0x00800000 - 0x2000
        eram   : ORIGIN = 0x00800000, LENGTH = 0
        }
 
SECTIONS
{
        .romvec :
        {
        __romvec = . ;
        *(.romvec)
        } > romvec
 
        .text :
        {
        ___rom_start = . ;
        text_start = . ;
        *(.text)
        __etext = . ;
        } > flash
 
        .initrd :
        {
        __initrd_start = . ;
        *(.initrd)
        __initrd_end = . ;
        ___data_rom_start = . ;
        } > flash
 
        .eflash :
        {
        __flashend = . ;
        } > eflash
 
        .data :
        AT ( ADDR (.initrd) + SIZEOF (.initrd))
        {
        __ramstart = . ;
        __sdata = . ;
        ___data_start = . ;
        *(.data)
        __edata = . ;
        __end_data = . ;
        __data_end = . ;
        edata = ALIGN( 0x10 ) ;
        } > ram
 
        .bss :
        {
        __sbss = ALIGN( 0x10 ) ;
        ___bss_start = ALIGN( 0x10 ) ;
        *(.bss)
        *(COMMON)
        __ebss = . ;
        ___bss_end = . ;
        end = ALIGN( 0x10 ) ;
        __end = ALIGN( 0x10 ) ;
        } > ram
 
        .ramvec :
        AT ( ADDR (.initrd) + SIZEOF (.initrd) + SIZEOF (.data))
        {
        __ramvec_start = . ;
        *(.ramvec)
        __ramvec_end = . ;
        } > ramvec
 
        .eram :
        {
        __ramend = . ;
        } > eram
}

Line No.	Rev	Author	Line
1	666	simons	`MEMORY`
2			`{`
3			`romvec : ORIGIN = 0x04000000, LENGTH = 0x2000`
4	753	simons	`flash : ORIGIN = 0x04002000, LENGTH = 0x00800000 - 0x2000`
5			`eflash : ORIGIN = 0x04800000, LENGTH = 0`
6	666	simons	`ramvec : ORIGIN = 0x00000000, LENGTH = 0x00002000`
7	718	simons	`ram : ORIGIN = 0x00002000, LENGTH = 0x00800000 - 0x2000`
8			`eram : ORIGIN = 0x00800000, LENGTH = 0`
9	666	simons	`}`
10
11			`SECTIONS`
12			`{`
13			`.romvec :`
14			`{`
15			`__romvec = . ;`
16			`*(.romvec)`
17			`} > romvec`
18	743	simons
19	666	simons	`.text :`
20			`{`
21			`___rom_start = . ;`
22			`text_start = . ;`
23			`*(.text)`
24			`__etext = . ;`
25			`} > flash`
26	743	simons
27	666	simons	`.initrd :`
28			`{`
29			`__initrd_start = . ;`
30			`*(.initrd)`
31			`__initrd_end = . ;`
32			`___data_rom_start = . ;`
33			`} > flash`
34	743	simons
35	666	simons	`.eflash :`
36			`{`
37			`__flashend = . ;`
38			`} > eflash`
39	743	simons
40	666	simons	`.data :`
41			`AT ( ADDR (.initrd) + SIZEOF (.initrd))`
42			`{`
43			`__ramstart = . ;`
44			`__sdata = . ;`
45			`___data_start = . ;`
46			`*(.data)`
47			`__edata = . ;`
48			`__end_data = . ;`
49			`__data_end = . ;`
50			`edata = ALIGN( 0x10 ) ;`
51			`} > ram`
52	743	simons
53	666	simons	`.bss :`
54			`{`
55			`__sbss = ALIGN( 0x10 ) ;`
56			`___bss_start = ALIGN( 0x10 ) ;`
57			`*(.bss)`
58			`*(COMMON)`
59			`__ebss = . ;`
60			`___bss_end = . ;`
61			`end = ALIGN( 0x10 ) ;`
62			`__end = ALIGN( 0x10 ) ;`
63			`} > ram`
64	743	simons
65	666	simons	`.ramvec :`
66			`AT ( ADDR (.initrd) + SIZEOF (.initrd) + SIZEOF (.data))`
67			`{`
68			`__ramvec_start = . ;`
69			`*(.ramvec)`
70			`__ramvec_end = . ;`
71			`} > ramvec`
72	743	simons
73	666	simons	`.eram :`
74			`{`
75			`__ramend = . ;`
76			`} > eram`
77			`}`

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[/] [or1k/] [trunk/] [uclinux/] [uClinux-2.0.x/] [arch/] [or32/] [board/] [rom.ld] - Blame information for rev 753