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[/] [or1k/] [trunk/] [uclinux/] [uClinux-2.0.x/] [arch/] [or32/] [kernel/] [head.S] - Blame information for rev 753

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Line No. Rev Author Line
1 666 simons 
#include
2 
#include
3 
#include
4 
#include
5 
#include
6 
 
7 
#define RAM 0
8 
 
9 
        .global __text_start
10 
        .global __main
11 
        .global ___bss_start
12 
        .global __bss_end
13 
        .global __ram_start
14 
        .global __ram_end
15 
        .global __rom_start
16 
        .global __rom_end
17 
        .global ___data_start
18 
        .global __data_end
19 
        .global ___data_rom_start
20 
 
21 
        .global splash_bits
22 
        .global __start
23 
        .global __stext
24 
 
25 
        .global __switch
26 
        .global _putc
27 
 
28 
#define SAVE_REGS(mark) \
29 
        l.addi  r1,r1,-(INT_FRAME_SIZE); \
30 
        l.mfspr r3,r0,SPR_EPCR_BASE; \
31 
        l.sw    PC(r1),r3; \
32 
        l.mfspr r3,r0,SPR_ESR_BASE; \
33 
        l.sw    SR(r1),r3; \
34 
        l.lwz   r3,4(r0); /* Read r1 (sp) from tmp location */ \
35 
        l.sw    SP(r1),r3; \
36 
        l.sw    GPR2(r1),r2; \
37 
        l.sw    GPR4(r1),r4; \
38 
        l.sw    GPR5(r1),r5; \
39 
        l.sw    GPR6(r1),r6; \
40 
        l.sw    GPR7(r1),r7; \
41 
        l.sw    GPR8(r1),r8; \
42 
        l.sw    GPR9(r1),r9; \
43 
        l.sw    GPR10(r1),r10; \
44 
        l.sw    GPR11(r1),r11; \
45 
        l.sw    GPR12(r1),r12; \
46 
        l.sw    GPR13(r1),r13; \
47 
        l.sw    GPR14(r1),r14; \
48 
        l.sw    GPR15(r1),r15; \
49 
        l.sw    GPR16(r1),r16; \
50 
        l.sw    GPR17(r1),r17; \
51 
        l.sw    GPR18(r1),r18; \
52 
        l.sw    GPR19(r1),r19; \
53 
        l.sw    GPR20(r1),r20; \
54 
        l.sw    GPR21(r1),r21; \
55 
        l.sw    GPR22(r1),r22; \
56 
        l.sw    GPR23(r1),r23; \
57 
        l.sw    GPR24(r1),r24; \
58 
        l.sw    GPR25(r1),r25; \
59 
        l.sw    GPR26(r1),r26; \
60 
        l.sw    GPR27(r1),r27; \
61 
        l.sw    GPR28(r1),r28; \
62 
        l.sw    GPR29(r1),r29; \
63 
        l.sw    GPR30(r1),r30; \
64 
        l.sw    GPR31(r1),r31; \
65 
        l.lwz   r3,0(r0);  /* Read r3 from tmp location */ \
66 700 simons 
        l.sw    GPR3(r1),r3; \
67 
        l.sw    ORIG_GPR3(r1),r3; \
68 681 simons 
        l.sw    RESULT(r1),r0
69 666 simons 
 
70 
#define SAVE_INT_REGS(mark) \
71 
        l.sw    0(r0),r3;       /* Temporary store r3 to add 0!!! */ \
72 
        l.sw    4(r0),r1;       /* Temporary store r1 to add 4!!! */ \
73 
        l.mfspr r3,r0,SPR_SR; \
74 
        l.addi  r1,r0,-1; \
75 
        l.xori  r1,r1,(SPR_SR_IEE | SPR_SR_TEE); \
76 
        l.and   r3,r3,r1; \
77 
        l.mtspr r0,r3,SPR_SR; \
78 
        l.lwz   r1,4(r0); \
79 
        l.mfspr r3,r0,SPR_ESR_BASE; /* Interrupt from user/system mode */ \
80 
        l.andi  r3,r3,SPR_SR_SM; \
81 
        l.sfeqi r3,SPR_SR_SM; \
82 
        l.bf    10f; /* SIMON */ /* Branch if SUPV */ \
83 
        l.nop; \
84 
        l.movhi r3,hi(_current_set); \
85 
        l.ori   r3,r3,lo(_current_set); \
86 681 simons 
        l.lwz   r3,0(r3); \
87 666 simons 
        l.sw    TSS+TSS_USP(r3),r1; \
88 
        l.mfspr r1,r0,SPR_EPCR_BASE; \
89 
        l.sw    TSS+TSS_PC(r3),r1; \
90 
        l.lwz   r1,TSS+TSS_KSP(r3); \
91 
        l.addi  r1,r1,-(INT_FRAME_SIZE); \
92 
        l.sw    TSS+TSS_REGS(r3),r1; \
93 
        l.lwz   r1,TSS+TSS_KSP(r3); \
94 
10:     SAVE_REGS(mark)
95 
 
96 
#define RETURN_FROM_INT(mark) \
97 
90:     l.addi  r4,r0,-1;       /* Disable interrupts */ \
98 
        l.xori  r4,r4,(SPR_SR_IEE | SPR_SR_TEE); \
99 
        l.mfspr r3,r0,SPR_SR; \
100 
        l.and   r3,r3,r4; \
101 
        l.mtspr r0,r3,SPR_SR; \
102 
        l.movhi r2,hi(_intr_count); \
103 
        l.ori   r2,r2,lo(_intr_count); \
104 681 simons 
        l.lwz   r3,0(r2); \
105 666 simons 
        l.sfeqi r3,0; \
106 
        l.bnf   00f; \
107 
        l.nop; \
108 
        l.movhi r4,hi(_bh_mask); \
109 
        l.ori   r4,r4,lo(_bh_mask); \
110 681 simons 
        l.lwz   r4,0(r4); \
111 666 simons 
        l.movhi r5,hi(_bh_active); \
112 
        l.ori   r5,r5,lo(_bh_active); \
113 681 simons 
        l.lwz   r5,0(r5); \
114 666 simons 
        l.and   r4,r4,r5; \
115 
        l.sfeqi r4,0; \
116 
        l.bf    00f; \
117 
        l.nop; \
118 
        l.addi  r3,r3,1; \
119 681 simons 
        l.sw    0(r2),r3; \
120 666 simons 
        l.jal   _do_bottom_half; \
121 
        l.nop; \
122 
        l.movhi r2,hi(_intr_count); \
123 
        l.ori   r2,r2,lo(_intr_count); \
124 681 simons 
        l.lwz   r3,0(r2); \
125 666 simons 
        l.addi  r3,r3,-1; \
126 
        l.sw    0(r2),r3; \
127 
00:     l.lwz   r2,SR(r1); \
128 
        l.andi  r3,r2,SPR_SR_SM; \
129 
        l.sfeqi r3,0; \
130 
        l.bnf   10f; /* SIMON */ /* Branch if SUPV */ \
131 
        l.nop; \
132 
        l.andi  r3,r2,SPR_SR_ICE; \
133 
        l.sfeqi r3,0; \
134 
        l.bf    05f; /* Branch if IC disabled */ \
135 
        l.nop; \
136 
        l.jal   _ic_invalidate; \
137 
        l.nop; \
138 
05:     l.movhi r3,hi(_current_set); /* need to save kernel stack pointer */ \
139 
        l.ori   r3,r3,lo(_current_set); \
140 681 simons 
        l.lwz   r3,0(r3); \
141 666 simons 
        l.addi  r4,r1,INT_FRAME_SIZE; \
142 
        l.sw    TSS+TSS_KSP(r3),r4; \
143 
        l.lwz   r4,STATE(r3); /* If state != 0, can't run */ \
144 
        l.sfeqi r4,0; \
145 
        l.bf    06f; \
146 
        l.nop; \
147 
        l.jal   _schedule; \
148 
        l.nop; \
149 
        l.j     90b; \
150 
        l.nop; \
151 
06:     l.lwz   r4,COUNTER(r3); \
152 
        l.sfeqi r4,0; \
153 
        l.bnf   07f; \
154 
        l.nop; \
155 
        l.jal   _schedule; \
156 
        l.nop; \
157 
        l.j     90b; \
158 
        l.nop; \
159 
07:     l.addi  r5,r0,-1; \
160 
        l.lwz   r4,BLOCKED(r3); /* Check for pending unblocked signals */ \
161 
        l.xor   r4,r4,r5; \
162 
        l.lwz   r5,SIGNAL(r3); \
163 
        l.and   r5,r5,r4; \
164 
        l.sfeqi r5,0; \
165 
        l.bf    10f; \
166 
        l.nop; \
167 
        l.addi  r3,r4,0; \
168 
        l.addi  r4,r1,0; \
169 
        l.jal   _do_signal; \
170 
        l.nop; \
171 
10:     l.lwz   r3,PC(r1); \
172 
        l.mtspr r0,r3,SPR_EPCR_BASE; \
173 
        l.lwz   r3,SR(r1); \
174 
        l.mtspr r0,r3,SPR_ESR_BASE; \
175 
        l.lwz   r2,GPR2(r1); \
176 
        l.lwz   r3,GPR3(r1); \
177 
        l.lwz   r4,GPR4(r1); \
178 
        l.lwz   r5,GPR5(r1); \
179 
        l.lwz   r6,GPR6(r1); \
180 
        l.lwz   r7,GPR7(r1); \
181 
        l.lwz   r8,GPR8(r1); \
182 
        l.lwz   r9,GPR9(r1); \
183 
        l.lwz   r10,GPR10(r1); \
184 
        l.lwz   r11,GPR11(r1); \
185 
        l.lwz   r12,GPR12(r1); \
186 
        l.lwz   r13,GPR13(r1); \
187 
        l.lwz   r14,GPR14(r1); \
188 
        l.lwz   r15,GPR15(r1); \
189 
        l.lwz   r16,GPR16(r1); \
190 
        l.lwz   r17,GPR17(r1); \
191 
        l.lwz   r18,GPR18(r1); \
192 
        l.lwz   r19,GPR19(r1); \
193 
        l.lwz   r20,GPR20(r1); \
194 
        l.lwz   r21,GPR21(r1); \
195 
        l.lwz   r22,GPR22(r1); \
196 
        l.lwz   r23,GPR23(r1); \
197 
        l.lwz   r24,GPR24(r1); \
198 
        l.lwz   r25,GPR25(r1); \
199 
        l.lwz   r26,GPR26(r1); \
200 
        l.lwz   r27,GPR27(r1); \
201 
        l.lwz   r28,GPR28(r1); \
202 
        l.lwz   r29,GPR29(r1); \
203 
        l.lwz   r30,GPR30(r1); \
204 
        l.lwz   r31,GPR31(r1); \
205 
        l.lwz   r1,SP(r1); \
206 
        l.rfe; \
207 
        l.nop
208 
 
209 
        .bss
210 
sys_stack:
211 
        .space  4*4096
212 
sys_stack_top:
213 
#if !(RAM)
214 
        .section .romvec
215 
        .org    0x100
216 
 
217 753 simons 
        l.nop
218 666 simons 
        l.movhi r3,hi(__start)
219 753 simons 
        l.movhi r3,hi(MC_BASE_ADD)
220 
        l.ori   r3,r3,MC_BA_MASK
221 
        l.addi  r5,r0,0x00
222 
        l.sw    0(r3),r5
223 
 
224 
        l.movhi r3,hi(__start)
225 666 simons 
        l.ori   r3,r3,lo(__start)
226 
        l.jr    r3
227 
        l.nop
228 
 
229 
        .org    0x200
230 
 
231 
        l.nop
232 
        l.rfe
233 
        l.nop
234 
 
235 
        .org    0x300
236 
 
237 
        l.nop
238 
        l.j     _dpfault
239 
        l.nop
240 
 
241 
        .org    0x400
242 
 
243 
        l.nop
244 
        l.j     _ipfault
245 
        l.nop
246 
 
247 
        .org    0x500
248 
 
249 
        l.nop
250 
        l.j     _tick
251 
        l.nop
252 
 
253 743 simons 
        .org    0x600
254 
 
255 
        l.nop
256 
        l.j     _align
257 
        l.nop
258 
 
259 666 simons 
        .org    0x800
260 
 
261 
        l.nop
262 
        l.j     _ext_int
263 
        l.nop
264 
 
265 
        .org    0x900
266 
 
267 
        l.nop
268 
        l.j     _dtlbmiss
269 
        l.nop
270 
 
271 
        .org    0xa00
272 
 
273 
        l.nop
274 
        l.j     _itlbmiss
275 
        l.nop
276 
 
277 
        .org    0xb00
278 
 
279 
        l.nop
280 
        l.j     _sys_call
281 
        l.nop
282 
 
283 
        .org    0xc00
284 
 
285 
        l.nop
286 
        l.j     _sys_call
287 
        l.nop
288 
#endif
289 
        .section .ramvec
290 
        .org    0x100
291 
 
292 
        l.movhi r3,hi(__start)
293 
        l.ori   r3,r3,lo(__start)
294 
        l.jr    r3
295 
        l.nop
296 
 
297 
        .org    0x200
298 
 
299 
        l.nop
300 
        l.rfe
301 
        l.nop
302 
 
303 
        .org    0x300
304 
 
305 
        l.nop
306 
        l.j     _dpfault
307 
        l.nop
308 
 
309 
        .org    0x400
310 
 
311 
        l.nop
312 
        l.j     _ipfault
313 
        l.nop
314 
 
315 
        .org    0x500
316 
 
317 
        l.nop
318 
        l.j     _tick
319 
        l.nop
320 
 
321 743 simons 
        .org    0x600
322 
 
323 
        l.nop
324 
        l.j     _align
325 
        l.nop
326 
 
327 666 simons 
        .org    0x800
328 
 
329 
        l.nop
330 
        l.j     _ext_int
331 
        l.nop
332 
 
333 
        .org    0x900
334 
 
335 
        l.nop
336 
        l.j     _dtlbmiss
337 
        l.nop
338 
 
339 
        .org    0xa00
340 
 
341 
        l.nop
342 
        l.j     _itlbmiss
343 
        l.nop
344 
 
345 
        .org    0xb00
346 
 
347 
        l.nop
348 
        l.j     _sys_call
349 
        l.nop
350 
 
351 
        .org    0xc00
352 
 
353 
        l.nop
354 
        l.j     _sys_call
355 
        l.nop
356 
 
357 
 
358 
        .text
359 
__start:
360 
__stext:
361 
        l.addi  r3,r0,SPR_SR_SM
362 
        l.mtspr r0,r3,SPR_SR
363 
#if 1
364 
 
365 
        /* Init uart */
366 
        l.jal   _ua_init
367 
        l.nop
368 
 
369 
        /* Jump to flash original location */
370 
        l.movhi r3,hi(__flsh_start)
371 
        l.ori   r3,r3,lo(__flsh_start)
372 
        l.jr    r3
373 
        l.nop
374 
 
375 
__flsh_start:
376 
 
377 
#if MC_INIT
378 
        l.movhi r3,hi(MC_BASE_ADD)
379 
        l.ori   r3,r3,lo(MC_BASE_ADD)
380 753 simons 
 
381 666 simons 
        l.addi  r4,r3,MC_CSC(0)
382 
        l.movhi r5,hi(FLASH_BASE_ADD)
383 
        l.srai  r5,r5,5
384 753 simons 
        l.ori   r5,r5,0x0025
385 666 simons 
        l.sw    0(r4),r5
386 753 simons 
 
387 666 simons 
        l.addi  r4,r3,MC_TMS(0)
388 753 simons 
        l.movhi r5,hi(FLASH_TMS_VAL)
389 
        l.ori   r5,r5,lo(FLASH_TMS_VAL)
390 
        l.sw    0(r4),r5
391 
 
392 666 simons 
        l.addi  r4,r3,MC_BA_MASK
393 753 simons 
        l.addi  r5,r0,MC_MASK_VAL
394 666 simons 
        l.sw    0(r4),r5
395 753 simons 
 
396 
        l.addi  r4,r3,MC_CSR
397 
        l.movhi r5,hi(MC_CSR_VAL)
398 
        l.ori   r5,r5,lo(MC_CSR_VAL)
399 
        l.sw    0(r4),r5
400 
 
401 
        l.addi  r4,r3,MC_TMS(1)
402 
        l.movhi r5,hi(SDRAM_TMS_VAL)
403 
        l.ori   r5,r5,lo(SDRAM_TMS_VAL)
404 
        l.sw    0(r4),r5
405 
 
406 666 simons 
        l.addi  r4,r3,MC_CSC(1)
407 753 simons 
        l.movhi r5,hi(SDRAM_BASE_ADD)
408 666 simons 
        l.srai  r5,r5,5
409 753 simons 
        l.ori   r5,r5,0x0411
410 666 simons 
        l.sw    0(r4),r5
411 753 simons 
#ifdef FBMEM_BASE_ADD
412 
        l.addi  r4,r3,MC_CSC(2)
413 
        l.movhi r5,hi(FBMEM_BASE_ADD)
414 
        l.srai  r5,r5,5
415 
        l.ori   r5,r5,0x0005
416 
        l.sw    0(r4),r5
417 666 simons 
 
418 753 simons 
        l.addi  r4,r3,MC_TMS(2)
419 666 simons 
        l.movhi r5,0xffff
420 
        l.ori   r5,r5,0xffff
421 
        l.sw    0(r4),r5
422 
#endif
423 
#endif
424 753 simons 
#endif
425 666 simons 
 
426 
#if ICACHE
427 
        l.jal   _ic_enable
428 
        l.nop
429 
#endif
430 
 
431 
#if DCACHE
432 
        l.jal   _dc_enable
433 
        l.nop
434 
#endif
435 
 
436 
        l.movhi r1, hi(sys_stack_top)           /* stack setup */
437 
        l.ori   r1,r1,lo(sys_stack_top)
438 
 
439 
#if 1
440 
        /* Copy data segment from ROM to RAM */
441 
        l.movhi r3, hi(___data_rom_start)
442 
        l.ori   r3,r3,lo(___data_rom_start)
443 
 
444 
        l.movhi r4, hi(___data_start)
445 
        l.ori   r4,r4,lo(___data_start)
446 
 
447 
        l.movhi r5, hi(__data_end)
448 
        l.ori   r5,r5,lo(__data_end)
449 
 
450 
        /* Copy %r3 to %r4 until %r4 == %r5 */
451 
1:
452 
        l.sfeq  r3,r4
453 
        l.bf    3f
454 
        l.nop
455 
2:
456 
        l.sfgeu r4,r5
457 
        l.bf    1f
458 
        l.nop
459 
        l.lwz   r8,0(r3)
460 
        l.sw    0(r4),r8
461 
        l.addi  r3,r3,4
462 
        l.j     2b
463 
        l.addi  r4,r4,4
464 
 
465 
        /* Copy ramvec segment from ROM to RAM */
466 
1:
467 
        l.movhi r4, hi(__ramvec_start)
468 
        l.ori   r4,r4,lo(__ramvec_start)
469 
 
470 
        l.movhi r5, hi(__ramvec_end)
471 
        l.ori   r5,r5,lo(__ramvec_end)
472 
 
473 
        /* Copy %r3 to %r4 until %r4 == %r5 */
474 
2:
475 
        l.sfgeu r4,r5
476 
        l.bf    1f
477 
        l.nop
478 
        l.lwz   r8,0(r3)
479 
        l.sw    0(r4),r8
480 
        l.addi  r3,r3,4
481 
        l.j     2b
482 
        l.addi  r4,r4,4
483 
#if 0
484 
        /* Copy initrd segment from ROM to RAM */
485 
1:
486 
        l.movhi r4, hi(__initrd_start)
487 
        l.ori   r4,r4,lo(__initrd_start)
488 
 
489 
        l.movhi r5, hi(__initrd_end)
490 
        l.ori   r5,r5,lo(__initrd_end)
491 
 
492 
        /* Copy %r3 to %r4 until %r4 == %r5 */
493 
2:
494 
        l.sfgeu r4,r5
495 
        l.bf    1f
496 
        l.nop
497 
        l.lwz   r8,0(r3)
498 
        l.sw    0(r4),r8
499 
        l.addi  r3,r3,4
500 
        l.j     2b
501 
        l.addi  r4,r4,4
502 
#endif
503 
#endif
504 
1:
505 
3:
506 
        l.movhi r3, hi(___bss_start)
507 
        l.ori   r3,r3,lo(___bss_start)
508 
 
509 
        l.movhi r4, hi(end)
510 
        l.ori   r4,r4,lo(end)
511 
 
512 
        /* Copy 0 to %r3 until %r3 == %r4 */
513 
1:
514 
        l.sfgeu r3,r4
515 
        l.bf    1f
516 
        l.nop
517 
        l.sw    0(r3),r0
518 
        l.j     1b
519 
        l.addi  r3,r3,4
520 
1:
521 
 
522 
#if IMMU
523 
        l.jal   _immu_enable
524 
        l.nop
525 
#endif
526 
 
527 
#if DMMU
528 
        l.jal   _dmmu_enable
529 
        l.nop
530 
#endif
531 
 
532 
        l.j     _start_kernel
533 
        l.nop
534 
 
535 
_exit:
536 
        l.j     _exit
537 
        l.nop
538 
 
539 
_dpfault:
540 
 
541 
 
542 
_ipfault:
543 
 
544 
_tick:
545 
        SAVE_INT_REGS(0x0500)
546 
        l.addi  r3,r1,0
547 
        l.jal   _timer_interrupt
548 
        l.nop
549 
        RETURN_FROM_INT(0x500)
550 
 
551 743 simons 
_align:
552 
        l.addi  r1,r1,-128
553 
        l.sw    0x08(r1),r2
554 
        l.sw    0x0c(r1),r3
555 
        l.sw    0x10(r1),r4
556 
        l.sw    0x14(r1),r5
557 
        l.sw    0x18(r1),r6
558 
        l.sw    0x1c(r1),r7
559 
        l.sw    0x20(r1),r8
560 
        l.sw    0x24(r1),r9
561 
        l.sw    0x28(r1),r10
562 
        l.sw    0x2c(r1),r11
563 
        l.sw    0x30(r1),r12
564 
        l.sw    0x34(r1),r13
565 
        l.sw    0x38(r1),r14
566 
        l.sw    0x3c(r1),r15
567 
        l.sw    0x40(r1),r16
568 
        l.sw    0x44(r1),r17
569 
        l.sw    0x48(r1),r18
570 
        l.sw    0x4c(r1),r19
571 
        l.sw    0x50(r1),r20
572 
        l.sw    0x54(r1),r21
573 
        l.sw    0x58(r1),r22
574 
        l.sw    0x5c(r1),r23
575 
        l.sw    0x60(r1),r24
576 
        l.sw    0x64(r1),r25
577 
        l.sw    0x68(r1),r26
578 
        l.sw    0x6c(r1),r27
579 
        l.sw    0x70(r1),r28
580 
        l.sw    0x74(r1),r29
581 
        l.sw    0x78(r1),r30
582 
        l.sw    0x7c(r1),r31
583 
 
584 
        l.mfspr r2,r0,SPR_EEAR_BASE     /* Load the efective addres */
585 
        l.mfspr r5,r0,SPR_EPCR_BASE     /* Load the insn address */
586 
 
587 
        l.lwz   r3,0(r5)                /* Load insn */
588 
        l.srli  r4,r3,26                /* Shift left to get the insn opcode */
589 
 
590 
        l.sfeqi r4,0x00                 /* Check if the load/store insn is in delay slot */
591 
        l.bf    jmp
592 
        l.sfeqi r4,0x01
593 
        l.bf    jmp
594 
        l.sfeqi r4,0x03
595 
        l.bf    jmp
596 
        l.sfeqi r4,0x04
597 
        l.bf    jmp
598 
        l.sfeqi r4,0x11
599 
        l.bf    jr
600 
        l.sfeqi r4,0x12
601 
        l.bf    jr
602 
        l.nop
603 
        l.j     1f
604 
        l.addi  r5,r5,4                 /* Increment PC to get return insn address */
605 
 
606 
jmp:
607 
        l.slli  r4,r3,6                 /* Get the signed extended jump length */
608 
        l.srai  r4,r4,4
609 
 
610 
        l.lwz   r3,4(r5)                /* Load the real load/store insn */
611 
 
612 
        l.add   r5,r5,r4                /* Calculate jump target address */
613 
 
614 
        l.j     1f
615 
        l.srli  r4,r3,26                /* Shift left to get the insn opcode */
616 
 
617 
jr:
618 
        l.slli  r4,r3,9                 /* Shift to get the reg nb */
619 
        l.andi  r4,r4,0x7c
620 
 
621 
        l.lwz   r3,4(r5)                /* Load the real load/store insn */
622 
 
623 
        l.add   r4,r4,r1                /* Load the jump register value from the stack */
624 
        l.lwz   r5,0(r4)
625 
 
626 
        l.srli  r4,r3,26                /* Shift left to get the insn opcode */
627 
 
628 
 
629 
1:      l.mtspr r0,r5,SPR_EPCR_BASE
630 
 
631 
        l.sfeqi r4,0x26
632 
        l.bf    lhs
633 
        l.sfeqi r4,0x25
634 
        l.bf    lhz
635 
        l.sfeqi r4,0x22
636 
        l.bf    lws
637 
        l.sfeqi r4,0x21
638 
        l.bf    lwz
639 
        l.sfeqi r4,0x37
640 
        l.bf    sh
641 
        l.sfeqi r4,0x35
642 
        l.bf    sw
643 
        l.nop
644 
 
645 
1:      l.j     1b                      /* I don't know what to do */
646 
        l.nop
647 
 
648 
lhs:    l.lbs   r5,0(r2)
649 
        l.slli  r5,r5,8
650 
        l.lbz   r6,1(r2)
651 
        l.or    r5,r5,r6
652 
        l.srli  r4,r3,19
653 
        l.andi  r4,r4,0x7c
654 
        l.add   r4,r4,r1
655 
        l.j     align_end
656 
        l.sw    0(r4),r5
657 
 
658 
lhz:    l.lbz   r5,0(r2)
659 
        l.slli  r5,r5,8
660 
        l.lbz   r6,1(r2)
661 
        l.or    r5,r5,r6
662 
        l.srli  r4,r3,19
663 
        l.andi  r4,r4,0x7c
664 
        l.add   r4,r4,r1
665 
        l.j     align_end
666 
        l.sw    0(r4),r5
667 
 
668 
lws:    l.lbs   r5,0(r2)
669 
        l.slli  r5,r5,24
670 
        l.lbz   r6,1(r2)
671 
        l.slli  r6,r6,16
672 
        l.or    r5,r5,r6
673 
        l.lbz   r6,2(r2)
674 
        l.slli  r6,r6,8
675 
        l.or    r5,r5,r6
676 
        l.lbz   r6,3(r2)
677 
        l.or    r5,r5,r6
678 
        l.srli  r4,r3,19
679 
        l.andi  r4,r4,0x7c
680 
        l.add   r4,r4,r1
681 
        l.j     align_end
682 
        l.sw    0(r4),r5
683 
 
684 
lwz:    l.lbz   r5,0(r2)
685 
        l.slli  r5,r5,24
686 
        l.lbz   r6,1(r2)
687 
        l.slli  r6,r6,16
688 
        l.or    r5,r5,r6
689 
        l.lbz   r6,2(r2)
690 
        l.slli  r6,r6,8
691 
        l.or    r5,r5,r6
692 
        l.lbz   r6,3(r2)
693 
        l.or    r5,r5,r6
694 
        l.srli  r4,r3,19
695 
        l.andi  r4,r4,0x7c
696 
        l.add   r4,r4,r1
697 
        l.j     align_end
698 
        l.sw    0(r4),r5
699 
 
700 
sh:
701 
        l.srli  r4,r3,9
702 
        l.andi  r4,r4,0x7c
703 
        l.add   r4,r4,r1
704 
        l.lwz   r5,0(r4)
705 
        l.sb    1(r2),r5
706 
        l.slli  r5,r5,8
707 
        l.j     align_end
708 
        l.sb    0(r2),r5
709 
 
710 
sw:
711 
        l.srli  r4,r3,9
712 
        l.andi  r4,r4,0x7c
713 
        l.add   r4,r4,r1
714 
        l.lwz   r5,0(r4)
715 
        l.sb    3(r2),r5
716 
        l.slli  r5,r5,8
717 
        l.sb    2(r2),r5
718 
        l.slli  r5,r5,8
719 
        l.sb    1(r2),r5
720 
        l.slli  r5,r5,8
721 
        l.j     align_end
722 
        l.sb    0(r2),r5
723 
 
724 
align_end:
725 
        l.lwz   r2,0x08(r1)
726 
        l.lwz   r3,0x0c(r1)
727 
        l.lwz   r4,0x10(r1)
728 
        l.lwz   r5,0x14(r1)
729 
        l.lwz   r6,0x18(r1)
730 
        l.lwz   r7,0x1c(r1)
731 
        l.lwz   r8,0x20(r1)
732 
        l.lwz   r9,0x24(r1)
733 
        l.lwz   r10,0x28(r1)
734 
        l.lwz   r11,0x2c(r1)
735 
        l.lwz   r12,0x30(r1)
736 
        l.lwz   r13,0x34(r1)
737 
        l.lwz   r14,0x38(r1)
738 
        l.lwz   r15,0x3c(r1)
739 
        l.lwz   r16,0x40(r1)
740 
        l.lwz   r17,0x44(r1)
741 
        l.lwz   r18,0x48(r1)
742 
        l.lwz   r19,0x4c(r1)
743 
        l.lwz   r20,0x50(r1)
744 
        l.lwz   r21,0x54(r1)
745 
        l.lwz   r22,0x58(r1)
746 
        l.lwz   r23,0x5c(r1)
747 
        l.lwz   r24,0x60(r1)
748 
        l.lwz   r25,0x64(r1)
749 
        l.lwz   r26,0x68(r1)
750 
        l.lwz   r27,0x6c(r1)
751 
        l.lwz   r28,0x70(r1)
752 
        l.lwz   r29,0x74(r1)
753 
        l.lwz   r30,0x78(r1)
754 
        l.lwz   r31,0x7c(r1)
755 
        l.addi  r1,r1,128
756 
        l.rfe
757 
 
758 
 
759 666 simons 
_ext_int:
760 
        SAVE_INT_REGS(0x0800)
761 
        l.addi  r3,r1,0
762 
        l.jal   _handle_IRQ
763 
        l.nop
764 
        RETURN_FROM_INT(0x800)
765 
 
766 
_dtlbmiss:
767 
        l.sw    0(r0),r3
768 
        l.sw    4(r0),r4
769 
        l.sw    8(r0),r5
770 
        l.mfspr r3,r0,SPR_EEAR_BASE
771 
        l.srli  r4,r3,DMMU_PAGE_ADD_BITS
772 
        l.andi  r4,r4,DMMU_SET_ADD_MASK
773 
        l.addi  r5,r0,-1
774 
        l.xori  r5,r5,DMMU_PAGE_ADD_MASK
775 
        l.and   r5,r3,r5
776 
        l.ori   r5,r5,SPR_DTLBMR_V
777 
        l.mtspr r4,r5,SPR_DTLBMR_BASE(0)
778 
        l.movhi r5,hi(SPR_DTLBTR_PPN)
779 
        l.ori   r5,r5,lo(SPR_DTLBTR_PPN)
780 
        l.and   r5,r3,r5
781 
        l.ori   r5,r5,DTLBTR_NO_LIMIT
782 
        l.movhi r3,0x8000
783 
        l.sfgeu r5,r3
784 
        l.bnf   1f
785 
        l.nop
786 
        l.ori   r5,r5,SPR_DTLBTR_CI
787 
1:      l.mtspr r4,r5,SPR_DTLBTR_BASE(0)
788 
        l.lwz   r3,0(r0)
789 
        l.lwz   r4,4(r0)
790 
        l.lwz   r5,8(r0)
791 
        l.rfe
792 
        l.nop
793 
 
794 
 
795 
_itlbmiss:
796 
        l.sw    0(r0),r3
797 
        l.sw    4(r0),r4
798 
        l.sw    8(r0),r5
799 
        l.mfspr r3,r0,SPR_EEAR_BASE
800 
        l.srli  r4,r3,IMMU_PAGE_ADD_BITS
801 
        l.andi  r4,r4,IMMU_SET_ADD_MASK
802 
        l.addi  r5,r0,-1
803 
        l.xori  r5,r5,IMMU_PAGE_ADD_MASK
804 
        l.and   r5,r3,r5
805 
        l.ori   r5,r5,SPR_ITLBMR_V
806 
        l.mtspr r4,r5,SPR_ITLBMR_BASE(0)
807 
        l.movhi r5,hi(SPR_ITLBTR_PPN)
808 
        l.ori   r5,r5,lo(SPR_ITLBTR_PPN)
809 
        l.and   r5,r3,r5
810 
        l.ori   r5,r5,ITLBTR_NO_LIMIT
811 
        l.mtspr r4,r5,SPR_ITLBTR_BASE(0)
812 
        l.lwz   r3,0(r0)
813 
        l.lwz   r4,4(r0)
814 
        l.lwz   r5,8(r0)
815 
        l.rfe
816 
        l.nop
817 
 
818 
_sys_call:
819 
        SAVE_INT_REGS(0x0c00)
820 681 simons 
        /* EPCR was pointing to l.sys instruction, we have to incremet it */
821 
/*      l.lwz   r2,PC(r1)
822 
        l.addi  r2,r2,4
823 666 simons 
        l.sw    PC(r1),r2
824 681 simons 
*/
825 
        l.sfeqi r11,0x7777              /* Special case for 'sys_sigreturn' */
826 
        l.bnf   10f
827 
        l.nop
828 
        l.jal   _sys_sigreturn
829 
        l.addi  r3,r1,0
830 
        l.sfgtsi r11,0                  /* Check for restarted system call */
831 
        l.bf    99f
832 
        l.nop
833 
        l.j     20f
834 
        l.nop
835 
10:
836 666 simons 
        l.movhi r2,hi(_sys_call_table)
837 
        l.ori   r2,r2,lo(_sys_call_table)
838 
        l.slli  r11,r11,2
839 
        l.add   r2,r2,r11
840 
        l.lwz   r2,0(r2)
841 
        l.addi  r8,r1,0                 /* regs pointer */
842 
        l.jalr  r2
843 
        l.nop
844 
        l.sw    GPR11(r1),r11           /* save return value */
845 681 simons 
20:
846 
        l.sw    RESULT(r1),r11          /* save result */
847 
        l.sfgesi r11,0
848 
        l.bf    99f
849 
        l.nop
850 
        l.sfeqi r11,-ERESTARTNOHAND
851 
        l.bnf   22f
852 
        l.nop
853 
        l.addi  r11,r0,EINTR
854 
22:
855 
        l.sw    RESULT(r1),r11
856 
99:
857 666 simons 
        RETURN_FROM_INT(0xc00)
858 
 
859 
/*
860 
 * This routine switches between two different tasks.  The process
861 
 * state of one is saved on its kernel stack.  Then the state
862 
 * of the other is restored from its kernel stack.  The memory
863 
 * management hardware is updated to the second process's state.
864 
 * Finally, we can return to the second process, via the 'return'.
865 
 *
866 
 * Note: there are two ways to get to the "going out" portion
867 
 * of this code; either by coming in via the entry (_switch)
868 
 * or via "fork" which must set up an environment equivalent
869 
 * to the "_switch" path.  If you change this (or in particular, the
870 
 * SAVE_REGS macro), you'll have to change the fork code also.
871 
 */
872 
__switch:
873 
        l.sw    0(r0),r3                /* Temporary store r3 to add 0!!! */
874 
        l.sw    4(r0),r1                /* Temporary store r1 to add 4!!! */
875 
        l.mtspr r0,r9,SPR_EPCR_BASE     /* Link register to EPCR */
876 
        l.mfspr r3,r0,SPR_SR            /* From SR to ESR */
877 
        l.mtspr r0,r3,SPR_ESR_BASE
878 
        SAVE_REGS(0x0FF0)
879 
        l.sw    TSS_KSP(r3),r1          /* Set old stack pointer */
880 
        l.lwz   r1,TSS_KSP(r4)          /* Load new stack pointer */
881 
        RETURN_FROM_INT(0xFF0)
882 
 
883 
_ua_init:
884 740 simons 
        l.movhi r3,hi(UART_BASE_ADD)
885 666 simons 
 
886 
        l.addi r4,r0,0x7
887 
        l.sb 0x2(r3),r4
888 
 
889 
        l.addi r4,r0,0x0
890 
        l.sb 0x1(r3),r4
891 
 
892 
        l.addi r4,r0,0x3
893 
        l.sb 0x3(r3),r4
894 
 
895 
        l.lbz  r5,3(r3)
896 
        l.ori r4,r5,0x80
897 
        l.sb  0x3(r3),r4
898 
        l.sb  0x1(r3),r0
899 
        l.addi  r4,r0,0x82
900 
        l.sb  0x0(r3),r4
901 
        l.sb  0x3(r3),r5
902 
 
903 
        l.jr  r9
904 
        l.nop
905 
 
906 
_putc:
907 740 simons 
        l.movhi r4,hi(UART_BASE_ADD)
908 666 simons 
 
909 
        l.addi  r6,r0,0x20
910 
1:      l.lbz   r5,5(r4)
911 
        l.andi  r5,r5,0x20
912 
        l.sfeq  r5,r6
913 
        l.bnf   1b
914 
        l.nop
915 
 
916 
        l.sb    0(r4),r3
917 
 
918 
        l.addi  r6,r0,0x60
919 
1:      l.lbz   r5,5(r4)
920 
        l.andi  r5,r5,0x60
921 
        l.sfeq  r5,r6
922 
        l.bnf   1b
923 
        l.nop
924 
 
925 
        l.jr    r9
926 
        l.nop
927 
 
928 
 
929 
        .data
930 
env:
931 
        .long   0

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