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[/] [or1k/] [trunk/] [uclinux/] [uClinux-2.0.x/] [arch/] [sparc/] [kernel/] [trampoline.S] - Blame information for rev 1775

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1 199 simons 
/* $Id: trampoline.S,v 1.1.1.1 2001-09-10 07:44:02 simons Exp $
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 * mp.S:  Multiprocessor low-level routines on the Sparc.
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 *
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 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
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 */
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#include
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#include
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#include
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#include
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#include
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#include
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#include
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        .text
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        .align 4
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/* When we start up a cpu for the first time it enters this routine.
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 * This initializes the chip from whatever state the prom left it
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 * in and sets PIL in %psr to 15, no irqs.
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 */
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        .globl C_LABEL(sparc_cpu_startup)
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C_LABEL(sparc_cpu_startup):
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cpu1_startup:
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        sethi   %hi(C_LABEL(trapbase_cpu1)), %g7
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        or      %g7, %lo(C_LABEL(trapbase_cpu1)), %g7
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        sethi   %hi(C_LABEL(cpu1_stack)), %g6
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        or      %g6, %lo(C_LABEL(cpu1_stack)), %g6
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        b       1f
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         nop
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cpu2_startup:
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        sethi   %hi(C_LABEL(trapbase_cpu2)), %g7
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        or      %g7, %lo(C_LABEL(trapbase_cpu2)), %g7
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        sethi   %hi(C_LABEL(cpu2_stack)), %g6
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        or      %g6, %lo(C_LABEL(cpu2_stack)), %g6
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        b       1f
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         nop
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cpu3_startup:
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        sethi   %hi(C_LABEL(trapbase_cpu3)), %g7
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        or      %g7, %lo(C_LABEL(trapbase_cpu3)), %g7
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        sethi   %hi(C_LABEL(cpu3_stack)), %g6
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        or      %g6, %lo(C_LABEL(cpu3_stack)), %g6
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        b       1f
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         nop
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1:
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        /* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
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        set     (PSR_PIL | PSR_S | PSR_PS), %g1
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        wr      %g1, 0x0, %psr          ! traps off though
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        WRITE_PAUSE
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        /* Our %wim is one behind CWP */
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        mov     2, %g1
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        wr      %g1, 0x0, %wim
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        WRITE_PAUSE
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        /* This identifies "this cpu". */
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        wr      %g7, 0x0, %tbr
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        WRITE_PAUSE
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        /* Give ourselves a stack. */
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        set     0x2000, %g5
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        add     %g6, %g5, %g6           ! end of stack
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        sub     %g6, REGWIN_SZ, %sp
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        mov     0, %fp
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        /* Turn on traps (PSR_ET). */
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        rd      %psr, %g1
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        wr      %g1, PSR_ET, %psr       ! traps on
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        WRITE_PAUSE
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        /* Init our caches, etc. */
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        set     C_LABEL(poke_srmmu), %g5
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        ld      [%g5], %g5
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        call    %g5
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         nop
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        /* Start this processor. */
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        call    C_LABEL(smp_callin)
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         nop
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        call    C_LABEL(cpu_idle)
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         mov    0, %o0
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        call    C_LABEL(cpu_panic)
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         nop

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