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[/] [or1k/] [trunk/] [uclinux/] [uClinux-2.0.x/] [drivers/] [char/] [68302serial.h] - Blame information for rev 1765

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Line No. Rev Author Line
1 199 simons
/* 68302serial.h: Definitions for the mc68302 serial driver.
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 *
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 * Based on:
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 *
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 * drivers/char/68328serial.h
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 *
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 */
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#ifndef _MC68302_SERIAL_H
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#define _MC68302_SERIAL_H
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#include <linux/config.h>
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struct serial_struct {
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        int     type;
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        int     line;
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        int     port;
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        int     irq;
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        int     flags;
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        int     xmit_fifo_size;
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        int     custom_divisor;
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        int     baud_base;
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        unsigned short  close_delay;
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        char    reserved_char[2];
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        int     hub6;  /* FIXME: We don't have AT&T Hub6 boards! */
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        unsigned short  closing_wait; /* time to wait before closing */
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        unsigned short  closing_wait2; /* no longer used... */
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        int     reserved[4];
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};
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/*
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 * For the close wait times, 0 means wait forever for serial port to
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 * flush its output.  65535 means don't wait at all.
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 */
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#define S_CLOSING_WAIT_INF      0
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#define S_CLOSING_WAIT_NONE     65535
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/*
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 * Definitions for S_struct (and serial_struct) flags field
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 */
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#define S_HUP_NOTIFY 0x0001 /* Notify getty on hangups and closes 
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                                   on the callout port */
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#define S_FOURPORT  0x0002      /* Set OU1, OUT2 per AST Fourport settings */
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#define S_SAK   0x0004  /* Secure Attention Key (Orange book) */
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#define S_SPLIT_TERMIOS 0x0008 /* Separate termios for dialin/callout */
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#define S_SPD_MASK      0x0030
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#define S_SPD_HI        0x0010  /* Use 56000 instead of 38400 bps */
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#define S_SPD_VHI       0x0020  /* Use 115200 instead of 38400 bps */
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#define S_SPD_CUST      0x0030  /* Use user-specified divisor */
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#define S_SKIP_TEST     0x0040 /* Skip UART test during autoconfiguration */
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#define S_AUTO_IRQ  0x0080 /* Do automatic IRQ during autoconfiguration */
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#define S_SESSION_LOCKOUT 0x0100 /* Lock out cua opens based on session */
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#define S_PGRP_LOCKOUT    0x0200 /* Lock out cua opens based on pgrp */
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#define S_CALLOUT_NOHUP   0x0400 /* Don't do hangups for cua device */
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#define S_FLAGS 0x0FFF  /* Possible legal S flags */
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#define S_USR_MASK 0x0430       /* Legal flags that non-privileged
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                                 * users can set or reset */
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/* Internal flags used only by kernel/chr_drv/serial.c */
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#define S_INITIALIZED   0x80000000 /* Serial port was initialized */
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#define S_CALLOUT_ACTIVE        0x40000000 /* Call out device is active */
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#define S_NORMAL_ACTIVE 0x20000000 /* Normal device is active */
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#define S_BOOT_AUTOCONF 0x10000000 /* Autoconfigure port on bootup */
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#define S_CLOSING               0x08000000 /* Serial port is closing */
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#define S_CTS_FLOW              0x04000000 /* Do CTS flow control */
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#define S_CHECK_CD              0x02000000 /* i.e., CLOCAL */
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/* Software state per channel */
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#ifdef __KERNEL__
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/*
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 * This is our internal structure for each serial port's state.
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 *
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 * Many fields are paralleled by the structure used by the serial_struct
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 * structure.
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 *
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 * For definitions of the flags field, see tty.h
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 */
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struct m68k_serial {
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        char soft_carrier;  /* Use soft carrier on this channel */
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        char break_abort;   /* Is serial console in, so process brk/abrt */
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#if 0
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        char cons_keyb;     /* Channel runs the keyboard */
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        char cons_mouse;    /* Channel runs the mouse */
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        char kgdb_channel;  /* Kgdb is running on this channel */
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#endif
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        char is_cons;       /* Is this our console. */
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        /* We need to know the current clock divisor
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         * to read the bps rate the chip has currently
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         * loaded.
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         */
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        unsigned char clk_divisor;  /* May be 1, 16, 32, or 64 */
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        int baud;
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        int                     magic;
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        int                     baud_base;
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        int                     port;
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        int                     irq;
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        int                     flags;          /* defined in tty.h */
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        int                     type;           /* UART type */
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        struct tty_struct       *tty;
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        int                     read_status_mask;
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        int                     ignore_status_mask;
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        int                     timeout;
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        int                     xmit_fifo_size;
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        int                     custom_divisor;
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        int                     x_char; /* xon/xoff character */
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        int                     close_delay;
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        unsigned short          closing_wait;
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        unsigned short          closing_wait2;
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        unsigned long           event;
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        unsigned long           last_active;
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        int                     line;
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        int                     count;      /* # of fd on device */
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        int                     blocked_open; /* # of blocked opens */
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        long                    session; /* Session of opening process */
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        long                    pgrp; /* pgrp of opening process */
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        unsigned char           *xmit_buf;
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        int                     xmit_head;
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        int                     xmit_tail;
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        int                     xmit_cnt;
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        struct tq_struct        tqueue;
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        struct tq_struct        tqueue_hangup;
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        struct termios          normal_termios;
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        struct termios          callout_termios;
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        struct wait_queue       *open_wait;
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        struct wait_queue       *close_wait;
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};
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#define SERIAL_MAGIC 0x5301
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/*
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 * The size of the serial xmit buffer is 1 page, or 4096 bytes
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 */
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#define SERIAL_XMIT_SIZE 4096
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/*
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 * Events are used to schedule things to happen at timer-interrupt
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 * time, instead of at rs interrupt time.
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 */
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#define RS_EVENT_WRITE_WAKEUP   0
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#endif /* __KERNEL__ */
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#define BASE 0xF00000
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//#define BASE 0xFFF000
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#define VSP(X) (*(volatile unsigned short *)(X))
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#define VCP(X) (*(volatile unsigned char *)(X))
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#define VLP(X) (*(volatile unsigned long *)(X))
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#define GIMR    VSP(BASE+0x812) /* Global Interrupt Mode Reg's Memory Address */
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#define IMR             VSP(BASE+0x816) /* Interrupt Mask Reg'S Memory Address */
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#define ISR             VSP(BASE+0x818)
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#define IxR_SCC1        0x2000
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#define IxR_SCC2        0x400
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#define IxR_SCC3        0x100
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#define SCCBASE BASE+0x880
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#define SCCOFFSET 0x10
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#define BDBASE BASE+0x400
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#define BDOFFSET 0x100
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/* SCC registers */
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// Common SCC
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#define SIMODE    VSP(BASE+0x8B4)
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#define SIMASK    VSP(BASE+0x8B2)
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#define SPMODE    VSP(BASE+0x8B0)
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#define SCR               VSP(BASE+0x860)
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#define SMC2Rx    VSP(BASE+0x66A)
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#define SMC1Rx    VSP(BASE+0x666)
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#define SMC2Tx    VSP(BASE+0x66C)
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#define BDSIZE      4                                           // Each BD has 4 ushorts
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        /* CR - command register */
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#define CR_RST                                                          0x80
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#define CR_GCI                                                          0x40
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#define CR_OP_STOP_TX                                           0x00
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#define CR_OP_REST_TX                                           0x10
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#define CR_OP_HUNT_MODE                                         0x20
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#define CR_OP_RST_BCS                                           0x30
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#define CR_SCC1                                                         0x00
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#define CR_SCC2                                                         0x02
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#define CR_SCC3                                                         0x04
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#define CR_FLG                                                          0x01
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/* SCM - SCC Mode Register common bits */
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#define SCCM_ENT        4
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#define SCCM_ENR        8
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/* SCM - SCC Mode Register UART bits */
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#define SCM_CL          0x100
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#define SCM_SL          0x40
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#define SCM_PEN         0x1000
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#define SCM_ODD         0
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#define SCM_EVEN        0x8000
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/* SCCE - SCC Event Register  */
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#define SCCE_CTS        0x80
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#define SCCE_CD         0x40
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#define SCCE_IDLE       0x20
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#define SCCE_BRK        0x10
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#define SCCE_CCR        0x8
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#define SCCE_BSY        0x4
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#define SCCE_TX         0x2
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#define SCCE_RX         0x1
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/* BD RX control bits */
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#define RX_BD_OV        0x2
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#define RX_BD_PR        0x8
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#define RX_BD_FR        0x10
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#define RX_BD_BR        0x20
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/*  SCC 0,1,2 */
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#define SCON(X)         VSP(SCCBASE+SCCOFFSET*(X)+2)  
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#define SCM(X)          VSP(SCCBASE+SCCOFFSET*(X)+4)
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#define SCCE(X)         VCP(SCCBASE+SCCOFFSET*(X)+8)
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#define SCCM(X)         VCP(SCCBASE+SCCOFFSET*(X)+0xA)
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#define SCC_TXBD_1W(X,Y)        VSP(BDBASE+BDOFFSET*(X)+BDSIZE*(Y)+0x40)  
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#define SCC_TXBD_2W(X,Y)        VSP(BDBASE+BDOFFSET*(X)+BDSIZE*(Y)+0x42)
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#define SCC_TXBD_1L(X,Y)        VLP(BDBASE+BDOFFSET*(X)+BDSIZE*(Y)+0x44)
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#define SCC_RXBD_1W(X,Y)        VSP(BDBASE+BDOFFSET*(X)+BDSIZE*(Y)+0x00) 
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#define SCC_RXBD_2W(X,Y)        VSP(BDBASE+BDOFFSET*(X)+BDSIZE*(Y)+0x02)
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#define SCC_RXBD_1L(X,Y)        VLP(BDBASE+BDOFFSET*(X)+BDSIZE*(Y)+0x04)
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#define SCC_MAX_IDL(X)          VSP(BDBASE+BDOFFSET*(X)+0x9C)
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#define SCC_BRKCR(X)            VSP(BDBASE+BDOFFSET*(X)+0xA0)
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#define SCC_PAREC(X)            VSP(BDBASE+BDOFFSET*(X)+0xA2)
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#define SCC_FRMEC(X)            VSP(BDBASE+BDOFFSET*(X)+0xA4)
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#define SCC_NOSEC(X)            VSP(BDBASE+BDOFFSET*(X)+0xA6)
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#define SCC_BRKEC(X)            VSP(BDBASE+BDOFFSET*(X)+0xA8) 
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#define SCC_MRBLR(X)            VSP(BDBASE+BDOFFSET*(X)+0x82)
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#define SCC_RFCR(X)                     VSP(BDBASE+BDOFFSET*(X)+0x80)
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#define SCC_CARACT(X)           VSP(BDBASE+BDOFFSET*(X)+0xB0)
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#define SCC_UADDR1(X)           VSP(BDBASE+BDOFFSET*(X)+0xAA)
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#define SCC_UADDR2(X)           VSP(BDBASE+BDOFFSET*(X)+0xAC)
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#define MAX_BUFFER_SIZE         0xFFFF
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// port A 
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#define PACNT    VSP(BASE+0x81E)
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#define PADDR    VSP(BASE+0x820)
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#define PADAT    VSP(BASE+0x822)
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/* port B */
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#define PBCNT           VSP(BASE+0x824)
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#define PBDDR           VSP(BASE+0x826) 
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#define PBDAT           VSP(BASE+0x828)
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#endif /* !(_MC68302_SERIAL_H) */

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