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199 |
simons |
/* $Id: hfc_2bds0.c,v 1.1.1.1 2001-09-10 07:44:18 simons Exp $
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*
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* specific routines for CCD's HFC 2BDS0
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*
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* Author Karsten Keil (keil@temic-ech.spacenet.de)
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*
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*
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* $Log: not supported by cvs2svn $
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* Revision 1.1.1.1 2001/07/02 17:58:32 simons
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* Initial revision
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*
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* Revision 1.1.2.9 1998/11/03 00:06:24 keil
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* certification related changes
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* fixed logging for smaller stack use
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*
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* Revision 1.1.2.8 1998/09/30 22:23:55 keil
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* Fix missing line in setstack*
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*
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* Revision 1.1.2.7 1998/09/27 13:06:01 keil
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* Apply most changes from 2.1.X (HiSax 3.1)
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*
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* Revision 1.1.2.6 1998/06/27 22:54:07 keil
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* make 16.3c working with 3.0
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*
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* Revision 1.1.2.5 1998/05/27 18:05:23 keil
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* HiSax 3.0
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*
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* Revision 1.1.2.4 1998/04/08 21:54:35 keil
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* Fix "ll_trans ..." message
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*
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* Revision 1.1.2.3 1998/04/04 21:59:20 keil
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* Fixed B-channel access
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*
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* Revision 1.1.2.2 1998/01/27 22:40:35 keil
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* fixed IRQ latency, B-channel selection and more
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*
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* Revision 1.1.2.1 1998/01/11 22:54:00 keil
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* Teles 16.3c (HFC 2BDS0) first version
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*
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*
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*/
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#define __NO_VERSION__
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#include "hisax.h"
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#include "hfc_2bds0.h"
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#include "isdnl1.h"
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#include <linux/interrupt.h>
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/*
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#define KDEBUG_DEF
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#include "kdebug.h"
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*/
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#define byteout(addr,val) outb(val,addr)
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#define bytein(addr) inb(addr)
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static void
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dummyf(struct IsdnCardState *cs, u_char * data, int size)
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{
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printk(KERN_WARNING "HiSax: hfcd dummy fifo called\n");
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}
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static inline u_char
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ReadReg(struct IsdnCardState *cs, int data, u_char reg)
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| 63 |
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{
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| 64 |
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register u_char ret;
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| 65 |
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| 66 |
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if (data) {
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if (cs->hw.hfcD.cip != reg) {
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cs->hw.hfcD.cip = reg;
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byteout(cs->hw.hfcD.addr | 1, reg);
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}
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ret = bytein(cs->hw.hfcD.addr);
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#if HFC_REG_DEBUG
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if (cs->debug & L1_DEB_HSCX_FIFO && (data != 2))
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debugl1(cs, "t3c RD %02x %02x", reg, ret);
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#endif
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} else
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ret = bytein(cs->hw.hfcD.addr | 1);
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return (ret);
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}
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static inline void
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WriteReg(struct IsdnCardState *cs, int data, u_char reg, u_char value)
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| 83 |
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{
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| 84 |
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if (cs->hw.hfcD.cip != reg) {
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cs->hw.hfcD.cip = reg;
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byteout(cs->hw.hfcD.addr | 1, reg);
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| 87 |
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}
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| 88 |
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if (data)
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| 89 |
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byteout(cs->hw.hfcD.addr, value);
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| 90 |
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#if HFC_REG_DEBUG
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| 91 |
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if (cs->debug & L1_DEB_HSCX_FIFO && (data != HFCD_DATA_NODEB))
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debugl1(cs, "t3c W%c %02x %02x", data ? 'D' : 'C', reg, value);
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| 93 |
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#endif
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| 94 |
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}
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| 96 |
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/* Interface functions */
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| 98 |
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static u_char
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| 99 |
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readreghfcd(struct IsdnCardState *cs, u_char offset)
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| 100 |
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{
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| 101 |
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return(ReadReg(cs, HFCD_DATA, offset));
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| 102 |
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}
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| 103 |
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| 104 |
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static void
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| 105 |
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writereghfcd(struct IsdnCardState *cs, u_char offset, u_char value)
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| 106 |
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{
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| 107 |
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WriteReg(cs, HFCD_DATA, offset, value);
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| 108 |
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}
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| 109 |
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| 110 |
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void
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| 111 |
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set_cs_func(struct IsdnCardState *cs)
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{
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| 113 |
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cs->readisac = &readreghfcd;
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cs->writeisac = &writereghfcd;
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| 115 |
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cs->readisacfifo = &dummyf;
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cs->writeisacfifo = &dummyf;
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cs->BC_Read_Reg = &ReadReg;
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cs->BC_Write_Reg = &WriteReg;
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}
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static inline int
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WaitForBusy(struct IsdnCardState *cs)
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{
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| 124 |
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int to = 130;
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| 125 |
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| 126 |
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while (!(ReadReg(cs, HFCD_DATA, HFCD_STAT) & HFCD_BUSY) && to) {
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udelay(1);
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| 128 |
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to--;
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| 129 |
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}
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| 130 |
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if (!to)
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printk(KERN_WARNING "HiSax: WaitForBusy timeout\n");
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return (to);
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| 133 |
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}
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| 134 |
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| 135 |
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static inline int
|
| 136 |
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WaitNoBusy(struct IsdnCardState *cs)
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| 137 |
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{
|
| 138 |
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long flags;
|
| 139 |
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int to = 130;
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| 140 |
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| 141 |
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while ((ReadReg(cs, HFCD_STATUS, HFCD_STATUS) & HFCD_BUSY) && to) {
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| 142 |
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save_flags(flags);
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| 143 |
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sti();
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| 144 |
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udelay(1);
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| 145 |
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to--;
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| 146 |
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restore_flags(flags);
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| 147 |
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}
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| 148 |
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if (!to)
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| 149 |
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printk(KERN_WARNING "HiSax: WaitNoBusy timeout\n");
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| 150 |
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return (to);
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| 151 |
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}
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| 152 |
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| 153 |
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static int
|
| 154 |
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SelFiFo(struct IsdnCardState *cs, u_char FiFo)
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| 155 |
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{
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| 156 |
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u_char cip;
|
| 157 |
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long flags;
|
| 158 |
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| 159 |
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| 160 |
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if (cs->hw.hfcD.fifo == FiFo)
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| 161 |
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return(1);
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| 162 |
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save_flags(flags);
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| 163 |
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cli();
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| 164 |
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switch(FiFo) {
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| 165 |
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case 0: cip = HFCB_FIFO | HFCB_Z1 | HFCB_SEND | HFCB_B1;
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| 166 |
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break;
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| 167 |
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case 1: cip = HFCB_FIFO | HFCB_Z1 | HFCB_REC | HFCB_B1;
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| 168 |
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break;
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| 169 |
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case 2: cip = HFCB_FIFO | HFCB_Z1 | HFCB_SEND | HFCB_B2;
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| 170 |
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break;
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| 171 |
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case 3: cip = HFCB_FIFO | HFCB_Z1 | HFCB_REC | HFCB_B2;
|
| 172 |
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break;
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| 173 |
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case 4: cip = HFCD_FIFO | HFCD_Z1 | HFCD_SEND;
|
| 174 |
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break;
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| 175 |
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case 5: cip = HFCD_FIFO | HFCD_Z1 | HFCD_REC;
|
| 176 |
|
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break;
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| 177 |
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default:
|
| 178 |
|
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restore_flags(flags);
|
| 179 |
|
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debugl1(cs, "SelFiFo Error");
|
| 180 |
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return(0);
|
| 181 |
|
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}
|
| 182 |
|
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cs->hw.hfcD.fifo = FiFo;
|
| 183 |
|
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WaitNoBusy(cs);
|
| 184 |
|
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cs->BC_Write_Reg(cs, HFCD_DATA, cip, 0);
|
| 185 |
|
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sti();
|
| 186 |
|
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WaitForBusy(cs);
|
| 187 |
|
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restore_flags(flags);
|
| 188 |
|
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return(2);
|
| 189 |
|
|
}
|
| 190 |
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static int
|
| 191 |
|
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GetFreeFifoBytes_B(struct BCState *bcs)
|
| 192 |
|
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{
|
| 193 |
|
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int s;
|
| 194 |
|
|
|
| 195 |
|
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if (bcs->hw.hfc.f1 == bcs->hw.hfc.f2)
|
| 196 |
|
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return (bcs->cs->hw.hfcD.bfifosize);
|
| 197 |
|
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s = bcs->hw.hfc.send[bcs->hw.hfc.f1] - bcs->hw.hfc.send[bcs->hw.hfc.f2];
|
| 198 |
|
|
if (s <= 0)
|
| 199 |
|
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s += bcs->cs->hw.hfcD.bfifosize;
|
| 200 |
|
|
s = bcs->cs->hw.hfcD.bfifosize - s;
|
| 201 |
|
|
return (s);
|
| 202 |
|
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}
|
| 203 |
|
|
|
| 204 |
|
|
static int
|
| 205 |
|
|
GetFreeFifoBytes_D(struct IsdnCardState *cs)
|
| 206 |
|
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{
|
| 207 |
|
|
int s;
|
| 208 |
|
|
|
| 209 |
|
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if (cs->hw.hfcD.f1 == cs->hw.hfcD.f2)
|
| 210 |
|
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return (cs->hw.hfcD.dfifosize);
|
| 211 |
|
|
s = cs->hw.hfcD.send[cs->hw.hfcD.f1] - cs->hw.hfcD.send[cs->hw.hfcD.f2];
|
| 212 |
|
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if (s <= 0)
|
| 213 |
|
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s += cs->hw.hfcD.dfifosize;
|
| 214 |
|
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s = cs->hw.hfcD.dfifosize - s;
|
| 215 |
|
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return (s);
|
| 216 |
|
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}
|
| 217 |
|
|
|
| 218 |
|
|
static int
|
| 219 |
|
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ReadZReg(struct IsdnCardState *cs, u_char reg)
|
| 220 |
|
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{
|
| 221 |
|
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int val;
|
| 222 |
|
|
|
| 223 |
|
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WaitNoBusy(cs);
|
| 224 |
|
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val = 256 * ReadReg(cs, HFCD_DATA, reg | HFCB_Z_HIGH);
|
| 225 |
|
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WaitNoBusy(cs);
|
| 226 |
|
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val += ReadReg(cs, HFCD_DATA, reg | HFCB_Z_LOW);
|
| 227 |
|
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return (val);
|
| 228 |
|
|
}
|
| 229 |
|
|
|
| 230 |
|
|
static void
|
| 231 |
|
|
hfc_sched_event(struct BCState *bcs, int event)
|
| 232 |
|
|
{
|
| 233 |
|
|
bcs->event |= 1 << event;
|
| 234 |
|
|
queue_task(&bcs->tqueue, &tq_immediate);
|
| 235 |
|
|
mark_bh(IMMEDIATE_BH);
|
| 236 |
|
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}
|
| 237 |
|
|
|
| 238 |
|
|
static struct sk_buff
|
| 239 |
|
|
*hfc_empty_fifo(struct BCState *bcs, int count)
|
| 240 |
|
|
{
|
| 241 |
|
|
u_char *ptr;
|
| 242 |
|
|
struct sk_buff *skb;
|
| 243 |
|
|
struct IsdnCardState *cs = bcs->cs;
|
| 244 |
|
|
int idx;
|
| 245 |
|
|
int chksum;
|
| 246 |
|
|
long flags;
|
| 247 |
|
|
u_char stat, cip;
|
| 248 |
|
|
|
| 249 |
|
|
if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
|
| 250 |
|
|
debugl1(cs, "hfc_empty_fifo");
|
| 251 |
|
|
idx = 0;
|
| 252 |
|
|
save_flags(flags);
|
| 253 |
|
|
if (count > HSCX_BUFMAX + 3) {
|
| 254 |
|
|
if (cs->debug & L1_DEB_WARN)
|
| 255 |
|
|
debugl1(cs, "hfc_empty_fifo: incoming packet too large");
|
| 256 |
|
|
cip = HFCB_FIFO | HFCB_FIFO_OUT | HFCB_REC | HFCB_CHANNEL(bcs->channel);
|
| 257 |
|
|
while (idx++ < count) {
|
| 258 |
|
|
cli();
|
| 259 |
|
|
WaitNoBusy(cs);
|
| 260 |
|
|
ReadReg(cs, HFCD_DATA_NODEB, cip);
|
| 261 |
|
|
sti();
|
| 262 |
|
|
}
|
| 263 |
|
|
skb = NULL;
|
| 264 |
|
|
} else if (count < 4) {
|
| 265 |
|
|
if (cs->debug & L1_DEB_WARN)
|
| 266 |
|
|
debugl1(cs, "hfc_empty_fifo: incoming packet too small");
|
| 267 |
|
|
cip = HFCB_FIFO | HFCB_FIFO_OUT | HFCB_REC | HFCB_CHANNEL(bcs->channel);
|
| 268 |
|
|
cli();
|
| 269 |
|
|
while ((idx++ < count) && WaitNoBusy(cs))
|
| 270 |
|
|
ReadReg(cs, HFCD_DATA_NODEB, cip);
|
| 271 |
|
|
skb = NULL;
|
| 272 |
|
|
} else if (!(skb = dev_alloc_skb(count - 3)))
|
| 273 |
|
|
printk(KERN_WARNING "HFC: receive out of memory\n");
|
| 274 |
|
|
else {
|
| 275 |
|
|
SET_SKB_FREE(skb);
|
| 276 |
|
|
ptr = skb_put(skb, count - 3);
|
| 277 |
|
|
idx = 0;
|
| 278 |
|
|
cip = HFCB_FIFO | HFCB_FIFO_OUT | HFCB_REC | HFCB_CHANNEL(bcs->channel);
|
| 279 |
|
|
cli();
|
| 280 |
|
|
while (idx < (count - 3)) {
|
| 281 |
|
|
cli();
|
| 282 |
|
|
if (!WaitNoBusy(cs))
|
| 283 |
|
|
break;
|
| 284 |
|
|
*ptr = ReadReg(cs, HFCD_DATA_NODEB, cip);
|
| 285 |
|
|
sti();
|
| 286 |
|
|
ptr++;
|
| 287 |
|
|
idx++;
|
| 288 |
|
|
}
|
| 289 |
|
|
if (idx != count - 3) {
|
| 290 |
|
|
sti();
|
| 291 |
|
|
debugl1(cs, "RFIFO BUSY error");
|
| 292 |
|
|
printk(KERN_WARNING "HFC FIFO channel %d BUSY Error\n", bcs->channel);
|
| 293 |
|
|
dev_kfree_skb(skb, FREE_READ);
|
| 294 |
|
|
skb = NULL;
|
| 295 |
|
|
} else {
|
| 296 |
|
|
cli();
|
| 297 |
|
|
WaitNoBusy(cs);
|
| 298 |
|
|
chksum = (ReadReg(cs, HFCD_DATA, cip) << 8);
|
| 299 |
|
|
WaitNoBusy(cs);
|
| 300 |
|
|
chksum += ReadReg(cs, HFCD_DATA, cip);
|
| 301 |
|
|
WaitNoBusy(cs);
|
| 302 |
|
|
stat = ReadReg(cs, HFCD_DATA, cip);
|
| 303 |
|
|
sti();
|
| 304 |
|
|
if (cs->debug & L1_DEB_HSCX)
|
| 305 |
|
|
debugl1(cs, "hfc_empty_fifo %d chksum %x stat %x",
|
| 306 |
|
|
bcs->channel, chksum, stat);
|
| 307 |
|
|
if (stat) {
|
| 308 |
|
|
debugl1(cs, "FIFO CRC error");
|
| 309 |
|
|
dev_kfree_skb(skb, FREE_READ);
|
| 310 |
|
|
skb = NULL;
|
| 311 |
|
|
}
|
| 312 |
|
|
}
|
| 313 |
|
|
}
|
| 314 |
|
|
sti();
|
| 315 |
|
|
WaitForBusy(cs);
|
| 316 |
|
|
cli();
|
| 317 |
|
|
WaitNoBusy(cs);
|
| 318 |
|
|
stat = ReadReg(cs, HFCD_DATA, HFCB_FIFO | HFCB_F2_INC |
|
| 319 |
|
|
HFCB_REC | HFCB_CHANNEL(bcs->channel));
|
| 320 |
|
|
sti();
|
| 321 |
|
|
WaitForBusy(cs);
|
| 322 |
|
|
restore_flags(flags);
|
| 323 |
|
|
return (skb);
|
| 324 |
|
|
}
|
| 325 |
|
|
|
| 326 |
|
|
static void
|
| 327 |
|
|
hfc_fill_fifo(struct BCState *bcs)
|
| 328 |
|
|
{
|
| 329 |
|
|
struct IsdnCardState *cs = bcs->cs;
|
| 330 |
|
|
long flags;
|
| 331 |
|
|
int idx, fcnt;
|
| 332 |
|
|
int count;
|
| 333 |
|
|
u_char cip;
|
| 334 |
|
|
|
| 335 |
|
|
if (!bcs->tx_skb)
|
| 336 |
|
|
return;
|
| 337 |
|
|
if (bcs->tx_skb->len <= 0)
|
| 338 |
|
|
return;
|
| 339 |
|
|
save_flags(flags);
|
| 340 |
|
|
cli();
|
| 341 |
|
|
SelFiFo(cs, HFCB_SEND | HFCB_CHANNEL(bcs->channel));
|
| 342 |
|
|
cip = HFCB_FIFO | HFCB_F1 | HFCB_SEND | HFCB_CHANNEL(bcs->channel);
|
| 343 |
|
|
WaitNoBusy(cs);
|
| 344 |
|
|
bcs->hw.hfc.f1 = ReadReg(cs, HFCD_DATA, cip);
|
| 345 |
|
|
WaitNoBusy(cs);
|
| 346 |
|
|
cip = HFCB_FIFO | HFCB_F2 | HFCB_SEND | HFCB_CHANNEL(bcs->channel);
|
| 347 |
|
|
WaitNoBusy(cs);
|
| 348 |
|
|
bcs->hw.hfc.f2 = ReadReg(cs, HFCD_DATA, cip);
|
| 349 |
|
|
bcs->hw.hfc.send[bcs->hw.hfc.f1] = ReadZReg(cs, HFCB_FIFO | HFCB_Z1 | HFCB_SEND | HFCB_CHANNEL(bcs->channel));
|
| 350 |
|
|
sti();
|
| 351 |
|
|
if (cs->debug & L1_DEB_HSCX)
|
| 352 |
|
|
debugl1(cs, "hfc_fill_fifo %d f1(%d) f2(%d) z1(%x)",
|
| 353 |
|
|
bcs->channel, bcs->hw.hfc.f1, bcs->hw.hfc.f2,
|
| 354 |
|
|
bcs->hw.hfc.send[bcs->hw.hfc.f1]);
|
| 355 |
|
|
fcnt = bcs->hw.hfc.f1 - bcs->hw.hfc.f2;
|
| 356 |
|
|
if (fcnt < 0)
|
| 357 |
|
|
fcnt += 32;
|
| 358 |
|
|
if (fcnt > 30) {
|
| 359 |
|
|
if (cs->debug & L1_DEB_HSCX)
|
| 360 |
|
|
debugl1(cs, "hfc_fill_fifo more as 30 frames");
|
| 361 |
|
|
restore_flags(flags);
|
| 362 |
|
|
return;
|
| 363 |
|
|
}
|
| 364 |
|
|
count = GetFreeFifoBytes_B(bcs);
|
| 365 |
|
|
if (cs->debug & L1_DEB_HSCX)
|
| 366 |
|
|
debugl1(cs, "hfc_fill_fifo %d count(%ld/%d),%lx",
|
| 367 |
|
|
bcs->channel, bcs->tx_skb->len,
|
| 368 |
|
|
count, current->state);
|
| 369 |
|
|
if (count < bcs->tx_skb->len) {
|
| 370 |
|
|
if (cs->debug & L1_DEB_HSCX)
|
| 371 |
|
|
debugl1(cs, "hfc_fill_fifo no fifo mem");
|
| 372 |
|
|
restore_flags(flags);
|
| 373 |
|
|
return;
|
| 374 |
|
|
}
|
| 375 |
|
|
cip = HFCB_FIFO | HFCB_FIFO_IN | HFCB_SEND | HFCB_CHANNEL(bcs->channel);
|
| 376 |
|
|
idx = 0;
|
| 377 |
|
|
cli();
|
| 378 |
|
|
WaitForBusy(cs);
|
| 379 |
|
|
WaitNoBusy(cs);
|
| 380 |
|
|
WriteReg(cs, HFCD_DATA_NODEB, cip, bcs->tx_skb->data[idx++]);
|
| 381 |
|
|
while (idx < bcs->tx_skb->len) {
|
| 382 |
|
|
cli();
|
| 383 |
|
|
if (!WaitNoBusy(cs))
|
| 384 |
|
|
break;
|
| 385 |
|
|
WriteReg(cs, HFCD_DATA_NODEB, cip, bcs->tx_skb->data[idx]);
|
| 386 |
|
|
sti();
|
| 387 |
|
|
idx++;
|
| 388 |
|
|
}
|
| 389 |
|
|
if (idx != bcs->tx_skb->len) {
|
| 390 |
|
|
sti();
|
| 391 |
|
|
debugl1(cs, "FIFO Send BUSY error");
|
| 392 |
|
|
printk(KERN_WARNING "HFC S FIFO channel %d BUSY Error\n", bcs->channel);
|
| 393 |
|
|
} else {
|
| 394 |
|
|
bcs->tx_cnt -= bcs->tx_skb->len;
|
| 395 |
|
|
if (bcs->st->lli.l1writewakeup &&
|
| 396 |
|
|
(PACKET_NOACK != bcs->tx_skb->pkt_type))
|
| 397 |
|
|
bcs->st->lli.l1writewakeup(bcs->st, bcs->tx_skb->len);
|
| 398 |
|
|
dev_kfree_skb(bcs->tx_skb, FREE_WRITE);
|
| 399 |
|
|
bcs->tx_skb = NULL;
|
| 400 |
|
|
}
|
| 401 |
|
|
WaitForBusy(cs);
|
| 402 |
|
|
cli();
|
| 403 |
|
|
WaitNoBusy(cs);
|
| 404 |
|
|
ReadReg(cs, HFCD_DATA, HFCB_FIFO | HFCB_F1_INC | HFCB_SEND | HFCB_CHANNEL(bcs->channel));
|
| 405 |
|
|
sti();
|
| 406 |
|
|
WaitForBusy(cs);
|
| 407 |
|
|
test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
|
| 408 |
|
|
restore_flags(flags);
|
| 409 |
|
|
return;
|
| 410 |
|
|
}
|
| 411 |
|
|
|
| 412 |
|
|
static void
|
| 413 |
|
|
hfc_send_data(struct BCState *bcs)
|
| 414 |
|
|
{
|
| 415 |
|
|
struct IsdnCardState *cs = bcs->cs;
|
| 416 |
|
|
|
| 417 |
|
|
if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
|
| 418 |
|
|
hfc_fill_fifo(bcs);
|
| 419 |
|
|
test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
|
| 420 |
|
|
} else
|
| 421 |
|
|
debugl1(cs,"send_data %d blocked", bcs->channel);
|
| 422 |
|
|
}
|
| 423 |
|
|
|
| 424 |
|
|
void
|
| 425 |
|
|
main_rec_2bds0(struct BCState *bcs)
|
| 426 |
|
|
{
|
| 427 |
|
|
long flags;
|
| 428 |
|
|
struct IsdnCardState *cs = bcs->cs;
|
| 429 |
|
|
int z1, z2, rcnt;
|
| 430 |
|
|
u_char f1, f2, cip;
|
| 431 |
|
|
int receive, count = 5;
|
| 432 |
|
|
struct sk_buff *skb;
|
| 433 |
|
|
|
| 434 |
|
|
save_flags(flags);
|
| 435 |
|
|
Begin:
|
| 436 |
|
|
count--;
|
| 437 |
|
|
cli();
|
| 438 |
|
|
if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
|
| 439 |
|
|
debugl1(cs,"rec_data %d blocked", bcs->channel);
|
| 440 |
|
|
restore_flags(flags);
|
| 441 |
|
|
return;
|
| 442 |
|
|
}
|
| 443 |
|
|
SelFiFo(cs, HFCB_REC | HFCB_CHANNEL(bcs->channel));
|
| 444 |
|
|
cip = HFCB_FIFO | HFCB_F1 | HFCB_REC | HFCB_CHANNEL(bcs->channel);
|
| 445 |
|
|
WaitNoBusy(cs);
|
| 446 |
|
|
f1 = ReadReg(cs, HFCD_DATA, cip);
|
| 447 |
|
|
cip = HFCB_FIFO | HFCB_F2 | HFCB_REC | HFCB_CHANNEL(bcs->channel);
|
| 448 |
|
|
WaitNoBusy(cs);
|
| 449 |
|
|
f2 = ReadReg(cs, HFCD_DATA, cip);
|
| 450 |
|
|
sti();
|
| 451 |
|
|
if (f1 != f2) {
|
| 452 |
|
|
if (cs->debug & L1_DEB_HSCX)
|
| 453 |
|
|
debugl1(cs, "hfc rec %d f1(%d) f2(%d)",
|
| 454 |
|
|
bcs->channel, f1, f2);
|
| 455 |
|
|
cli();
|
| 456 |
|
|
z1 = ReadZReg(cs, HFCB_FIFO | HFCB_Z1 | HFCB_REC | HFCB_CHANNEL(bcs->channel));
|
| 457 |
|
|
z2 = ReadZReg(cs, HFCB_FIFO | HFCB_Z2 | HFCB_REC | HFCB_CHANNEL(bcs->channel));
|
| 458 |
|
|
sti();
|
| 459 |
|
|
rcnt = z1 - z2;
|
| 460 |
|
|
if (rcnt < 0)
|
| 461 |
|
|
rcnt += cs->hw.hfcD.bfifosize;
|
| 462 |
|
|
rcnt++;
|
| 463 |
|
|
if (cs->debug & L1_DEB_HSCX)
|
| 464 |
|
|
debugl1(cs, "hfc rec %d z1(%x) z2(%x) cnt(%d)",
|
| 465 |
|
|
bcs->channel, z1, z2, rcnt);
|
| 466 |
|
|
if ((skb = hfc_empty_fifo(bcs, rcnt))) {
|
| 467 |
|
|
cli();
|
| 468 |
|
|
skb_queue_tail(&bcs->rqueue, skb);
|
| 469 |
|
|
sti();
|
| 470 |
|
|
hfc_sched_event(bcs, B_RCVBUFREADY);
|
| 471 |
|
|
}
|
| 472 |
|
|
rcnt = f1 -f2;
|
| 473 |
|
|
if (rcnt<0)
|
| 474 |
|
|
rcnt += 32;
|
| 475 |
|
|
if (rcnt>1)
|
| 476 |
|
|
receive = 1;
|
| 477 |
|
|
else
|
| 478 |
|
|
receive = 0;
|
| 479 |
|
|
} else
|
| 480 |
|
|
receive = 0;
|
| 481 |
|
|
test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
|
| 482 |
|
|
if (count && receive)
|
| 483 |
|
|
goto Begin;
|
| 484 |
|
|
restore_flags(flags);
|
| 485 |
|
|
return;
|
| 486 |
|
|
}
|
| 487 |
|
|
|
| 488 |
|
|
void
|
| 489 |
|
|
mode_2bs0(struct BCState *bcs, int mode, int bc)
|
| 490 |
|
|
{
|
| 491 |
|
|
struct IsdnCardState *cs = bcs->cs;
|
| 492 |
|
|
|
| 493 |
|
|
if (cs->debug & L1_DEB_HSCX)
|
| 494 |
|
|
debugl1(cs, "HFCD bchannel mode %d bchan %d/%d",
|
| 495 |
|
|
mode, bc, bcs->channel);
|
| 496 |
|
|
bcs->mode = mode;
|
| 497 |
|
|
bcs->channel = bc;
|
| 498 |
|
|
switch (mode) {
|
| 499 |
|
|
case (L1_MODE_NULL):
|
| 500 |
|
|
if (bc) {
|
| 501 |
|
|
cs->hw.hfcD.conn |= 0x18;
|
| 502 |
|
|
cs->hw.hfcD.sctrl &= ~SCTRL_B2_ENA;
|
| 503 |
|
|
} else {
|
| 504 |
|
|
cs->hw.hfcD.conn |= 0x3;
|
| 505 |
|
|
cs->hw.hfcD.sctrl &= ~SCTRL_B1_ENA;
|
| 506 |
|
|
}
|
| 507 |
|
|
break;
|
| 508 |
|
|
case (L1_MODE_TRANS):
|
| 509 |
|
|
if (bc) {
|
| 510 |
|
|
cs->hw.hfcD.ctmt |= 2;
|
| 511 |
|
|
cs->hw.hfcD.conn &= ~0x18;
|
| 512 |
|
|
cs->hw.hfcD.sctrl |= SCTRL_B2_ENA;
|
| 513 |
|
|
} else {
|
| 514 |
|
|
cs->hw.hfcD.ctmt |= 1;
|
| 515 |
|
|
cs->hw.hfcD.conn &= ~0x3;
|
| 516 |
|
|
cs->hw.hfcD.sctrl |= SCTRL_B1_ENA;
|
| 517 |
|
|
}
|
| 518 |
|
|
break;
|
| 519 |
|
|
case (L1_MODE_HDLC):
|
| 520 |
|
|
if (bc) {
|
| 521 |
|
|
cs->hw.hfcD.ctmt &= ~2;
|
| 522 |
|
|
cs->hw.hfcD.conn &= ~0x18;
|
| 523 |
|
|
cs->hw.hfcD.sctrl |= SCTRL_B2_ENA;
|
| 524 |
|
|
} else {
|
| 525 |
|
|
cs->hw.hfcD.ctmt &= ~1;
|
| 526 |
|
|
cs->hw.hfcD.conn &= ~0x3;
|
| 527 |
|
|
cs->hw.hfcD.sctrl |= SCTRL_B1_ENA;
|
| 528 |
|
|
}
|
| 529 |
|
|
break;
|
| 530 |
|
|
}
|
| 531 |
|
|
WriteReg(cs, HFCD_DATA, HFCD_SCTRL, cs->hw.hfcD.sctrl);
|
| 532 |
|
|
WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcD.ctmt);
|
| 533 |
|
|
WriteReg(cs, HFCD_DATA, HFCD_CONN, cs->hw.hfcD.conn);
|
| 534 |
|
|
}
|
| 535 |
|
|
|
| 536 |
|
|
static void
|
| 537 |
|
|
hfc_l2l1(struct PStack *st, int pr, void *arg)
|
| 538 |
|
|
{
|
| 539 |
|
|
struct sk_buff *skb = arg;
|
| 540 |
|
|
long flags;
|
| 541 |
|
|
|
| 542 |
|
|
switch (pr) {
|
| 543 |
|
|
case (PH_DATA | REQUEST):
|
| 544 |
|
|
save_flags(flags);
|
| 545 |
|
|
cli();
|
| 546 |
|
|
if (st->l1.bcs->tx_skb) {
|
| 547 |
|
|
skb_queue_tail(&st->l1.bcs->squeue, skb);
|
| 548 |
|
|
restore_flags(flags);
|
| 549 |
|
|
} else {
|
| 550 |
|
|
st->l1.bcs->tx_skb = skb;
|
| 551 |
|
|
/* test_and_set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
|
| 552 |
|
|
*/ st->l1.bcs->cs->BC_Send_Data(st->l1.bcs);
|
| 553 |
|
|
restore_flags(flags);
|
| 554 |
|
|
}
|
| 555 |
|
|
break;
|
| 556 |
|
|
case (PH_PULL | INDICATION):
|
| 557 |
|
|
if (st->l1.bcs->tx_skb) {
|
| 558 |
|
|
printk(KERN_WARNING "hfc_l2l1: this shouldn't happen\n");
|
| 559 |
|
|
break;
|
| 560 |
|
|
}
|
| 561 |
|
|
save_flags(flags);
|
| 562 |
|
|
cli();
|
| 563 |
|
|
/* test_and_set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
|
| 564 |
|
|
*/ st->l1.bcs->tx_skb = skb;
|
| 565 |
|
|
st->l1.bcs->cs->BC_Send_Data(st->l1.bcs);
|
| 566 |
|
|
restore_flags(flags);
|
| 567 |
|
|
break;
|
| 568 |
|
|
case (PH_PULL | REQUEST):
|
| 569 |
|
|
if (!st->l1.bcs->tx_skb) {
|
| 570 |
|
|
test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
|
| 571 |
|
|
st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
|
| 572 |
|
|
} else
|
| 573 |
|
|
test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
|
| 574 |
|
|
break;
|
| 575 |
|
|
case (PH_ACTIVATE | REQUEST):
|
| 576 |
|
|
test_and_set_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
|
| 577 |
|
|
mode_2bs0(st->l1.bcs, st->l1.mode, st->l1.bc);
|
| 578 |
|
|
l1_msg_b(st, pr, arg);
|
| 579 |
|
|
break;
|
| 580 |
|
|
case (PH_DEACTIVATE | REQUEST):
|
| 581 |
|
|
l1_msg_b(st, pr, arg);
|
| 582 |
|
|
break;
|
| 583 |
|
|
case (PH_DEACTIVATE | CONFIRM):
|
| 584 |
|
|
test_and_clear_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
|
| 585 |
|
|
test_and_clear_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
|
| 586 |
|
|
mode_2bs0(st->l1.bcs, 0, st->l1.bc);
|
| 587 |
|
|
st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
|
| 588 |
|
|
break;
|
| 589 |
|
|
}
|
| 590 |
|
|
}
|
| 591 |
|
|
|
| 592 |
|
|
void
|
| 593 |
|
|
close_2bs0(struct BCState *bcs)
|
| 594 |
|
|
{
|
| 595 |
|
|
mode_2bs0(bcs, 0, bcs->channel);
|
| 596 |
|
|
if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
|
| 597 |
|
|
discard_queue(&bcs->rqueue);
|
| 598 |
|
|
discard_queue(&bcs->squeue);
|
| 599 |
|
|
if (bcs->tx_skb) {
|
| 600 |
|
|
dev_kfree_skb(bcs->tx_skb, FREE_WRITE);
|
| 601 |
|
|
bcs->tx_skb = NULL;
|
| 602 |
|
|
test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
|
| 603 |
|
|
}
|
| 604 |
|
|
}
|
| 605 |
|
|
}
|
| 606 |
|
|
|
| 607 |
|
|
static int
|
| 608 |
|
|
open_hfcstate(struct IsdnCardState *cs, struct BCState *bcs)
|
| 609 |
|
|
{
|
| 610 |
|
|
if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
|
| 611 |
|
|
skb_queue_head_init(&bcs->rqueue);
|
| 612 |
|
|
skb_queue_head_init(&bcs->squeue);
|
| 613 |
|
|
}
|
| 614 |
|
|
bcs->tx_skb = NULL;
|
| 615 |
|
|
test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
|
| 616 |
|
|
bcs->event = 0;
|
| 617 |
|
|
bcs->tx_cnt = 0;
|
| 618 |
|
|
return (0);
|
| 619 |
|
|
}
|
| 620 |
|
|
|
| 621 |
|
|
int
|
| 622 |
|
|
setstack_2b(struct PStack *st, struct BCState *bcs)
|
| 623 |
|
|
{
|
| 624 |
|
|
bcs->channel = st->l1.bc;
|
| 625 |
|
|
if (open_hfcstate(st->l1.hardware, bcs))
|
| 626 |
|
|
return (-1);
|
| 627 |
|
|
st->l1.bcs = bcs;
|
| 628 |
|
|
st->l2.l2l1 = hfc_l2l1;
|
| 629 |
|
|
setstack_manager(st);
|
| 630 |
|
|
bcs->st = st;
|
| 631 |
|
|
setstack_l1_B(st);
|
| 632 |
|
|
return (0);
|
| 633 |
|
|
}
|
| 634 |
|
|
|
| 635 |
|
|
static void
|
| 636 |
|
|
hfcd_bh(struct IsdnCardState *cs)
|
| 637 |
|
|
{
|
| 638 |
|
|
/* struct PStack *stptr;
|
| 639 |
|
|
*/
|
| 640 |
|
|
if (!cs)
|
| 641 |
|
|
return;
|
| 642 |
|
|
#if 0
|
| 643 |
|
|
if (test_and_clear_bit(D_CLEARBUSY, &cs->event)) {
|
| 644 |
|
|
if (cs->debug)
|
| 645 |
|
|
debugl1(cs, "D-Channel Busy cleared");
|
| 646 |
|
|
stptr = cs->stlist;
|
| 647 |
|
|
while (stptr != NULL) {
|
| 648 |
|
|
stptr->l1.l1l2(stptr, PH_PAUSE | CONFIRM, NULL);
|
| 649 |
|
|
stptr = stptr->next;
|
| 650 |
|
|
}
|
| 651 |
|
|
}
|
| 652 |
|
|
#endif
|
| 653 |
|
|
if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) {
|
| 654 |
|
|
switch (cs->ph_state) {
|
| 655 |
|
|
case (0):
|
| 656 |
|
|
l1_msg(cs, HW_RESET | INDICATION, NULL);
|
| 657 |
|
|
break;
|
| 658 |
|
|
case (3):
|
| 659 |
|
|
l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
|
| 660 |
|
|
break;
|
| 661 |
|
|
case (8):
|
| 662 |
|
|
l1_msg(cs, HW_RSYNC | INDICATION, NULL);
|
| 663 |
|
|
break;
|
| 664 |
|
|
case (6):
|
| 665 |
|
|
l1_msg(cs, HW_INFO2 | INDICATION, NULL);
|
| 666 |
|
|
break;
|
| 667 |
|
|
case (7):
|
| 668 |
|
|
l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
|
| 669 |
|
|
break;
|
| 670 |
|
|
default:
|
| 671 |
|
|
break;
|
| 672 |
|
|
}
|
| 673 |
|
|
}
|
| 674 |
|
|
if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))
|
| 675 |
|
|
DChannel_proc_rcv(cs);
|
| 676 |
|
|
if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))
|
| 677 |
|
|
DChannel_proc_xmt(cs);
|
| 678 |
|
|
}
|
| 679 |
|
|
|
| 680 |
|
|
void
|
| 681 |
|
|
sched_event_D(struct IsdnCardState *cs, int event)
|
| 682 |
|
|
{
|
| 683 |
|
|
test_and_set_bit(event, &cs->event);
|
| 684 |
|
|
queue_task(&cs->tqueue, &tq_immediate);
|
| 685 |
|
|
mark_bh(IMMEDIATE_BH);
|
| 686 |
|
|
}
|
| 687 |
|
|
|
| 688 |
|
|
static
|
| 689 |
|
|
int receive_dmsg(struct IsdnCardState *cs)
|
| 690 |
|
|
{
|
| 691 |
|
|
struct sk_buff *skb;
|
| 692 |
|
|
long flags;
|
| 693 |
|
|
int idx;
|
| 694 |
|
|
int rcnt, z1, z2;
|
| 695 |
|
|
u_char stat, cip, f1, f2;
|
| 696 |
|
|
int chksum;
|
| 697 |
|
|
int count=5;
|
| 698 |
|
|
u_char *ptr;
|
| 699 |
|
|
|
| 700 |
|
|
save_flags(flags);
|
| 701 |
|
|
cli();
|
| 702 |
|
|
if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
|
| 703 |
|
|
debugl1(cs, "rec_dmsg blocked");
|
| 704 |
|
|
restore_flags(flags);
|
| 705 |
|
|
return(1);
|
| 706 |
|
|
}
|
| 707 |
|
|
SelFiFo(cs, 4 | HFCD_REC);
|
| 708 |
|
|
cip = HFCD_FIFO | HFCD_F1 | HFCD_REC;
|
| 709 |
|
|
WaitNoBusy(cs);
|
| 710 |
|
|
f1 = cs->readisac(cs, cip) & 0xf;
|
| 711 |
|
|
cip = HFCD_FIFO | HFCD_F2 | HFCD_REC;
|
| 712 |
|
|
WaitNoBusy(cs);
|
| 713 |
|
|
f2 = cs->readisac(cs, cip) & 0xf;
|
| 714 |
|
|
while ((f1 != f2) && count--) {
|
| 715 |
|
|
z1 = ReadZReg(cs, HFCD_FIFO | HFCD_Z1 | HFCD_REC);
|
| 716 |
|
|
z2 = ReadZReg(cs, HFCD_FIFO | HFCD_Z2 | HFCD_REC);
|
| 717 |
|
|
rcnt = z1 - z2;
|
| 718 |
|
|
if (rcnt < 0)
|
| 719 |
|
|
rcnt += cs->hw.hfcD.dfifosize;
|
| 720 |
|
|
rcnt++;
|
| 721 |
|
|
if (cs->debug & L1_DEB_ISAC)
|
| 722 |
|
|
debugl1(cs, "hfcd recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)",
|
| 723 |
|
|
f1, f2, z1, z2, rcnt);
|
| 724 |
|
|
sti();
|
| 725 |
|
|
idx = 0;
|
| 726 |
|
|
cip = HFCD_FIFO | HFCD_FIFO_OUT | HFCD_REC;
|
| 727 |
|
|
if (rcnt > MAX_DFRAME_LEN + 3) {
|
| 728 |
|
|
if (cs->debug & L1_DEB_WARN)
|
| 729 |
|
|
debugl1(cs, "empty_fifo d: incoming packet too large");
|
| 730 |
|
|
while (idx < rcnt) {
|
| 731 |
|
|
cli();
|
| 732 |
|
|
if (!(WaitNoBusy(cs)))
|
| 733 |
|
|
break;
|
| 734 |
|
|
ReadReg(cs, HFCD_DATA_NODEB, cip);
|
| 735 |
|
|
sti();
|
| 736 |
|
|
idx++;
|
| 737 |
|
|
}
|
| 738 |
|
|
} else if (rcnt < 4) {
|
| 739 |
|
|
if (cs->debug & L1_DEB_WARN)
|
| 740 |
|
|
debugl1(cs, "empty_fifo d: incoming packet too small");
|
| 741 |
|
|
cli();
|
| 742 |
|
|
while ((idx++ < rcnt) && WaitNoBusy(cs))
|
| 743 |
|
|
ReadReg(cs, HFCD_DATA_NODEB, cip);
|
| 744 |
|
|
} else if ((skb = dev_alloc_skb(rcnt - 3))) {
|
| 745 |
|
|
SET_SKB_FREE(skb);
|
| 746 |
|
|
ptr = skb_put(skb, rcnt - 3);
|
| 747 |
|
|
while (idx < (rcnt - 3)) {
|
| 748 |
|
|
cli();
|
| 749 |
|
|
if (!(WaitNoBusy(cs)))
|
| 750 |
|
|
break;
|
| 751 |
|
|
*ptr = ReadReg(cs, HFCD_DATA_NODEB, cip);
|
| 752 |
|
|
sti();
|
| 753 |
|
|
idx++;
|
| 754 |
|
|
ptr++;
|
| 755 |
|
|
}
|
| 756 |
|
|
if (idx != (rcnt - 3)) {
|
| 757 |
|
|
sti();
|
| 758 |
|
|
debugl1(cs, "RFIFO D BUSY error");
|
| 759 |
|
|
printk(KERN_WARNING "HFC DFIFO channel BUSY Error\n");
|
| 760 |
|
|
dev_kfree_skb(skb, FREE_READ);
|
| 761 |
|
|
skb = NULL;
|
| 762 |
|
|
} else {
|
| 763 |
|
|
cli();
|
| 764 |
|
|
WaitNoBusy(cs);
|
| 765 |
|
|
chksum = (ReadReg(cs, HFCD_DATA, cip) << 8);
|
| 766 |
|
|
WaitNoBusy(cs);
|
| 767 |
|
|
chksum += ReadReg(cs, HFCD_DATA, cip);
|
| 768 |
|
|
WaitNoBusy(cs);
|
| 769 |
|
|
stat = ReadReg(cs, HFCD_DATA, cip);
|
| 770 |
|
|
sti();
|
| 771 |
|
|
if (cs->debug & L1_DEB_ISAC)
|
| 772 |
|
|
debugl1(cs, "empty_dfifo chksum %x stat %x",
|
| 773 |
|
|
chksum, stat);
|
| 774 |
|
|
if (stat) {
|
| 775 |
|
|
debugl1(cs, "FIFO CRC error");
|
| 776 |
|
|
dev_kfree_skb(skb, FREE_READ);
|
| 777 |
|
|
skb = NULL;
|
| 778 |
|
|
} else {
|
| 779 |
|
|
skb_queue_tail(&cs->rq, skb);
|
| 780 |
|
|
sched_event_D(cs, D_RCVBUFREADY);
|
| 781 |
|
|
}
|
| 782 |
|
|
}
|
| 783 |
|
|
} else
|
| 784 |
|
|
printk(KERN_WARNING "HFC: D receive out of memory\n");
|
| 785 |
|
|
sti();
|
| 786 |
|
|
WaitForBusy(cs);
|
| 787 |
|
|
cip = HFCD_FIFO | HFCD_F2_INC | HFCD_REC;
|
| 788 |
|
|
cli();
|
| 789 |
|
|
WaitNoBusy(cs);
|
| 790 |
|
|
stat = ReadReg(cs, HFCD_DATA, cip);
|
| 791 |
|
|
sti();
|
| 792 |
|
|
WaitForBusy(cs);
|
| 793 |
|
|
cip = HFCD_FIFO | HFCD_F2 | HFCD_REC;
|
| 794 |
|
|
cli();
|
| 795 |
|
|
WaitNoBusy(cs);
|
| 796 |
|
|
f2 = cs->readisac(cs, cip) & 0xf;
|
| 797 |
|
|
}
|
| 798 |
|
|
test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
|
| 799 |
|
|
restore_flags(flags);
|
| 800 |
|
|
return(1);
|
| 801 |
|
|
}
|
| 802 |
|
|
|
| 803 |
|
|
static void
|
| 804 |
|
|
hfc_fill_dfifo(struct IsdnCardState *cs)
|
| 805 |
|
|
{
|
| 806 |
|
|
long flags;
|
| 807 |
|
|
int idx, fcnt;
|
| 808 |
|
|
int count;
|
| 809 |
|
|
u_char cip;
|
| 810 |
|
|
|
| 811 |
|
|
if (!cs->tx_skb)
|
| 812 |
|
|
return;
|
| 813 |
|
|
if (cs->tx_skb->len <= 0)
|
| 814 |
|
|
return;
|
| 815 |
|
|
|
| 816 |
|
|
save_flags(flags);
|
| 817 |
|
|
cli();
|
| 818 |
|
|
SelFiFo(cs, 4 | HFCD_SEND);
|
| 819 |
|
|
cip = HFCD_FIFO | HFCD_F1 | HFCD_SEND;
|
| 820 |
|
|
WaitNoBusy(cs);
|
| 821 |
|
|
cs->hw.hfcD.f1 = ReadReg(cs, HFCD_DATA, cip) & 0xf;
|
| 822 |
|
|
WaitNoBusy(cs);
|
| 823 |
|
|
cip = HFCD_FIFO | HFCD_F2 | HFCD_SEND;
|
| 824 |
|
|
cs->hw.hfcD.f2 = ReadReg(cs, HFCD_DATA, cip) & 0xf;
|
| 825 |
|
|
cs->hw.hfcD.send[cs->hw.hfcD.f1] = ReadZReg(cs, HFCD_FIFO | HFCD_Z1 | HFCD_SEND);
|
| 826 |
|
|
sti();
|
| 827 |
|
|
if (cs->debug & L1_DEB_ISAC)
|
| 828 |
|
|
debugl1(cs, "hfc_fill_Dfifo f1(%d) f2(%d) z1(%x)",
|
| 829 |
|
|
cs->hw.hfcD.f1, cs->hw.hfcD.f2,
|
| 830 |
|
|
cs->hw.hfcD.send[cs->hw.hfcD.f1]);
|
| 831 |
|
|
fcnt = cs->hw.hfcD.f1 - cs->hw.hfcD.f2;
|
| 832 |
|
|
if (fcnt < 0)
|
| 833 |
|
|
fcnt += 16;
|
| 834 |
|
|
if (fcnt > 14) {
|
| 835 |
|
|
if (cs->debug & L1_DEB_HSCX)
|
| 836 |
|
|
debugl1(cs, "hfc_fill_Dfifo more as 14 frames");
|
| 837 |
|
|
restore_flags(flags);
|
| 838 |
|
|
return;
|
| 839 |
|
|
}
|
| 840 |
|
|
count = GetFreeFifoBytes_D(cs);
|
| 841 |
|
|
if (cs->debug & L1_DEB_ISAC)
|
| 842 |
|
|
debugl1(cs, "hfc_fill_Dfifo count(%ld/%d)",
|
| 843 |
|
|
cs->tx_skb->len, count);
|
| 844 |
|
|
if (count < cs->tx_skb->len) {
|
| 845 |
|
|
if (cs->debug & L1_DEB_ISAC)
|
| 846 |
|
|
debugl1(cs, "hfc_fill_Dfifo no fifo mem");
|
| 847 |
|
|
restore_flags(flags);
|
| 848 |
|
|
return;
|
| 849 |
|
|
}
|
| 850 |
|
|
cip = HFCD_FIFO | HFCD_FIFO_IN | HFCD_SEND;
|
| 851 |
|
|
idx = 0;
|
| 852 |
|
|
cli();
|
| 853 |
|
|
WaitForBusy(cs);
|
| 854 |
|
|
WaitNoBusy(cs);
|
| 855 |
|
|
WriteReg(cs, HFCD_DATA_NODEB, cip, cs->tx_skb->data[idx++]);
|
| 856 |
|
|
while (idx < cs->tx_skb->len) {
|
| 857 |
|
|
cli();
|
| 858 |
|
|
if (!(WaitNoBusy(cs)))
|
| 859 |
|
|
break;
|
| 860 |
|
|
WriteReg(cs, HFCD_DATA_NODEB, cip, cs->tx_skb->data[idx]);
|
| 861 |
|
|
sti();
|
| 862 |
|
|
idx++;
|
| 863 |
|
|
}
|
| 864 |
|
|
if (idx != cs->tx_skb->len) {
|
| 865 |
|
|
sti();
|
| 866 |
|
|
debugl1(cs, "DFIFO Send BUSY error");
|
| 867 |
|
|
printk(KERN_WARNING "HFC S DFIFO channel BUSY Error\n");
|
| 868 |
|
|
}
|
| 869 |
|
|
WaitForBusy(cs);
|
| 870 |
|
|
cli();
|
| 871 |
|
|
WaitNoBusy(cs);
|
| 872 |
|
|
ReadReg(cs, HFCD_DATA, HFCD_FIFO | HFCD_F1_INC | HFCD_SEND);
|
| 873 |
|
|
dev_kfree_skb(cs->tx_skb, FREE_WRITE);
|
| 874 |
|
|
cs->tx_skb = NULL;
|
| 875 |
|
|
sti();
|
| 876 |
|
|
WaitForBusy(cs);
|
| 877 |
|
|
restore_flags(flags);
|
| 878 |
|
|
return;
|
| 879 |
|
|
}
|
| 880 |
|
|
|
| 881 |
|
|
static
|
| 882 |
|
|
struct BCState *Sel_BCS(struct IsdnCardState *cs, int channel)
|
| 883 |
|
|
{
|
| 884 |
|
|
if (cs->bcs[0].mode && (cs->bcs[0].channel == channel))
|
| 885 |
|
|
return(&cs->bcs[0]);
|
| 886 |
|
|
else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel))
|
| 887 |
|
|
return(&cs->bcs[1]);
|
| 888 |
|
|
else
|
| 889 |
|
|
return(NULL);
|
| 890 |
|
|
}
|
| 891 |
|
|
|
| 892 |
|
|
void
|
| 893 |
|
|
hfc2bds0_interrupt(struct IsdnCardState *cs, u_char val)
|
| 894 |
|
|
{
|
| 895 |
|
|
u_char exval;
|
| 896 |
|
|
struct BCState *bcs;
|
| 897 |
|
|
int count=15;
|
| 898 |
|
|
long flags;
|
| 899 |
|
|
|
| 900 |
|
|
if (cs->debug & L1_DEB_ISAC)
|
| 901 |
|
|
debugl1(cs, "HFCD irq %x %s", val,
|
| 902 |
|
|
test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags) ?
|
| 903 |
|
|
"locked" : "unlocked");
|
| 904 |
|
|
val &= cs->hw.hfcD.int_m1;
|
| 905 |
|
|
if (val & 0x40) { /* TE state machine irq */
|
| 906 |
|
|
exval = cs->readisac(cs, HFCD_STATES) & 0xf;
|
| 907 |
|
|
if (cs->debug & L1_DEB_ISAC)
|
| 908 |
|
|
debugl1(cs, "ph_state chg %d->%d", cs->ph_state,
|
| 909 |
|
|
exval);
|
| 910 |
|
|
cs->ph_state = exval;
|
| 911 |
|
|
sched_event_D(cs, D_L1STATECHANGE);
|
| 912 |
|
|
val &= ~0x40;
|
| 913 |
|
|
}
|
| 914 |
|
|
while (val) {
|
| 915 |
|
|
save_flags(flags);
|
| 916 |
|
|
cli();
|
| 917 |
|
|
if (test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
|
| 918 |
|
|
cs->hw.hfcD.int_s1 |= val;
|
| 919 |
|
|
restore_flags(flags);
|
| 920 |
|
|
return;
|
| 921 |
|
|
}
|
| 922 |
|
|
if (cs->hw.hfcD.int_s1 & 0x18) {
|
| 923 |
|
|
exval = val;
|
| 924 |
|
|
val = cs->hw.hfcD.int_s1;
|
| 925 |
|
|
cs->hw.hfcD.int_s1 = exval;
|
| 926 |
|
|
}
|
| 927 |
|
|
if (val & 0x08) {
|
| 928 |
|
|
if (!(bcs=Sel_BCS(cs, 0))) {
|
| 929 |
|
|
if (cs->debug)
|
| 930 |
|
|
debugl1(cs, "hfcd spurious 0x08 IRQ");
|
| 931 |
|
|
} else
|
| 932 |
|
|
main_rec_2bds0(bcs);
|
| 933 |
|
|
}
|
| 934 |
|
|
if (val & 0x10) {
|
| 935 |
|
|
if (!(bcs=Sel_BCS(cs, 1))) {
|
| 936 |
|
|
if (cs->debug)
|
| 937 |
|
|
debugl1(cs, "hfcd spurious 0x10 IRQ");
|
| 938 |
|
|
} else
|
| 939 |
|
|
main_rec_2bds0(bcs);
|
| 940 |
|
|
}
|
| 941 |
|
|
if (val & 0x01) {
|
| 942 |
|
|
if (!(bcs=Sel_BCS(cs, 0))) {
|
| 943 |
|
|
if (cs->debug)
|
| 944 |
|
|
debugl1(cs, "hfcd spurious 0x01 IRQ");
|
| 945 |
|
|
} else {
|
| 946 |
|
|
if (bcs->tx_skb) {
|
| 947 |
|
|
if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
|
| 948 |
|
|
hfc_fill_fifo(bcs);
|
| 949 |
|
|
test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
|
| 950 |
|
|
} else
|
| 951 |
|
|
debugl1(cs,"fill_data %d blocked", bcs->channel);
|
| 952 |
|
|
} else {
|
| 953 |
|
|
if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
|
| 954 |
|
|
if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
|
| 955 |
|
|
hfc_fill_fifo(bcs);
|
| 956 |
|
|
test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
|
| 957 |
|
|
} else
|
| 958 |
|
|
debugl1(cs,"fill_data %d blocked", bcs->channel);
|
| 959 |
|
|
} else {
|
| 960 |
|
|
hfc_sched_event(bcs, B_XMTBUFREADY);
|
| 961 |
|
|
}
|
| 962 |
|
|
}
|
| 963 |
|
|
}
|
| 964 |
|
|
}
|
| 965 |
|
|
if (val & 0x02) {
|
| 966 |
|
|
if (!(bcs=Sel_BCS(cs, 1))) {
|
| 967 |
|
|
if (cs->debug)
|
| 968 |
|
|
debugl1(cs, "hfcd spurious 0x02 IRQ");
|
| 969 |
|
|
} else {
|
| 970 |
|
|
if (bcs->tx_skb) {
|
| 971 |
|
|
if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
|
| 972 |
|
|
hfc_fill_fifo(bcs);
|
| 973 |
|
|
test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
|
| 974 |
|
|
} else
|
| 975 |
|
|
debugl1(cs,"fill_data %d blocked", bcs->channel);
|
| 976 |
|
|
} else {
|
| 977 |
|
|
if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
|
| 978 |
|
|
if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
|
| 979 |
|
|
hfc_fill_fifo(bcs);
|
| 980 |
|
|
test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
|
| 981 |
|
|
} else
|
| 982 |
|
|
debugl1(cs,"fill_data %d blocked", bcs->channel);
|
| 983 |
|
|
} else {
|
| 984 |
|
|
hfc_sched_event(bcs, B_XMTBUFREADY);
|
| 985 |
|
|
}
|
| 986 |
|
|
}
|
| 987 |
|
|
}
|
| 988 |
|
|
}
|
| 989 |
|
|
if (val & 0x20) { /* receive dframe */
|
| 990 |
|
|
receive_dmsg(cs);
|
| 991 |
|
|
}
|
| 992 |
|
|
if (val & 0x04) { /* dframe transmitted */
|
| 993 |
|
|
if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
|
| 994 |
|
|
del_timer(&cs->dbusytimer);
|
| 995 |
|
|
if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
|
| 996 |
|
|
sched_event_D(cs, D_CLEARBUSY);
|
| 997 |
|
|
if (cs->tx_skb)
|
| 998 |
|
|
if (cs->tx_skb->len) {
|
| 999 |
|
|
if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
|
| 1000 |
|
|
hfc_fill_dfifo(cs);
|
| 1001 |
|
|
test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
|
| 1002 |
|
|
} else {
|
| 1003 |
|
|
debugl1(cs, "hfc_fill_dfifo irq blocked");
|
| 1004 |
|
|
}
|
| 1005 |
|
|
goto afterXPR;
|
| 1006 |
|
|
} else {
|
| 1007 |
|
|
dev_kfree_skb(cs->tx_skb, FREE_WRITE);
|
| 1008 |
|
|
cs->tx_cnt = 0;
|
| 1009 |
|
|
cs->tx_skb = NULL;
|
| 1010 |
|
|
}
|
| 1011 |
|
|
if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
|
| 1012 |
|
|
cs->tx_cnt = 0;
|
| 1013 |
|
|
if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
|
| 1014 |
|
|
hfc_fill_dfifo(cs);
|
| 1015 |
|
|
test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
|
| 1016 |
|
|
} else {
|
| 1017 |
|
|
debugl1(cs, "hfc_fill_dfifo irq blocked");
|
| 1018 |
|
|
}
|
| 1019 |
|
|
} else
|
| 1020 |
|
|
sched_event_D(cs, D_XMTBUFREADY);
|
| 1021 |
|
|
}
|
| 1022 |
|
|
afterXPR:
|
| 1023 |
|
|
if (cs->hw.hfcD.int_s1 && count--) {
|
| 1024 |
|
|
val = cs->hw.hfcD.int_s1;
|
| 1025 |
|
|
cs->hw.hfcD.int_s1 = 0;
|
| 1026 |
|
|
if (cs->debug & L1_DEB_ISAC)
|
| 1027 |
|
|
debugl1(cs, "HFCD irq %x loop %d", val, 15-count);
|
| 1028 |
|
|
} else
|
| 1029 |
|
|
val = 0;
|
| 1030 |
|
|
restore_flags(flags);
|
| 1031 |
|
|
}
|
| 1032 |
|
|
}
|
| 1033 |
|
|
|
| 1034 |
|
|
static void
|
| 1035 |
|
|
HFCD_l1hw(struct PStack *st, int pr, void *arg)
|
| 1036 |
|
|
{
|
| 1037 |
|
|
struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
|
| 1038 |
|
|
struct sk_buff *skb = arg;
|
| 1039 |
|
|
|
| 1040 |
|
|
switch (pr) {
|
| 1041 |
|
|
case (PH_DATA | REQUEST):
|
| 1042 |
|
|
if (cs->debug & DEB_DLOG_HEX)
|
| 1043 |
|
|
LogFrame(cs, skb->data, skb->len);
|
| 1044 |
|
|
if (cs->debug & DEB_DLOG_VERBOSE)
|
| 1045 |
|
|
dlogframe(cs, skb, 0);
|
| 1046 |
|
|
if (cs->tx_skb) {
|
| 1047 |
|
|
skb_queue_tail(&cs->sq, skb);
|
| 1048 |
|
|
#ifdef L2FRAME_DEBUG /* psa */
|
| 1049 |
|
|
if (cs->debug & L1_DEB_LAPD)
|
| 1050 |
|
|
Logl2Frame(cs, skb, "PH_DATA Queued", 0);
|
| 1051 |
|
|
#endif
|
| 1052 |
|
|
} else {
|
| 1053 |
|
|
cs->tx_skb = skb;
|
| 1054 |
|
|
cs->tx_cnt = 0;
|
| 1055 |
|
|
#ifdef L2FRAME_DEBUG /* psa */
|
| 1056 |
|
|
if (cs->debug & L1_DEB_LAPD)
|
| 1057 |
|
|
Logl2Frame(cs, skb, "PH_DATA", 0);
|
| 1058 |
|
|
#endif
|
| 1059 |
|
|
if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
|
| 1060 |
|
|
hfc_fill_dfifo(cs);
|
| 1061 |
|
|
test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
|
| 1062 |
|
|
} else
|
| 1063 |
|
|
debugl1(cs, "hfc_fill_dfifo blocked");
|
| 1064 |
|
|
|
| 1065 |
|
|
}
|
| 1066 |
|
|
break;
|
| 1067 |
|
|
case (PH_PULL | INDICATION):
|
| 1068 |
|
|
if (cs->tx_skb) {
|
| 1069 |
|
|
if (cs->debug & L1_DEB_WARN)
|
| 1070 |
|
|
debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
|
| 1071 |
|
|
skb_queue_tail(&cs->sq, skb);
|
| 1072 |
|
|
break;
|
| 1073 |
|
|
}
|
| 1074 |
|
|
if (cs->debug & DEB_DLOG_HEX)
|
| 1075 |
|
|
LogFrame(cs, skb->data, skb->len);
|
| 1076 |
|
|
if (cs->debug & DEB_DLOG_VERBOSE)
|
| 1077 |
|
|
dlogframe(cs, skb, 0);
|
| 1078 |
|
|
cs->tx_skb = skb;
|
| 1079 |
|
|
cs->tx_cnt = 0;
|
| 1080 |
|
|
#ifdef L2FRAME_DEBUG /* psa */
|
| 1081 |
|
|
if (cs->debug & L1_DEB_LAPD)
|
| 1082 |
|
|
Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
|
| 1083 |
|
|
#endif
|
| 1084 |
|
|
if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
|
| 1085 |
|
|
hfc_fill_dfifo(cs);
|
| 1086 |
|
|
test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
|
| 1087 |
|
|
} else
|
| 1088 |
|
|
debugl1(cs, "hfc_fill_dfifo blocked");
|
| 1089 |
|
|
break;
|
| 1090 |
|
|
case (PH_PULL | REQUEST):
|
| 1091 |
|
|
#ifdef L2FRAME_DEBUG /* psa */
|
| 1092 |
|
|
if (cs->debug & L1_DEB_LAPD)
|
| 1093 |
|
|
debugl1(cs, "-> PH_REQUEST_PULL");
|
| 1094 |
|
|
#endif
|
| 1095 |
|
|
if (!cs->tx_skb) {
|
| 1096 |
|
|
test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
|
| 1097 |
|
|
st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
|
| 1098 |
|
|
} else
|
| 1099 |
|
|
test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
|
| 1100 |
|
|
break;
|
| 1101 |
|
|
case (HW_RESET | REQUEST):
|
| 1102 |
|
|
cs->writeisac(cs, HFCD_STATES, HFCD_LOAD_STATE | 3); /* HFC ST 3 */
|
| 1103 |
|
|
udelay(6);
|
| 1104 |
|
|
cs->writeisac(cs, HFCD_STATES, 3); /* HFC ST 2 */
|
| 1105 |
|
|
cs->hw.hfcD.mst_m |= HFCD_MASTER;
|
| 1106 |
|
|
cs->writeisac(cs, HFCD_MST_MODE, cs->hw.hfcD.mst_m);
|
| 1107 |
|
|
cs->writeisac(cs, HFCD_STATES, HFCD_ACTIVATE | HFCD_DO_ACTION);
|
| 1108 |
|
|
l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
|
| 1109 |
|
|
break;
|
| 1110 |
|
|
case (HW_ENABLE | REQUEST):
|
| 1111 |
|
|
cs->writeisac(cs, HFCD_STATES, HFCD_ACTIVATE | HFCD_DO_ACTION);
|
| 1112 |
|
|
break;
|
| 1113 |
|
|
case (HW_DEACTIVATE | REQUEST):
|
| 1114 |
|
|
cs->hw.hfcD.mst_m &= ~HFCD_MASTER;
|
| 1115 |
|
|
cs->writeisac(cs, HFCD_MST_MODE, cs->hw.hfcD.mst_m);
|
| 1116 |
|
|
break;
|
| 1117 |
|
|
case (HW_INFO3 | REQUEST):
|
| 1118 |
|
|
cs->hw.hfcD.mst_m |= HFCD_MASTER;
|
| 1119 |
|
|
cs->writeisac(cs, HFCD_MST_MODE, cs->hw.hfcD.mst_m);
|
| 1120 |
|
|
break;
|
| 1121 |
|
|
#if 0
|
| 1122 |
|
|
case (HW_TESTLOOP | REQUEST):
|
| 1123 |
|
|
u_char val = 0;
|
| 1124 |
|
|
if (1 & (int) arg)
|
| 1125 |
|
|
val |= 0x0c;
|
| 1126 |
|
|
if (2 & (int) arg)
|
| 1127 |
|
|
val |= 0x3;
|
| 1128 |
|
|
if (test_bit(HW_IOM1, &cs->HW_Flags)) {
|
| 1129 |
|
|
/* IOM 1 Mode */
|
| 1130 |
|
|
if (!val) {
|
| 1131 |
|
|
cs->writeisac(cs, ISAC_SPCR, 0xa);
|
| 1132 |
|
|
cs->writeisac(cs, ISAC_ADF1, 0x2);
|
| 1133 |
|
|
} else {
|
| 1134 |
|
|
cs->writeisac(cs, ISAC_SPCR, val);
|
| 1135 |
|
|
cs->writeisac(cs, ISAC_ADF1, 0xa);
|
| 1136 |
|
|
}
|
| 1137 |
|
|
} else {
|
| 1138 |
|
|
/* IOM 2 Mode */
|
| 1139 |
|
|
cs->writeisac(cs, ISAC_SPCR, val);
|
| 1140 |
|
|
if (val)
|
| 1141 |
|
|
cs->writeisac(cs, ISAC_ADF1, 0x8);
|
| 1142 |
|
|
else
|
| 1143 |
|
|
cs->writeisac(cs, ISAC_ADF1, 0x0);
|
| 1144 |
|
|
}
|
| 1145 |
|
|
break;
|
| 1146 |
|
|
#endif
|
| 1147 |
|
|
default:
|
| 1148 |
|
|
if (cs->debug & L1_DEB_WARN)
|
| 1149 |
|
|
debugl1(cs, "hfcd_l1hw unknown pr %4x", pr);
|
| 1150 |
|
|
break;
|
| 1151 |
|
|
}
|
| 1152 |
|
|
}
|
| 1153 |
|
|
|
| 1154 |
|
|
void
|
| 1155 |
|
|
setstack_hfcd(struct PStack *st, struct IsdnCardState *cs)
|
| 1156 |
|
|
{
|
| 1157 |
|
|
st->l1.l1hw = HFCD_l1hw;
|
| 1158 |
|
|
}
|
| 1159 |
|
|
|
| 1160 |
|
|
static void
|
| 1161 |
|
|
hfc_dbusy_timer(struct IsdnCardState *cs)
|
| 1162 |
|
|
{
|
| 1163 |
|
|
#if 0
|
| 1164 |
|
|
struct PStack *stptr;
|
| 1165 |
|
|
if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
|
| 1166 |
|
|
if (cs->debug)
|
| 1167 |
|
|
debugl1(cs, "D-Channel Busy");
|
| 1168 |
|
|
test_and_set_bit(FLG_L1_DBUSY, &cs->HW_Flags);
|
| 1169 |
|
|
stptr = cs->stlist;
|
| 1170 |
|
|
|
| 1171 |
|
|
while (stptr != NULL) {
|
| 1172 |
|
|
stptr->l1.l1l2(stptr, PH_PAUSE | INDICATION, NULL);
|
| 1173 |
|
|
stptr = stptr->next;
|
| 1174 |
|
|
}
|
| 1175 |
|
|
}
|
| 1176 |
|
|
#endif
|
| 1177 |
|
|
}
|
| 1178 |
|
|
|
| 1179 |
|
|
__initfunc(unsigned int
|
| 1180 |
|
|
*init_send_hfcd(int cnt))
|
| 1181 |
|
|
{
|
| 1182 |
|
|
int i, *send;
|
| 1183 |
|
|
|
| 1184 |
|
|
if (!(send = kmalloc(cnt * sizeof(unsigned int), GFP_ATOMIC))) {
|
| 1185 |
|
|
printk(KERN_WARNING
|
| 1186 |
|
|
"HiSax: No memory for hfcd.send\n");
|
| 1187 |
|
|
return(NULL);
|
| 1188 |
|
|
}
|
| 1189 |
|
|
for (i = 0; i < cnt; i++)
|
| 1190 |
|
|
send[i] = 0x1fff;
|
| 1191 |
|
|
return(send);
|
| 1192 |
|
|
}
|
| 1193 |
|
|
|
| 1194 |
|
|
__initfunc(void
|
| 1195 |
|
|
init2bds0(struct IsdnCardState *cs))
|
| 1196 |
|
|
{
|
| 1197 |
|
|
cs->setstack_d = setstack_hfcd;
|
| 1198 |
|
|
cs->dbusytimer.function = (void *) hfc_dbusy_timer;
|
| 1199 |
|
|
cs->dbusytimer.data = (long) cs;
|
| 1200 |
|
|
init_timer(&cs->dbusytimer);
|
| 1201 |
|
|
cs->tqueue.routine = (void *) (void *) hfcd_bh;
|
| 1202 |
|
|
if (!cs->hw.hfcD.send)
|
| 1203 |
|
|
cs->hw.hfcD.send = init_send_hfcd(16);
|
| 1204 |
|
|
if (!cs->bcs[0].hw.hfc.send)
|
| 1205 |
|
|
cs->bcs[0].hw.hfc.send = init_send_hfcd(32);
|
| 1206 |
|
|
if (!cs->bcs[1].hw.hfc.send)
|
| 1207 |
|
|
cs->bcs[1].hw.hfc.send = init_send_hfcd(32);
|
| 1208 |
|
|
cs->BC_Send_Data = &hfc_send_data;
|
| 1209 |
|
|
cs->bcs[0].BC_SetStack = setstack_2b;
|
| 1210 |
|
|
cs->bcs[1].BC_SetStack = setstack_2b;
|
| 1211 |
|
|
cs->bcs[0].BC_Close = close_2bs0;
|
| 1212 |
|
|
cs->bcs[1].BC_Close = close_2bs0;
|
| 1213 |
|
|
mode_2bs0(cs->bcs, 0, 0);
|
| 1214 |
|
|
mode_2bs0(cs->bcs + 1, 0, 1);
|
| 1215 |
|
|
}
|
| 1216 |
|
|
|
| 1217 |
|
|
void
|
| 1218 |
|
|
release2bds0(struct IsdnCardState *cs)
|
| 1219 |
|
|
{
|
| 1220 |
|
|
if (cs->bcs[0].hw.hfc.send) {
|
| 1221 |
|
|
kfree(cs->bcs[0].hw.hfc.send);
|
| 1222 |
|
|
cs->bcs[0].hw.hfc.send = NULL;
|
| 1223 |
|
|
}
|
| 1224 |
|
|
if (cs->bcs[1].hw.hfc.send) {
|
| 1225 |
|
|
kfree(cs->bcs[1].hw.hfc.send);
|
| 1226 |
|
|
cs->bcs[1].hw.hfc.send = NULL;
|
| 1227 |
|
|
}
|
| 1228 |
|
|
if (cs->hw.hfcD.send) {
|
| 1229 |
|
|
kfree(cs->hw.hfcD.send);
|
| 1230 |
|
|
cs->hw.hfcD.send = NULL;
|
| 1231 |
|
|
}
|
| 1232 |
|
|
}
|
