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[/] [or1k/] [trunk/] [uclinux/] [uClinux-2.0.x/] [drivers/] [isdn/] [hisax/] [isac.c] - Blame information for rev 1765

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/* $Id: isac.c,v 1.1.1.1 2001-09-10 07:44:18 simons Exp $
 
 * isac.c   ISAC specific routines
 *
 * Author       Karsten Keil (keil@isdn4linux.de)
 *
 *              This file is (c) under GNU PUBLIC LICENSE
 *              For changes and modifications please read
 *              ../../../Documentation/isdn/HiSax.cert
 *
 * $Log: not supported by cvs2svn $
 * Revision 1.1.1.1  2001/07/02 17:58:32  simons
 * Initial revision
 *
 * Revision 1.7.2.9  1998/11/03 00:06:41  keil
 * certification related changes
 * fixed logging for smaller stack use
 *
 * Revision 1.7.2.8  1998/09/27 13:06:18  keil
 * Apply most changes from 2.1.X (HiSax 3.1)
 *
 * Revision 1.7.2.7  1998/05/27 18:05:38  keil
 * HiSax 3.0
 *
 * Revision 1.7.2.6  1998/04/08 21:57:31  keil
 * New init code to fix problems during init if S0 is allready activ
 *
 * Revision 1.7.2.5  1998/03/07 23:15:24  tsbogend
 * made HiSax working on Linux/Alpha
 *
 * Revision 1.7.2.4  1998/02/09 11:24:06  keil
 * New leased line support (Read README.HiSax!)
 *
 * Revision 1.7.2.3  1998/01/11 22:58:55  keil
 * new setstack interface
 *
 * Revision 1.7.2.2  1997/11/15 18:54:23  keil
 * cosmetics
 *
 * Revision 1.7.2.1  1997/10/17 22:10:49  keil
 * new files on 2.0
 *
 * Revision 1.6  1997/08/15 17:47:08  keil
 * avoid oops because a uninitialised timer
 *
 * Revision 1.5  1997/08/07 17:48:49  keil
 * fix wrong parenthesis
 *
 * Revision 1.4  1997/07/30 17:11:59  keil
 * fixed Timer3
 *
 * Revision 1.3  1997/07/27 21:37:40  keil
 * T3 implemented; supervisor l1timer; B-channel TEST_LOOP
 *
 * Revision 1.2  1997/06/26 11:16:15  keil
 * first version
 *
 *
 */
 
#define __NO_VERSION__
#include "hisax.h"
#include "isac.h"
#include "isdnl1.h"
#include <linux/interrupt.h>
 
#define DBUSY_TIMER_VALUE 80
#define ARCOFI_USE 1
 
static char *ISACVer[] HISAX_INITDATA =
{"2086/2186 V1.1", "2085 B1", "2085 B2",
 "2085 V2.3"};
 
void
ISACVersion(struct IsdnCardState *cs, char *s)
{
        int val;
 
        val = cs->readisac(cs, ISAC_RBCH);
        printk(KERN_INFO "%s ISAC version (%x): %s\n", s, val, ISACVer[(val >> 5) & 3]);
}
 
static void
ph_command(struct IsdnCardState *cs, unsigned int command)
{
        if (cs->debug & L1_DEB_ISAC)
                debugl1(cs, "ph_command %x", command);
        cs->writeisac(cs, ISAC_CIX0, (command << 2) | 3);
}
 
 
static void
isac_new_ph(struct IsdnCardState *cs)
{
        switch (cs->ph_state) {
                case (ISAC_IND_RS):
                case (ISAC_IND_EI):
                        ph_command(cs, ISAC_CMD_DUI);
                        l1_msg(cs, HW_RESET | INDICATION, NULL);
                        break;
                case (ISAC_IND_DID):
                        l1_msg(cs, HW_DEACTIVATE | CONFIRM, NULL);
                        break;
                case (ISAC_IND_DR):
                        l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
                        break;
                case (ISAC_IND_PU):
                        l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
                        break;
                case (ISAC_IND_RSY):
                        l1_msg(cs, HW_RSYNC | INDICATION, NULL);
                        break;
                case (ISAC_IND_ARD):
                        l1_msg(cs, HW_INFO2 | INDICATION, NULL);
                        break;
                case (ISAC_IND_AI8):
                        l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
                        break;
                case (ISAC_IND_AI10):
                        l1_msg(cs, HW_INFO4_P10 | INDICATION, NULL);
                        break;
                default:
                        break;
        }
}
 
static void
isac_bh(struct IsdnCardState *cs)
{
        struct PStack *stptr;
 
        if (!cs)
                return;
        if (test_and_clear_bit(D_CLEARBUSY, &cs->event)) {
                if (cs->debug)
                        debugl1(cs, "D-Channel Busy cleared");
                stptr = cs->stlist;
                while (stptr != NULL) {
                        stptr->l1.l1l2(stptr, PH_PAUSE | CONFIRM, NULL);
                        stptr = stptr->next;
                }
        }
        if (test_and_clear_bit(D_L1STATECHANGE, &cs->event))
                isac_new_ph(cs);
        if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))
                DChannel_proc_rcv(cs);
        if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))
                DChannel_proc_xmt(cs);
        if (test_and_clear_bit(D_RX_MON0, &cs->event))
                test_and_set_bit(HW_MON0_RX_END, &cs->HW_Flags);
        if (test_and_clear_bit(D_RX_MON1, &cs->event))
                test_and_set_bit(HW_MON1_RX_END, &cs->HW_Flags);
        if (test_and_clear_bit(D_TX_MON0, &cs->event))
                test_and_set_bit(HW_MON0_TX_END, &cs->HW_Flags);
        if (test_and_clear_bit(D_TX_MON1, &cs->event))
                test_and_set_bit(HW_MON1_TX_END, &cs->HW_Flags);
}
 
void
isac_empty_fifo(struct IsdnCardState *cs, int count)
{
        u_char *ptr;
        long flags;
 
        if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))
                debugl1(cs, "isac_empty_fifo");
 
        if ((cs->rcvidx + count) >= MAX_DFRAME_LEN_L1) {
                if (cs->debug & L1_DEB_WARN)
                        debugl1(cs, "isac_empty_fifo overrun %d",
                                cs->rcvidx + count);
                cs->writeisac(cs, ISAC_CMDR, 0x80);
                cs->rcvidx = 0;
                return;
        }
        ptr = cs->rcvbuf + cs->rcvidx;
        cs->rcvidx += count;
        save_flags(flags);
        cli();
        cs->readisacfifo(cs, ptr, count);
        cs->writeisac(cs, ISAC_CMDR, 0x80);
        restore_flags(flags);
        if (cs->debug & L1_DEB_ISAC_FIFO) {
                char *t = cs->dlog;
 
                t += sprintf(t, "isac_empty_fifo cnt %d", count);
                QuickHex(t, ptr, count);
                debugl1(cs, cs->dlog);
        }
}
 
static void
isac_fill_fifo(struct IsdnCardState *cs)
{
        int count, more;
        u_char *ptr;
        long flags;
 
        if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))
                debugl1(cs, "isac_fill_fifo");
 
        if (!cs->tx_skb)
                return;
 
        count = cs->tx_skb->len;
        if (count <= 0)
                return;
 
        more = 0;
        if (count > 32) {
                more = !0;
                count = 32;
        }
        save_flags(flags);
        cli();
        ptr = cs->tx_skb->data;
        skb_pull(cs->tx_skb, count);
        cs->tx_cnt += count;
        cs->writeisacfifo(cs, ptr, count);
        cs->writeisac(cs, ISAC_CMDR, more ? 0x8 : 0xa);
        restore_flags(flags);
        if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
                debugl1(cs, "isac_fill_fifo dbusytimer running");
                del_timer(&cs->dbusytimer);
        }
        init_timer(&cs->dbusytimer);
        cs->dbusytimer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000);
        add_timer(&cs->dbusytimer);
        if (cs->debug & L1_DEB_ISAC_FIFO) {
                char *t = cs->dlog;
 
                t += sprintf(t, "isac_fill_fifo cnt %d", count);
                QuickHex(t, ptr, count);
                debugl1(cs, cs->dlog);
        }
}
 
void
isac_sched_event(struct IsdnCardState *cs, int event)
{
        test_and_set_bit(event, &cs->event);
        queue_task(&cs->tqueue, &tq_immediate);
        mark_bh(IMMEDIATE_BH);
}
 
void
isac_interrupt(struct IsdnCardState *cs, u_char val)
{
        u_char exval, v1;
        struct sk_buff *skb;
        unsigned int count;
        long flags;
 
        if (cs->debug & L1_DEB_ISAC)
                debugl1(cs, "ISAC interrupt %x", val);
        if (val & 0x80) {       /* RME */
                exval = cs->readisac(cs, ISAC_RSTA);
                if ((exval & 0x70) != 0x20) {
                        if (exval & 0x40)
                                if (cs->debug & L1_DEB_WARN)
                                        debugl1(cs, "ISAC RDO");
                        if (!(exval & 0x20))
                                if (cs->debug & L1_DEB_WARN)
                                        debugl1(cs, "ISAC CRC error");
                        cs->writeisac(cs, ISAC_CMDR, 0x80);
                } else {
                        count = cs->readisac(cs, ISAC_RBCL) & 0x1f;
                        if (count == 0)
                                count = 32;
                        isac_empty_fifo(cs, count);
                        save_flags(flags);
                        cli();
                        if ((count = cs->rcvidx) > 0) {
                                cs->rcvidx = 0;
                                if (!(skb = alloc_skb(count, GFP_ATOMIC)))
                                        printk(KERN_WARNING "HiSax: D receive out of memory\n");
                                else {
                                        SET_SKB_FREE(skb);
                                        memcpy(skb_put(skb, count), cs->rcvbuf, count);
                                        skb_queue_tail(&cs->rq, skb);
                                }
                        }
                        restore_flags(flags);
                }
                cs->rcvidx = 0;
                isac_sched_event(cs, D_RCVBUFREADY);
        }
        if (val & 0x40) {       /* RPF */
                isac_empty_fifo(cs, 32);
        }
        if (val & 0x20) {       /* RSC */
                /* never */
                if (cs->debug & L1_DEB_WARN)
                        debugl1(cs, "ISAC RSC interrupt");
        }
        if (val & 0x10) {       /* XPR */
                if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
                        del_timer(&cs->dbusytimer);
                if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
                        isac_sched_event(cs, D_CLEARBUSY);
                if (cs->tx_skb) {
                        if (cs->tx_skb->len) {
                                isac_fill_fifo(cs);
                                goto afterXPR;
                        } else {
                                dev_kfree_skb(cs->tx_skb, FREE_WRITE);
                                cs->tx_cnt = 0;
                                cs->tx_skb = NULL;
                        }
                }
                if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
                        cs->tx_cnt = 0;
                        isac_fill_fifo(cs);
                } else
                        isac_sched_event(cs, D_XMTBUFREADY);
        }
      afterXPR:
        if (val & 0x04) {       /* CISQ */
                exval = cs->readisac(cs, ISAC_CIR0);
                if (cs->debug & L1_DEB_ISAC)
                        debugl1(cs, "ISAC CIR0 %02X", exval );
                if (exval & 2) {
                        cs->ph_state = (exval >> 2) & 0xf;
                        if (cs->debug & L1_DEB_ISAC)
                                debugl1(cs, "ph_state change %x", cs->ph_state);
                        isac_sched_event(cs, D_L1STATECHANGE);
                }
                if (exval & 1) {
                        exval = cs->readisac(cs, ISAC_CIR1);
                        if (cs->debug & L1_DEB_ISAC)
                                debugl1(cs, "ISAC CIR1 %02X", exval );
                }
        }
        if (val & 0x02) {       /* SIN */
                /* never */
                if (cs->debug & L1_DEB_WARN)
                        debugl1(cs, "ISAC SIN interrupt");
        }
        if (val & 0x01) {       /* EXI */
                exval = cs->readisac(cs, ISAC_EXIR);
                if (cs->debug & L1_DEB_WARN)
                        debugl1(cs, "ISAC EXIR %02x", exval);
                if (exval & 0x04) {
                        v1 = cs->readisac(cs, ISAC_MOSR);
                        if (cs->debug & L1_DEB_MONITOR)
                                debugl1(cs, "ISAC MOSR %02x", v1);
#if ARCOFI_USE
                        if (v1 & 0x08) {
                                if (!cs->mon_rx) {
                                        if (!(cs->mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) {
                                                if (cs->debug & L1_DEB_WARN)
                                                        debugl1(cs, "ISAC MON RX out of memory!");
                                                cs->mocr &= 0xf0;
                                                cs->mocr |= 0x0a;
                                                cs->writeisac(cs, ISAC_MOCR, cs->mocr);
                                                goto afterMONR0;
                                        } else
                                                cs->mon_rxp = 0;
                                }
                                if (cs->mon_rxp >= MAX_MON_FRAME) {
                                        cs->mocr &= 0xf0;
                                        cs->mocr |= 0x0a;
                                        cs->writeisac(cs, ISAC_MOCR, cs->mocr);
                                        cs->mon_rxp = 0;
                                        if (cs->debug & L1_DEB_WARN)
                                                debugl1(cs, "ISAC MON RX overflow!");
                                        goto afterMONR0;
                                }
                                cs->mon_rx[cs->mon_rxp++] = cs->readisac(cs, ISAC_MOR0);
                                if (cs->debug & L1_DEB_MONITOR)
                                        debugl1(cs, "ISAC MOR0 %02x", cs->mon_rx[cs->mon_rxp -1]);
                                if (cs->mon_rxp == 1) {
                                        cs->mocr |= 0x04;
                                        cs->writeisac(cs, ISAC_MOCR, cs->mocr);
                                }
                        }
                      afterMONR0:
                        if (v1 & 0x80) {
                                if (!cs->mon_rx) {
                                        if (!(cs->mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) {
                                                if (cs->debug & L1_DEB_WARN)
                                                        debugl1(cs, "ISAC MON RX out of memory!");
                                                cs->mocr &= 0x0f;
                                                cs->mocr |= 0xa0;
                                                cs->writeisac(cs, ISAC_MOCR, cs->mocr);
                                                goto afterMONR1;
                                        } else
                                                cs->mon_rxp = 0;
                                }
                                if (cs->mon_rxp >= MAX_MON_FRAME) {
                                        cs->mocr &= 0x0f;
                                        cs->mocr |= 0xa0;
                                        cs->writeisac(cs, ISAC_MOCR, cs->mocr);
                                        cs->mon_rxp = 0;
                                        if (cs->debug & L1_DEB_WARN)
                                                debugl1(cs, "ISAC MON RX overflow!");
                                        goto afterMONR1;
                                }
                                cs->mon_rx[cs->mon_rxp++] = cs->readisac(cs, ISAC_MOR1);
                                if (cs->debug & L1_DEB_MONITOR)
                                        debugl1(cs, "ISAC MOR1 %02x", cs->mon_rx[cs->mon_rxp -1]);
                                cs->mocr |= 0x40;
                                cs->writeisac(cs, ISAC_MOCR, cs->mocr);
                        }
                      afterMONR1:
                        if (v1 & 0x04) {
                                cs->mocr &= 0xf0;
                                cs->writeisac(cs, ISAC_MOCR, cs->mocr);
                                cs->mocr |= 0x0a;
                                cs->writeisac(cs, ISAC_MOCR, cs->mocr);
                                test_and_set_bit(HW_MON0_RX_END, &cs->HW_Flags);
                        }
                        if (v1 & 0x40) {
                                cs->mocr &= 0x0f;
                                cs->writeisac(cs, ISAC_MOCR, cs->mocr);
                                cs->mocr |= 0xa0;
                                cs->writeisac(cs, ISAC_MOCR, cs->mocr);
                                test_and_set_bit(HW_MON1_RX_END, &cs->HW_Flags);
                        }
                        if (v1 & 0x02) {
                                if ((!cs->mon_tx) || (cs->mon_txc &&
                                        (cs->mon_txp >= cs->mon_txc) &&
                                        !(v1 & 0x08))) {
                                        cs->mocr &= 0xf0;
                                        cs->writeisac(cs, ISAC_MOCR, cs->mocr);
                                        cs->mocr |= 0x0a;
                                        cs->writeisac(cs, ISAC_MOCR, cs->mocr);
                                        if (cs->mon_txc &&
                                                (cs->mon_txp >= cs->mon_txc))
                                                test_and_set_bit(HW_MON0_TX_END, &cs->HW_Flags);
                                        goto AfterMOX0;
                                }
                                if (cs->mon_txc && (cs->mon_txp >= cs->mon_txc)) {
                                        test_and_set_bit(HW_MON0_TX_END, &cs->HW_Flags);
                                        goto AfterMOX0;
                                }
                                cs->writeisac(cs, ISAC_MOX0,
                                        cs->mon_tx[cs->mon_txp++]);
                                if (cs->debug & L1_DEB_MONITOR)
                                        debugl1(cs, "ISAC %02x -> MOX0", cs->mon_tx[cs->mon_txp -1]);
                        }
                      AfterMOX0:
                        if (v1 & 0x20) {
                                if ((!cs->mon_tx) || (cs->mon_txc &&
                                        (cs->mon_txp >= cs->mon_txc) &&
                                        !(v1 & 0x80))) {
                                        cs->mocr &= 0x0f;
                                        cs->writeisac(cs, ISAC_MOCR, cs->mocr);
                                        cs->mocr |= 0xa0;
                                        cs->writeisac(cs, ISAC_MOCR, cs->mocr);
                                        if (cs->mon_txc &&
                                                (cs->mon_txp >= cs->mon_txc))
                                                test_and_set_bit(HW_MON1_TX_END, &cs->HW_Flags);
                                        goto AfterMOX1;
                                }
                                if (cs->mon_txc && (cs->mon_txp >= cs->mon_txc)) {
                                        test_and_set_bit(HW_MON1_TX_END, &cs->HW_Flags);
                                        goto AfterMOX1;
                                }
                                cs->writeisac(cs, ISAC_MOX1,
                                        cs->mon_tx[cs->mon_txp++]);
                                if (cs->debug & L1_DEB_MONITOR)
                                        debugl1(cs, "ISAC %02x -> MOX1", cs->mon_tx[cs->mon_txp -1]);
                        }
                      AfterMOX1:
#endif
                }
        }
}
 
static void
ISAC_l1hw(struct PStack *st, int pr, void *arg)
{
        struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
        struct sk_buff *skb = arg;
        int  val;
 
        switch (pr) {
                case (PH_DATA |REQUEST):
                        if (cs->debug & DEB_DLOG_HEX)
                                LogFrame(cs, skb->data, skb->len);
                        if (cs->debug & DEB_DLOG_VERBOSE)
                                dlogframe(cs, skb, 0);
                        if (cs->tx_skb) {
                                skb_queue_tail(&cs->sq, skb);
#ifdef L2FRAME_DEBUG            /* psa */
                                if (cs->debug & L1_DEB_LAPD)
                                        Logl2Frame(cs, skb, "PH_DATA Queued", 0);
#endif
                        } else {
                                cs->tx_skb = skb;
                                cs->tx_cnt = 0;
#ifdef L2FRAME_DEBUG            /* psa */
                                if (cs->debug & L1_DEB_LAPD)
                                        Logl2Frame(cs, skb, "PH_DATA", 0);
#endif
                                isac_fill_fifo(cs);
                        }
                        break;
                case (PH_PULL |INDICATION):
                        if (cs->tx_skb) {
                                if (cs->debug & L1_DEB_WARN)
                                        debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
                                skb_queue_tail(&cs->sq, skb);
                                break;
                        }
                        if (cs->debug & DEB_DLOG_HEX)
                                LogFrame(cs, skb->data, skb->len);
                        if (cs->debug & DEB_DLOG_VERBOSE)
                                dlogframe(cs, skb, 0);
                        cs->tx_skb = skb;
                        cs->tx_cnt = 0;
#ifdef L2FRAME_DEBUG            /* psa */
                        if (cs->debug & L1_DEB_LAPD)
                                Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
#endif
                        isac_fill_fifo(cs);
                        break;
                case (PH_PULL | REQUEST):
#ifdef L2FRAME_DEBUG            /* psa */
                        if (cs->debug & L1_DEB_LAPD)
                                debugl1(cs, "-> PH_REQUEST_PULL");
#endif
                        if (!cs->tx_skb) {
                                test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
                                st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
                        } else
                                test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
                        break;
                case (HW_RESET | REQUEST):
                        if ((cs->ph_state == ISAC_IND_EI) ||
                                (cs->ph_state == ISAC_IND_DR) ||
                                (cs->ph_state == ISAC_IND_RS))
                                ph_command(cs, ISAC_CMD_TIM);
                        else
                                ph_command(cs, ISAC_CMD_RS);
                        break;
                case (HW_ENABLE | REQUEST):
                        ph_command(cs, ISAC_CMD_TIM);
                        break;
                case (HW_INFO3 | REQUEST):
                        ph_command(cs, ISAC_CMD_AR8);
                        break;
                case (HW_TESTLOOP | REQUEST):
                        val = 0;
                        if (1 & (long) arg)
                                val |= 0x0c;
                        if (2 & (long) arg)
                                val |= 0x3;
                        if (test_bit(HW_IOM1, &cs->HW_Flags)) {
                                /* IOM 1 Mode */
                                if (!val) {
                                        cs->writeisac(cs, ISAC_SPCR, 0xa);
                                        cs->writeisac(cs, ISAC_ADF1, 0x2);
                                } else {
                                        cs->writeisac(cs, ISAC_SPCR, val);
                                        cs->writeisac(cs, ISAC_ADF1, 0xa);
                                }
                        } else {
                                /* IOM 2 Mode */
                                cs->writeisac(cs, ISAC_SPCR, val);
                                if (val)
                                        cs->writeisac(cs, ISAC_ADF1, 0x8);
                                else
                                        cs->writeisac(cs, ISAC_ADF1, 0x0);
                        }
                        break;
                case (HW_DEACTIVATE | RESPONSE):
                        discard_queue(&cs->rq);
                        discard_queue(&cs->sq);
                        if (cs->tx_skb) {
                                dev_kfree_skb(cs->tx_skb, FREE_WRITE);
                                cs->tx_skb = NULL;
                        }
                        if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
                                del_timer(&cs->dbusytimer);
                        if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
                                isac_sched_event(cs, D_CLEARBUSY);
                        break;
                default:
                        if (cs->debug & L1_DEB_WARN)
                                debugl1(cs, "isac_l1hw unknown %04x", pr);
                        break;
        }
}
 
void
setstack_isac(struct PStack *st, struct IsdnCardState *cs)
{
        st->l1.l1hw = ISAC_l1hw;
}
 
static void
dbusy_timer_handler(struct IsdnCardState *cs)
{
        struct PStack *stptr;
        int     val;
 
        if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
                if (cs->debug) {
                        debugl1(cs, "D-Channel Busy");
                        val = cs->readisac(cs, ISAC_RBCH);
                        if (val & ISAC_RBCH_XAC)
                                debugl1(cs, "ISAC XAC");
                        else
                                debugl1(cs, "ISAC No XAC");
                }
                test_and_set_bit(FLG_L1_DBUSY, &cs->HW_Flags);
                stptr = cs->stlist;
 
                while (stptr != NULL) {
                        stptr->l1.l1l2(stptr, PH_PAUSE | INDICATION, NULL);
                        stptr = stptr->next;
                }
        }
}
 
HISAX_INITFUNC(void
initisac(struct IsdnCardState *cs))
{
        cs->tqueue.routine = (void *) (void *) isac_bh;
        cs->setstack_d = setstack_isac;
        cs->dbusytimer.function = (void *) dbusy_timer_handler;
        cs->dbusytimer.data = (long) cs;
        init_timer(&cs->dbusytimer);
        cs->writeisac(cs, ISAC_MASK, 0xff);
        cs->mocr = 0xaa;
        if (test_bit(HW_IOM1, &cs->HW_Flags)) {
                /* IOM 1 Mode */
                cs->writeisac(cs, ISAC_ADF2, 0x0);
                cs->writeisac(cs, ISAC_SPCR, 0xa);
                cs->writeisac(cs, ISAC_ADF1, 0x2);
                cs->writeisac(cs, ISAC_STCR, 0x70);
                cs->writeisac(cs, ISAC_MODE, 0xc9);
        } else {
                /* IOM 2 Mode */
                cs->writeisac(cs, ISAC_ADF2, 0x80);
                cs->writeisac(cs, ISAC_SQXR, 0x2f);
                cs->writeisac(cs, ISAC_SPCR, 0x00);
                cs->writeisac(cs, ISAC_STCR, 0x70);
                cs->writeisac(cs, ISAC_MODE, 0xc9);
                cs->writeisac(cs, ISAC_TIMR, 0x00);
                cs->writeisac(cs, ISAC_ADF1, 0x00);
        }
        ph_command(cs, ISAC_CMD_RS);
        cs->writeisac(cs, ISAC_MASK, 0x0);
}
 
HISAX_INITFUNC(void
clear_pending_isac_ints(struct IsdnCardState *cs))
{
        int val, eval;
 
        val = cs->readisac(cs, ISAC_STAR);
        debugl1(cs, "ISAC STAR %x", val);
        val = cs->readisac(cs, ISAC_MODE);
        debugl1(cs, "ISAC MODE %x", val);
        val = cs->readisac(cs, ISAC_ADF2);
        debugl1(cs, "ISAC ADF2 %x", val);
        val = cs->readisac(cs, ISAC_ISTA);
        debugl1(cs, "ISAC ISTA %x", val);
        if (val & 0x01) {
                eval = cs->readisac(cs, ISAC_EXIR);
                debugl1(cs, "ISAC EXIR %x", eval);
        }
        val = cs->readisac(cs, ISAC_CIR0);
        debugl1(cs, "ISAC CIR0 %x", val);
        cs->ph_state = (val >> 2) & 0xf;
        isac_sched_event(cs, D_L1STATECHANGE);
        /* Disable all IRQ */
        cs->writeisac(cs, ISAC_MASK, 0xFF);
}

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[/] [or1k/] [trunk/] [uclinux/] [uClinux-2.0.x/] [drivers/] [isdn/] [hisax/] [isac.c] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	199	simons	`/* $Id: isac.c,v 1.1.1.1 2001-09-10 07:44:18 simons Exp $`
2
3			`* isac.c ISAC specific routines`
4			`*`
5			`* Author Karsten Keil (keil@isdn4linux.de)`
6			`*`
7			`* This file is (c) under GNU PUBLIC LICENSE`
8			`* For changes and modifications please read`
9			`* ../../../Documentation/isdn/HiSax.cert`
10			`*`
11			`* $Log: not supported by cvs2svn $`
12			`* Revision 1.1.1.1 2001/07/02 17:58:32 simons`
13			`* Initial revision`
14			`*`
15			`* Revision 1.7.2.9 1998/11/03 00:06:41 keil`
16			`* certification related changes`
17			`* fixed logging for smaller stack use`
18			`*`
19			`* Revision 1.7.2.8 1998/09/27 13:06:18 keil`
20			`* Apply most changes from 2.1.X (HiSax 3.1)`
21			`*`
22			`* Revision 1.7.2.7 1998/05/27 18:05:38 keil`
23			`* HiSax 3.0`
24			`*`
25			`* Revision 1.7.2.6 1998/04/08 21:57:31 keil`
26			`* New init code to fix problems during init if S0 is allready activ`
27			`*`
28			`* Revision 1.7.2.5 1998/03/07 23:15:24 tsbogend`
29			`* made HiSax working on Linux/Alpha`
30			`*`
31			`* Revision 1.7.2.4 1998/02/09 11:24:06 keil`
32			`* New leased line support (Read README.HiSax!)`
33			`*`
34			`* Revision 1.7.2.3 1998/01/11 22:58:55 keil`
35			`* new setstack interface`
36			`*`
37			`* Revision 1.7.2.2 1997/11/15 18:54:23 keil`
38			`* cosmetics`
39			`*`
40			`* Revision 1.7.2.1 1997/10/17 22:10:49 keil`
41			`* new files on 2.0`
42			`*`
43			`* Revision 1.6 1997/08/15 17:47:08 keil`
44			`* avoid oops because a uninitialised timer`
45			`*`
46			`* Revision 1.5 1997/08/07 17:48:49 keil`
47			`* fix wrong parenthesis`
48			`*`
49			`* Revision 1.4 1997/07/30 17:11:59 keil`
50			`* fixed Timer3`
51			`*`
52			`* Revision 1.3 1997/07/27 21:37:40 keil`
53			`* T3 implemented; supervisor l1timer; B-channel TEST_LOOP`
54			`*`
55			`* Revision 1.2 1997/06/26 11:16:15 keil`
56			`* first version`
57			`*`
58			`*`
59			`*/`
60
61			`#define __NO_VERSION__`
62			`#include "hisax.h"`
63			`#include "isac.h"`
64			`#include "isdnl1.h"`
65			`#include <linux/interrupt.h>`
66
67			`#define DBUSY_TIMER_VALUE 80`
68			`#define ARCOFI_USE 1`
69
70			`static char *ISACVer[] HISAX_INITDATA =`
71			`{"2086/2186 V1.1", "2085 B1", "2085 B2",`
72			`"2085 V2.3"};`
73
74			`void`
75			`ISACVersion(struct IsdnCardState cs, char s)`
76			`{`
77			`int val;`
78
79			`val = cs->readisac(cs, ISAC_RBCH);`
80			`printk(KERN_INFO "%s ISAC version (%x): %s\n", s, val, ISACVer[(val >> 5) & 3]);`
81			`}`
82
83			`static void`
84			`ph_command(struct IsdnCardState *cs, unsigned int command)`
85			`{`
86			`if (cs->debug & L1_DEB_ISAC)`
87			`debugl1(cs, "ph_command %x", command);`
88			`cs->writeisac(cs, ISAC_CIX0, (command << 2) \| 3);`
89			`}`
90
91
92			`static void`
93			`isac_new_ph(struct IsdnCardState *cs)`
94			`{`
95			`switch (cs->ph_state) {`
96			`case (ISAC_IND_RS):`
97			`case (ISAC_IND_EI):`
98			`ph_command(cs, ISAC_CMD_DUI);`
99			`l1_msg(cs, HW_RESET \| INDICATION, NULL);`
100			`break;`
101			`case (ISAC_IND_DID):`
102			`l1_msg(cs, HW_DEACTIVATE \| CONFIRM, NULL);`
103			`break;`
104			`case (ISAC_IND_DR):`
105			`l1_msg(cs, HW_DEACTIVATE \| INDICATION, NULL);`
106			`break;`
107			`case (ISAC_IND_PU):`
108			`l1_msg(cs, HW_POWERUP \| CONFIRM, NULL);`
109			`break;`
110			`case (ISAC_IND_RSY):`
111			`l1_msg(cs, HW_RSYNC \| INDICATION, NULL);`
112			`break;`
113			`case (ISAC_IND_ARD):`
114			`l1_msg(cs, HW_INFO2 \| INDICATION, NULL);`
115			`break;`
116			`case (ISAC_IND_AI8):`
117			`l1_msg(cs, HW_INFO4_P8 \| INDICATION, NULL);`
118			`break;`
119			`case (ISAC_IND_AI10):`
120			`l1_msg(cs, HW_INFO4_P10 \| INDICATION, NULL);`
121			`break;`
122			`default:`
123			`break;`
124			`}`
125			`}`
126
127			`static void`
128			`isac_bh(struct IsdnCardState *cs)`
129			`{`
130			`struct PStack *stptr;`
131
132			`if (!cs)`
133			`return;`
134			`if (test_and_clear_bit(D_CLEARBUSY, &cs->event)) {`
135			`if (cs->debug)`
136			`debugl1(cs, "D-Channel Busy cleared");`
137			`stptr = cs->stlist;`
138			`while (stptr != NULL) {`
139			`stptr->l1.l1l2(stptr, PH_PAUSE \| CONFIRM, NULL);`
140			`stptr = stptr->next;`
141			`}`
142			`}`
143			`if (test_and_clear_bit(D_L1STATECHANGE, &cs->event))`
144			`isac_new_ph(cs);`
145			`if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))`
146			`DChannel_proc_rcv(cs);`
147			`if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))`
148			`DChannel_proc_xmt(cs);`
149			`if (test_and_clear_bit(D_RX_MON0, &cs->event))`
150			`test_and_set_bit(HW_MON0_RX_END, &cs->HW_Flags);`
151			`if (test_and_clear_bit(D_RX_MON1, &cs->event))`
152			`test_and_set_bit(HW_MON1_RX_END, &cs->HW_Flags);`
153			`if (test_and_clear_bit(D_TX_MON0, &cs->event))`
154			`test_and_set_bit(HW_MON0_TX_END, &cs->HW_Flags);`
155			`if (test_and_clear_bit(D_TX_MON1, &cs->event))`
156			`test_and_set_bit(HW_MON1_TX_END, &cs->HW_Flags);`
157			`}`
158
159			`void`
160			`isac_empty_fifo(struct IsdnCardState *cs, int count)`
161			`{`
162			`u_char *ptr;`
163			`long flags;`
164
165			`if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))`
166			`debugl1(cs, "isac_empty_fifo");`
167
168			`if ((cs->rcvidx + count) >= MAX_DFRAME_LEN_L1) {`
169			`if (cs->debug & L1_DEB_WARN)`
170			`debugl1(cs, "isac_empty_fifo overrun %d",`
171			`cs->rcvidx + count);`
172			`cs->writeisac(cs, ISAC_CMDR, 0x80);`
173			`cs->rcvidx = 0;`
174			`return;`
175			`}`
176			`ptr = cs->rcvbuf + cs->rcvidx;`
177			`cs->rcvidx += count;`
178			`save_flags(flags);`
179			`cli();`
180			`cs->readisacfifo(cs, ptr, count);`
181			`cs->writeisac(cs, ISAC_CMDR, 0x80);`
182			`restore_flags(flags);`
183			`if (cs->debug & L1_DEB_ISAC_FIFO) {`
184			`char *t = cs->dlog;`
185
186			`t += sprintf(t, "isac_empty_fifo cnt %d", count);`
187			`QuickHex(t, ptr, count);`
188			`debugl1(cs, cs->dlog);`
189			`}`
190			`}`
191
192			`static void`
193			`isac_fill_fifo(struct IsdnCardState *cs)`
194			`{`
195			`int count, more;`
196			`u_char *ptr;`
197			`long flags;`
198
199			`if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))`
200			`debugl1(cs, "isac_fill_fifo");`
201
202			`if (!cs->tx_skb)`
203			`return;`
204
205			`count = cs->tx_skb->len;`
206			`if (count <= 0)`
207			`return;`
208
209			`more = 0;`
210			`if (count > 32) {`
211			`more = !0;`
212			`count = 32;`
213			`}`
214			`save_flags(flags);`
215			`cli();`
216			`ptr = cs->tx_skb->data;`
217			`skb_pull(cs->tx_skb, count);`
218			`cs->tx_cnt += count;`
219			`cs->writeisacfifo(cs, ptr, count);`
220			`cs->writeisac(cs, ISAC_CMDR, more ? 0x8 : 0xa);`
221			`restore_flags(flags);`
222			`if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {`
223			`debugl1(cs, "isac_fill_fifo dbusytimer running");`
224			`del_timer(&cs->dbusytimer);`
225			`}`
226			`init_timer(&cs->dbusytimer);`
227			`cs->dbusytimer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000);`
228			`add_timer(&cs->dbusytimer);`
229			`if (cs->debug & L1_DEB_ISAC_FIFO) {`
230			`char *t = cs->dlog;`
231
232			`t += sprintf(t, "isac_fill_fifo cnt %d", count);`
233			`QuickHex(t, ptr, count);`
234			`debugl1(cs, cs->dlog);`
235			`}`
236			`}`
237
238			`void`
239			`isac_sched_event(struct IsdnCardState *cs, int event)`
240			`{`
241			`test_and_set_bit(event, &cs->event);`
242			`queue_task(&cs->tqueue, &tq_immediate);`
243			`mark_bh(IMMEDIATE_BH);`
244			`}`
245
246			`void`
247			`isac_interrupt(struct IsdnCardState *cs, u_char val)`
248			`{`
249			`u_char exval, v1;`
250			`struct sk_buff *skb;`
251			`unsigned int count;`
252			`long flags;`
253
254			`if (cs->debug & L1_DEB_ISAC)`
255			`debugl1(cs, "ISAC interrupt %x", val);`
256			`if (val & 0x80) { /* RME */`
257			`exval = cs->readisac(cs, ISAC_RSTA);`
258			`if ((exval & 0x70) != 0x20) {`
259			`if (exval & 0x40)`
260			`if (cs->debug & L1_DEB_WARN)`
261			`debugl1(cs, "ISAC RDO");`
262			`if (!(exval & 0x20))`
263			`if (cs->debug & L1_DEB_WARN)`
264			`debugl1(cs, "ISAC CRC error");`
265			`cs->writeisac(cs, ISAC_CMDR, 0x80);`
266			`} else {`
267			`count = cs->readisac(cs, ISAC_RBCL) & 0x1f;`
268			`if (count == 0)`
269			`count = 32;`
270			`isac_empty_fifo(cs, count);`
271			`save_flags(flags);`
272			`cli();`
273			`if ((count = cs->rcvidx) > 0) {`
274			`cs->rcvidx = 0;`
275			`if (!(skb = alloc_skb(count, GFP_ATOMIC)))`
276			`printk(KERN_WARNING "HiSax: D receive out of memory\n");`
277			`else {`
278			`SET_SKB_FREE(skb);`
279			`memcpy(skb_put(skb, count), cs->rcvbuf, count);`
280			`skb_queue_tail(&cs->rq, skb);`
281			`}`
282			`}`
283			`restore_flags(flags);`
284			`}`
285			`cs->rcvidx = 0;`
286			`isac_sched_event(cs, D_RCVBUFREADY);`
287			`}`
288			`if (val & 0x40) { /* RPF */`
289			`isac_empty_fifo(cs, 32);`
290			`}`
291			`if (val & 0x20) { /* RSC */`
292			`/* never */`
293			`if (cs->debug & L1_DEB_WARN)`
294			`debugl1(cs, "ISAC RSC interrupt");`
295			`}`
296			`if (val & 0x10) { /* XPR */`
297			`if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))`
298			`del_timer(&cs->dbusytimer);`
299			`if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))`
300			`isac_sched_event(cs, D_CLEARBUSY);`
301			`if (cs->tx_skb) {`
302			`if (cs->tx_skb->len) {`
303			`isac_fill_fifo(cs);`
304			`goto afterXPR;`
305			`} else {`
306			`dev_kfree_skb(cs->tx_skb, FREE_WRITE);`
307			`cs->tx_cnt = 0;`
308			`cs->tx_skb = NULL;`
309			`}`
310			`}`
311			`if ((cs->tx_skb = skb_dequeue(&cs->sq))) {`
312			`cs->tx_cnt = 0;`
313			`isac_fill_fifo(cs);`
314			`} else`
315			`isac_sched_event(cs, D_XMTBUFREADY);`
316			`}`
317			`afterXPR:`
318			`if (val & 0x04) { /* CISQ */`
319			`exval = cs->readisac(cs, ISAC_CIR0);`
320			`if (cs->debug & L1_DEB_ISAC)`
321			`debugl1(cs, "ISAC CIR0 %02X", exval );`
322			`if (exval & 2) {`
323			`cs->ph_state = (exval >> 2) & 0xf;`
324			`if (cs->debug & L1_DEB_ISAC)`
325			`debugl1(cs, "ph_state change %x", cs->ph_state);`
326			`isac_sched_event(cs, D_L1STATECHANGE);`
327			`}`
328			`if (exval & 1) {`
329			`exval = cs->readisac(cs, ISAC_CIR1);`
330			`if (cs->debug & L1_DEB_ISAC)`
331			`debugl1(cs, "ISAC CIR1 %02X", exval );`
332			`}`
333			`}`
334			`if (val & 0x02) { /* SIN */`
335			`/* never */`
336			`if (cs->debug & L1_DEB_WARN)`
337			`debugl1(cs, "ISAC SIN interrupt");`
338			`}`
339			`if (val & 0x01) { /* EXI */`
340			`exval = cs->readisac(cs, ISAC_EXIR);`
341			`if (cs->debug & L1_DEB_WARN)`
342			`debugl1(cs, "ISAC EXIR %02x", exval);`
343			`if (exval & 0x04) {`
344			`v1 = cs->readisac(cs, ISAC_MOSR);`
345			`if (cs->debug & L1_DEB_MONITOR)`
346			`debugl1(cs, "ISAC MOSR %02x", v1);`
347			`#if ARCOFI_USE`
348			`if (v1 & 0x08) {`
349			`if (!cs->mon_rx) {`
350			`if (!(cs->mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) {`
351			`if (cs->debug & L1_DEB_WARN)`
352			`debugl1(cs, "ISAC MON RX out of memory!");`
353			`cs->mocr &= 0xf0;`
354			`cs->mocr \|= 0x0a;`
355			`cs->writeisac(cs, ISAC_MOCR, cs->mocr);`
356			`goto afterMONR0;`
357			`} else`
358			`cs->mon_rxp = 0;`
359			`}`
360			`if (cs->mon_rxp >= MAX_MON_FRAME) {`
361			`cs->mocr &= 0xf0;`
362			`cs->mocr \|= 0x0a;`
363			`cs->writeisac(cs, ISAC_MOCR, cs->mocr);`
364			`cs->mon_rxp = 0;`
365			`if (cs->debug & L1_DEB_WARN)`
366			`debugl1(cs, "ISAC MON RX overflow!");`
367			`goto afterMONR0;`
368			`}`
369			`cs->mon_rx[cs->mon_rxp++] = cs->readisac(cs, ISAC_MOR0);`
370			`if (cs->debug & L1_DEB_MONITOR)`
371			`debugl1(cs, "ISAC MOR0 %02x", cs->mon_rx[cs->mon_rxp -1]);`
372			`if (cs->mon_rxp == 1) {`
373			`cs->mocr \|= 0x04;`
374			`cs->writeisac(cs, ISAC_MOCR, cs->mocr);`
375			`}`
376			`}`
377			`afterMONR0:`
378			`if (v1 & 0x80) {`
379			`if (!cs->mon_rx) {`
380			`if (!(cs->mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) {`
381			`if (cs->debug & L1_DEB_WARN)`
382			`debugl1(cs, "ISAC MON RX out of memory!");`
383			`cs->mocr &= 0x0f;`
384			`cs->mocr \|= 0xa0;`
385			`cs->writeisac(cs, ISAC_MOCR, cs->mocr);`
386			`goto afterMONR1;`
387			`} else`
388			`cs->mon_rxp = 0;`
389			`}`
390			`if (cs->mon_rxp >= MAX_MON_FRAME) {`
391			`cs->mocr &= 0x0f;`
392			`cs->mocr \|= 0xa0;`
393			`cs->writeisac(cs, ISAC_MOCR, cs->mocr);`
394			`cs->mon_rxp = 0;`
395			`if (cs->debug & L1_DEB_WARN)`
396			`debugl1(cs, "ISAC MON RX overflow!");`
397			`goto afterMONR1;`
398			`}`
399			`cs->mon_rx[cs->mon_rxp++] = cs->readisac(cs, ISAC_MOR1);`
400			`if (cs->debug & L1_DEB_MONITOR)`
401			`debugl1(cs, "ISAC MOR1 %02x", cs->mon_rx[cs->mon_rxp -1]);`
402			`cs->mocr \|= 0x40;`
403			`cs->writeisac(cs, ISAC_MOCR, cs->mocr);`
404			`}`
405			`afterMONR1:`
406			`if (v1 & 0x04) {`
407			`cs->mocr &= 0xf0;`
408			`cs->writeisac(cs, ISAC_MOCR, cs->mocr);`
409			`cs->mocr \|= 0x0a;`
410			`cs->writeisac(cs, ISAC_MOCR, cs->mocr);`
411			`test_and_set_bit(HW_MON0_RX_END, &cs->HW_Flags);`
412			`}`
413			`if (v1 & 0x40) {`
414			`cs->mocr &= 0x0f;`
415			`cs->writeisac(cs, ISAC_MOCR, cs->mocr);`
416			`cs->mocr \|= 0xa0;`
417			`cs->writeisac(cs, ISAC_MOCR, cs->mocr);`
418			`test_and_set_bit(HW_MON1_RX_END, &cs->HW_Flags);`
419			`}`
420			`if (v1 & 0x02) {`
421			`if ((!cs->mon_tx) \|\| (cs->mon_txc &&`
422			`(cs->mon_txp >= cs->mon_txc) &&`
423			`!(v1 & 0x08))) {`
424			`cs->mocr &= 0xf0;`
425			`cs->writeisac(cs, ISAC_MOCR, cs->mocr);`
426			`cs->mocr \|= 0x0a;`
427			`cs->writeisac(cs, ISAC_MOCR, cs->mocr);`
428			`if (cs->mon_txc &&`
429			`(cs->mon_txp >= cs->mon_txc))`
430			`test_and_set_bit(HW_MON0_TX_END, &cs->HW_Flags);`
431			`goto AfterMOX0;`
432			`}`
433			`if (cs->mon_txc && (cs->mon_txp >= cs->mon_txc)) {`
434			`test_and_set_bit(HW_MON0_TX_END, &cs->HW_Flags);`
435			`goto AfterMOX0;`
436			`}`
437			`cs->writeisac(cs, ISAC_MOX0,`
438			`cs->mon_tx[cs->mon_txp++]);`
439			`if (cs->debug & L1_DEB_MONITOR)`
440			`debugl1(cs, "ISAC %02x -> MOX0", cs->mon_tx[cs->mon_txp -1]);`
441			`}`
442			`AfterMOX0:`
443			`if (v1 & 0x20) {`
444			`if ((!cs->mon_tx) \|\| (cs->mon_txc &&`
445			`(cs->mon_txp >= cs->mon_txc) &&`
446			`!(v1 & 0x80))) {`
447			`cs->mocr &= 0x0f;`
448			`cs->writeisac(cs, ISAC_MOCR, cs->mocr);`
449			`cs->mocr \|= 0xa0;`
450			`cs->writeisac(cs, ISAC_MOCR, cs->mocr);`
451			`if (cs->mon_txc &&`
452			`(cs->mon_txp >= cs->mon_txc))`
453			`test_and_set_bit(HW_MON1_TX_END, &cs->HW_Flags);`
454			`goto AfterMOX1;`
455			`}`
456			`if (cs->mon_txc && (cs->mon_txp >= cs->mon_txc)) {`
457			`test_and_set_bit(HW_MON1_TX_END, &cs->HW_Flags);`
458			`goto AfterMOX1;`
459			`}`
460			`cs->writeisac(cs, ISAC_MOX1,`
461			`cs->mon_tx[cs->mon_txp++]);`
462			`if (cs->debug & L1_DEB_MONITOR)`
463			`debugl1(cs, "ISAC %02x -> MOX1", cs->mon_tx[cs->mon_txp -1]);`
464			`}`
465			`AfterMOX1:`
466			`#endif`
467			`}`
468			`}`
469			`}`
470
471			`static void`
472			`ISAC_l1hw(struct PStack st, int pr, void arg)`
473			`{`
474			`struct IsdnCardState cs = (struct IsdnCardState ) st->l1.hardware;`
475			`struct sk_buff *skb = arg;`
476			`int val;`
477
478			`switch (pr) {`
479			`case (PH_DATA \|REQUEST):`
480			`if (cs->debug & DEB_DLOG_HEX)`
481			`LogFrame(cs, skb->data, skb->len);`
482			`if (cs->debug & DEB_DLOG_VERBOSE)`
483			`dlogframe(cs, skb, 0);`
484			`if (cs->tx_skb) {`
485			`skb_queue_tail(&cs->sq, skb);`
486			`#ifdef L2FRAME_DEBUG /* psa */`
487			`if (cs->debug & L1_DEB_LAPD)`
488			`Logl2Frame(cs, skb, "PH_DATA Queued", 0);`
489			`#endif`
490			`} else {`
491			`cs->tx_skb = skb;`
492			`cs->tx_cnt = 0;`
493			`#ifdef L2FRAME_DEBUG /* psa */`
494			`if (cs->debug & L1_DEB_LAPD)`
495			`Logl2Frame(cs, skb, "PH_DATA", 0);`
496			`#endif`
497			`isac_fill_fifo(cs);`
498			`}`
499			`break;`
500			`case (PH_PULL \|INDICATION):`
501			`if (cs->tx_skb) {`
502			`if (cs->debug & L1_DEB_WARN)`
503			`debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");`
504			`skb_queue_tail(&cs->sq, skb);`
505			`break;`
506			`}`
507			`if (cs->debug & DEB_DLOG_HEX)`
508			`LogFrame(cs, skb->data, skb->len);`
509			`if (cs->debug & DEB_DLOG_VERBOSE)`
510			`dlogframe(cs, skb, 0);`
511			`cs->tx_skb = skb;`
512			`cs->tx_cnt = 0;`
513			`#ifdef L2FRAME_DEBUG /* psa */`
514			`if (cs->debug & L1_DEB_LAPD)`
515			`Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);`
516			`#endif`
517			`isac_fill_fifo(cs);`
518			`break;`
519			`case (PH_PULL \| REQUEST):`
520			`#ifdef L2FRAME_DEBUG /* psa */`
521			`if (cs->debug & L1_DEB_LAPD)`
522			`debugl1(cs, "-> PH_REQUEST_PULL");`
523			`#endif`
524			`if (!cs->tx_skb) {`
525			`test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);`
526			`st->l1.l1l2(st, PH_PULL \| CONFIRM, NULL);`
527			`} else`
528			`test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);`
529			`break;`
530			`case (HW_RESET \| REQUEST):`
531			`if ((cs->ph_state == ISAC_IND_EI) \|\|`
532			`(cs->ph_state == ISAC_IND_DR) \|\|`
533			`(cs->ph_state == ISAC_IND_RS))`
534			`ph_command(cs, ISAC_CMD_TIM);`
535			`else`
536			`ph_command(cs, ISAC_CMD_RS);`
537			`break;`
538			`case (HW_ENABLE \| REQUEST):`
539			`ph_command(cs, ISAC_CMD_TIM);`
540			`break;`
541			`case (HW_INFO3 \| REQUEST):`
542			`ph_command(cs, ISAC_CMD_AR8);`
543			`break;`
544			`case (HW_TESTLOOP \| REQUEST):`
545			`val = 0;`
546			`if (1 & (long) arg)`
547			`val \|= 0x0c;`
548			`if (2 & (long) arg)`
549			`val \|= 0x3;`
550			`if (test_bit(HW_IOM1, &cs->HW_Flags)) {`
551			`/* IOM 1 Mode */`
552			`if (!val) {`
553			`cs->writeisac(cs, ISAC_SPCR, 0xa);`
554			`cs->writeisac(cs, ISAC_ADF1, 0x2);`
555			`} else {`
556			`cs->writeisac(cs, ISAC_SPCR, val);`
557			`cs->writeisac(cs, ISAC_ADF1, 0xa);`
558			`}`
559			`} else {`
560			`/* IOM 2 Mode */`
561			`cs->writeisac(cs, ISAC_SPCR, val);`
562			`if (val)`
563			`cs->writeisac(cs, ISAC_ADF1, 0x8);`
564			`else`
565			`cs->writeisac(cs, ISAC_ADF1, 0x0);`
566			`}`
567			`break;`
568			`case (HW_DEACTIVATE \| RESPONSE):`
569			`discard_queue(&cs->rq);`
570			`discard_queue(&cs->sq);`
571			`if (cs->tx_skb) {`
572			`dev_kfree_skb(cs->tx_skb, FREE_WRITE);`
573			`cs->tx_skb = NULL;`
574			`}`
575			`if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))`
576			`del_timer(&cs->dbusytimer);`
577			`if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))`
578			`isac_sched_event(cs, D_CLEARBUSY);`
579			`break;`
580			`default:`
581			`if (cs->debug & L1_DEB_WARN)`
582			`debugl1(cs, "isac_l1hw unknown %04x", pr);`
583			`break;`
584			`}`
585			`}`
586
587			`void`
588			`setstack_isac(struct PStack st, struct IsdnCardState cs)`
589			`{`
590			`st->l1.l1hw = ISAC_l1hw;`
591			`}`
592
593			`static void`
594			`dbusy_timer_handler(struct IsdnCardState *cs)`
595			`{`
596			`struct PStack *stptr;`
597			`int val;`
598
599			`if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {`
600			`if (cs->debug) {`
601			`debugl1(cs, "D-Channel Busy");`
602			`val = cs->readisac(cs, ISAC_RBCH);`
603			`if (val & ISAC_RBCH_XAC)`
604			`debugl1(cs, "ISAC XAC");`
605			`else`
606			`debugl1(cs, "ISAC No XAC");`
607			`}`
608			`test_and_set_bit(FLG_L1_DBUSY, &cs->HW_Flags);`
609			`stptr = cs->stlist;`
610
611			`while (stptr != NULL) {`
612			`stptr->l1.l1l2(stptr, PH_PAUSE \| INDICATION, NULL);`
613			`stptr = stptr->next;`
614			`}`
615			`}`
616			`}`
617
618			`HISAX_INITFUNC(void`
619			`initisac(struct IsdnCardState *cs))`
620			`{`
621			`cs->tqueue.routine = (void ) (void ) isac_bh;`
622			`cs->setstack_d = setstack_isac;`
623			`cs->dbusytimer.function = (void *) dbusy_timer_handler;`
624			`cs->dbusytimer.data = (long) cs;`
625			`init_timer(&cs->dbusytimer);`
626			`cs->writeisac(cs, ISAC_MASK, 0xff);`
627			`cs->mocr = 0xaa;`
628			`if (test_bit(HW_IOM1, &cs->HW_Flags)) {`
629			`/* IOM 1 Mode */`
630			`cs->writeisac(cs, ISAC_ADF2, 0x0);`
631			`cs->writeisac(cs, ISAC_SPCR, 0xa);`
632			`cs->writeisac(cs, ISAC_ADF1, 0x2);`
633			`cs->writeisac(cs, ISAC_STCR, 0x70);`
634			`cs->writeisac(cs, ISAC_MODE, 0xc9);`
635			`} else {`
636			`/* IOM 2 Mode */`
637			`cs->writeisac(cs, ISAC_ADF2, 0x80);`
638			`cs->writeisac(cs, ISAC_SQXR, 0x2f);`
639			`cs->writeisac(cs, ISAC_SPCR, 0x00);`
640			`cs->writeisac(cs, ISAC_STCR, 0x70);`
641			`cs->writeisac(cs, ISAC_MODE, 0xc9);`
642			`cs->writeisac(cs, ISAC_TIMR, 0x00);`
643			`cs->writeisac(cs, ISAC_ADF1, 0x00);`
644			`}`
645			`ph_command(cs, ISAC_CMD_RS);`
646			`cs->writeisac(cs, ISAC_MASK, 0x0);`
647			`}`
648
649			`HISAX_INITFUNC(void`
650			`clear_pending_isac_ints(struct IsdnCardState *cs))`
651			`{`
652			`int val, eval;`
653
654			`val = cs->readisac(cs, ISAC_STAR);`
655			`debugl1(cs, "ISAC STAR %x", val);`
656			`val = cs->readisac(cs, ISAC_MODE);`
657			`debugl1(cs, "ISAC MODE %x", val);`
658			`val = cs->readisac(cs, ISAC_ADF2);`
659			`debugl1(cs, "ISAC ADF2 %x", val);`
660			`val = cs->readisac(cs, ISAC_ISTA);`
661			`debugl1(cs, "ISAC ISTA %x", val);`
662			`if (val & 0x01) {`
663			`eval = cs->readisac(cs, ISAC_EXIR);`
664			`debugl1(cs, "ISAC EXIR %x", eval);`
665			`}`
666			`val = cs->readisac(cs, ISAC_CIR0);`
667			`debugl1(cs, "ISAC CIR0 %x", val);`
668			`cs->ph_state = (val >> 2) & 0xf;`
669			`isac_sched_event(cs, D_L1STATECHANGE);`
670			`/* Disable all IRQ */`
671			`cs->writeisac(cs, ISAC_MASK, 0xFF);`
672			`}`