OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [uclinux/] [uClinux-2.0.x/] [drivers/] [net/] [8390.h] - Blame information for rev 1765

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 199 simons
/* Generic NS8390 register definitions. */
2
/* This file is part of Donald Becker's 8390 drivers, and is distributed
3
   under the same license.
4
   Some of these names and comments originated from the Crynwr
5
   packet drivers, which are distributed under the GPL. */
6
 
7
#ifndef _8390_h
8
#define _8390_h
9
 
10
#include <linux/if_ether.h>
11
#include <linux/ioport.h>
12
#include <linux/skbuff.h>
13
 
14
#define TX_2X_PAGES 12
15
#define TX_1X_PAGES 6
16
 
17
/* Should always use two Tx slots to get back-to-back transmits. */
18
#define EI_PINGPONG
19
 
20
#ifdef EI_PINGPONG
21
#define TX_PAGES TX_2X_PAGES
22
#else
23
#define TX_PAGES TX_1X_PAGES
24
#endif
25
 
26
#define ETHER_ADDR_LEN 6
27
 
28
/* The 8390 specific per-packet-header format. */
29
struct e8390_pkt_hdr {
30
  unsigned char status; /* status */
31
  unsigned char next;   /* pointer to next packet. */
32
  unsigned short count; /* header + packet length in bytes */
33
};
34
 
35
/* From 8390.c */
36
extern int ei_debug;
37
extern struct sigaction ei_sigaction;
38
 
39
extern int ethif_init(struct device *dev);
40
extern int ethdev_init(struct device *dev);
41
extern void NS8390_init(struct device *dev, int startp);
42
extern int ei_open(struct device *dev);
43
extern int ei_close(struct device *dev);
44
extern void ei_interrupt(int irq, void *dev_id, struct pt_regs *regs);
45
 
46
#ifndef HAVE_AUTOIRQ
47
/* From auto_irq.c */
48
extern struct device *irq2dev_map[16];
49
extern int autoirq_setup(int waittime);
50
extern int autoirq_report(int waittime);
51
#endif
52
 
53
/* Most of these entries should be in 'struct device' (or most of the
54
   things in there should be here!) */
55
/* You have one of these per-board */
56
struct ei_device {
57
  const char *name;
58
  void (*reset_8390)(struct device *);
59
  void (*get_8390_hdr)(struct device *, struct e8390_pkt_hdr *, int);
60
  void (*block_output)(struct device *, int, const unsigned char *, int);
61
  void (*block_input)(struct device *, int, struct sk_buff *, int);
62
  unsigned open:1;
63
  unsigned word16:1;  /* We have the 16-bit (vs 8-bit) version of the card. */
64
  unsigned txing:1;             /* Transmit Active */
65
  unsigned irqlock:1;           /* 8390's intrs disabled when '1'. */
66
  unsigned dmaing:1;            /* Remote DMA Active */
67
  unsigned char tx_start_page, rx_start_page, stop_page;
68
  unsigned char current_page;   /* Read pointer in buffer  */
69
  unsigned char interface_num;  /* Net port (AUI, 10bT.) to use. */
70
  unsigned char txqueue;        /* Tx Packet buffer queue length. */
71
  short tx1, tx2;               /* Packet lengths for ping-pong tx. */
72
  short lasttx;                 /* Alpha version consistency check. */
73
  unsigned char reg0;           /* Register '0' in a WD8013 */
74
  unsigned char reg5;           /* Register '5' in a WD8013 */
75
  unsigned char saved_irq;      /* Original dev->irq value. */
76
  /* The new statistics table. */
77
  struct enet_statistics stat;
78
};
79
 
80
/* The maximum number of 8390 interrupt service routines called per IRQ. */
81
#define MAX_SERVICE 12
82
 
83
/* The maximum time waited (in jiffies) before assuming a Tx failed. (20ms) */
84
#define TX_TIMEOUT (20*HZ/100)
85
 
86
#define ei_status (*(struct ei_device *)(dev->priv))
87
 
88
/* Some generic ethernet register configurations. */
89
#define E8390_TX_IRQ_MASK 0xa   /* For register EN0_ISR */
90
#define E8390_RX_IRQ_MASK  0x5
91
#define E8390_RXCONFIG 0x4      /* EN0_RXCR: broadcasts, no multicast,errors */
92
#define E8390_RXOFF 0x20        /* EN0_RXCR: Accept no packets */
93
#define E8390_TXCONFIG 0x00     /* EN0_TXCR: Normal transmit mode */
94
#define E8390_TXOFF 0x02        /* EN0_TXCR: Transmitter off */
95
 
96
/*  Register accessed at EN_CMD, the 8390 base addr.  */
97
#define E8390_STOP      0x01    /* Stop and reset the chip */
98
#define E8390_START     0x02    /* Start the chip, clear reset */
99
#define E8390_TRANS     0x04    /* Transmit a frame */
100
#define E8390_RREAD     0x08    /* Remote read */
101
#define E8390_RWRITE    0x10    /* Remote write  */
102
#define E8390_NODMA     0x20    /* Remote DMA */
103
#define E8390_PAGE0     0x00    /* Select page chip registers */
104
#define E8390_PAGE1     0x40    /* using the two high-order bits */
105
#define E8390_PAGE2     0x80    /* Page 3 is invalid. */
106
 
107
#define E8390_CMD       0x00    /* The command register (for all pages) */
108
/* Page 0 register offsets. */
109
#define EN0_CLDALO      0x01    /* Low byte of current local dma addr  RD */
110
#define EN0_STARTPG     0x01    /* Starting page of ring bfr WR */
111
#define EN0_CLDAHI      0x02    /* High byte of current local dma addr  RD */
112
#define EN0_STOPPG      0x02    /* Ending page +1 of ring bfr WR */
113
#define EN0_BOUNDARY    0x03    /* Boundary page of ring bfr RD WR */
114
#define EN0_TSR         0x04    /* Transmit status reg RD */
115
#define EN0_TPSR        0x04    /* Transmit starting page WR */
116
#define EN0_NCR         0x05    /* Number of collision reg RD */
117
#define EN0_TCNTLO      0x05    /* Low  byte of tx byte count WR */
118
#define EN0_FIFO        0x06    /* FIFO RD */
119
#define EN0_TCNTHI      0x06    /* High byte of tx byte count WR */
120
#define EN0_ISR         0x07    /* Interrupt status reg RD WR */
121
#define EN0_CRDALO      0x08    /* low byte of current remote dma address RD */
122
#define EN0_RSARLO      0x08    /* Remote start address reg 0 */
123
#define EN0_CRDAHI      0x09    /* high byte, current remote dma address RD */
124
#define EN0_RSARHI      0x09    /* Remote start address reg 1 */
125
#define EN0_RCNTLO      0x0a    /* Remote byte count reg WR */
126
#define EN0_RCNTHI      0x0b    /* Remote byte count reg WR */
127
#define EN0_RSR         0x0c    /* rx status reg RD */
128
#define EN0_RXCR        0x0c    /* RX configuration reg WR */
129
#define EN0_TXCR        0x0d    /* TX configuration reg WR */
130
#define EN0_COUNTER0    0x0d    /* Rcv alignment error counter RD */
131
#define EN0_DCFG        0x0e    /* Data configuration reg WR */
132
#define EN0_COUNTER1    0x0e    /* Rcv CRC error counter RD */
133
#define EN0_IMR         0x0f    /* Interrupt mask reg WR */
134
#define EN0_COUNTER2    0x0f    /* Rcv missed frame error counter RD */
135
 
136
/* Bits in EN0_ISR - Interrupt status register */
137
#define ENISR_RX        0x01    /* Receiver, no error */
138
#define ENISR_TX        0x02    /* Transmitter, no error */
139
#define ENISR_RX_ERR    0x04    /* Receiver, with error */
140
#define ENISR_TX_ERR    0x08    /* Transmitter, with error */
141
#define ENISR_OVER      0x10    /* Receiver overwrote the ring */
142
#define ENISR_COUNTERS  0x20    /* Counters need emptying */
143
#define ENISR_RDC       0x40    /* remote dma complete */
144
#define ENISR_RESET     0x80    /* Reset completed */
145
#define ENISR_ALL       0x3f    /* Interrupts we will enable */
146
 
147
/* Bits in EN0_DCFG - Data config register */
148
#define ENDCFG_WTS      0x01    /* word transfer mode selection */
149
 
150
/* Page 1 register offsets. */
151
#define EN1_PHYS   0x01 /* This board's physical enet addr RD WR */
152
#define EN1_CURPAG 0x07 /* Current memory page RD WR */
153
#define EN1_MULT   0x08 /* Multicast filter mask array (8 bytes) RD WR */
154
 
155
/* Bits in received packet status byte and EN0_RSR*/
156
#define ENRSR_RXOK      0x01    /* Received a good packet */
157
#define ENRSR_CRC       0x02    /* CRC error */
158
#define ENRSR_FAE       0x04    /* frame alignment error */
159
#define ENRSR_FO        0x08    /* FIFO overrun */
160
#define ENRSR_MPA       0x10    /* missed pkt */
161
#define ENRSR_PHY       0x20    /* physical/multicase address */
162
#define ENRSR_DIS       0x40    /* receiver disable. set in monitor mode */
163
#define ENRSR_DEF       0x80    /* deferring */
164
 
165
/* Transmitted packet status, EN0_TSR. */
166
#define ENTSR_PTX 0x01  /* Packet transmitted without error */
167
#define ENTSR_ND  0x02  /* The transmit wasn't deferred. */
168
#define ENTSR_COL 0x04  /* The transmit collided at least once. */
169
#define ENTSR_ABT 0x08  /* The transmit collided 16 times, and was deferred. */
170
#define ENTSR_CRS 0x10  /* The carrier sense was lost. */
171
#define ENTSR_FU  0x20  /* A "FIFO underrun" occurred during transmit. */
172
#define ENTSR_CDH 0x40  /* The collision detect "heartbeat" signal was lost. */
173
#define ENTSR_OWC 0x80  /* There was an out-of-window collision. */
174
 
175
#endif /* _8390_h */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.