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[/] [or1k/] [trunk/] [uclinux/] [uClinux-2.0.x/] [drivers/] [net/] [a2065.h] - Blame information for rev 1765

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Line No. Rev Author Line
1 199 simons
/*
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 * Amiga Linux/68k A2065 Ethernet Driver
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 *
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 * (C) Copyright 1995 by Geert Uytterhoeven
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 *                      (Geert.Uytterhoeven@cs.kuleuven.ac.be)
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 *
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 * ---------------------------------------------------------------------------
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 *
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 * This program is based on
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 *
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 *      ariadne.?:      Amiga Linux/68k Ariadne Ethernet Driver
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 *                      (C) Copyright 1995 by Geert Uytterhoeven,
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 *                      Peter De Schrijver
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 *
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 *      lance.c:        An AMD LANCE ethernet driver for linux.
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 *                      Written 1993-94 by Donald Becker.
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 *
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 *      Am79C960:       PCnet(tm)-ISA Single-Chip Ethernet Controller
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 *                      Advanced Micro Devices
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 *                      Publication #16907, Rev. B, Amendment/0, May 1994
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 *
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 * ---------------------------------------------------------------------------
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 *
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 * This file is subject to the terms and conditions of the GNU General Public
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 * License.  See the file COPYING in the main directory of the Linux
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 * distribution for more details.
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 *
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 * ---------------------------------------------------------------------------
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 *
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 * The A2065 is a Zorro-II board made by Commodore/Ameristar. It contains:
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 *
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 *      - an Am7990 Local Area Network Controller for Ethernet (LANCE) with
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 *        both 10BASE-2 (thin coax) and AUI (DB-15) connectors
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 */
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/*
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 *              Am7990 Local Area Network Controller for Ethernet (LANCE)
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 */
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struct Am7990 {
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        volatile u_short RDP;           /* Register Data Port */
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        volatile u_short RAP;           /* Register Address Port */
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};
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/*
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 *              Am7990 Control and Status Registers
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 */
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#define CSR0            0x0000          /* LANCE Controller Status */
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#define CSR1            0x0001          /* IADR[15:0] */
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#define CSR2            0x0002          /* IADR[23:16] */
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#define CSR3            0x0003          /* Misc */
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/*
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 *              Bit definitions for CSR0 (LANCE Controller Status)
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 */
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#define ERR             0x8000          /* Error */
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#define BABL            0x4000          /* Babble: Transmitted too many bits */
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#define CERR            0x2000          /* No Heartbeat (10BASE-T) */
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#define MISS            0x1000          /* Missed Frame */
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#define MERR            0x0800          /* Memory Error */
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#define RINT            0x0400          /* Receive Interrupt */
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#define TINT            0x0200          /* Transmit Interrupt */
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#define IDON            0x0100          /* Initialization Done */
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#define INTR            0x0080          /* Interrupt Flag */
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#define INEA            0x0040          /* Interrupt Enable */
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#define RXON            0x0020          /* Receive On */
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#define TXON            0x0010          /* Transmit On */
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#define TDMD            0x0008          /* Transmit Demand */
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#define STOP            0x0004          /* Stop */
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#define STRT            0x0002          /* Start */
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#define INIT            0x0001          /* Initialize */
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/*
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 *              Bit definitions for CSR3
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 */
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#define BSWP            0x0004          /* Byte Swap
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                                           (on for big endian byte order) */
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#define ACON            0x0002          /* ALE Control
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                                           (on for active low ALE) */
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#define BCON            0x0001          /* Byte Control */
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/*
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 *              Initialization Block
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 */
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struct InitBlock {
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        u_short Mode;                   /* Mode */
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        u_char PADR[6];                 /* Physical Address */
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        u_long LADRF[2];                /* Logical Address Filter */
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        u_short RDRA;                   /* Receive Descriptor Ring Address */
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        u_short RLEN;                   /* Receive Descriptor Ring Length */
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        u_short TDRA;                   /* Transmit Descriptor Ring Address */
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        u_short TLEN;                   /* Transmit Descriptor Ring Length */
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};
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/*
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 *              Mode Flags
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 */
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#define PROM            0x8000          /* Promiscuous Mode */
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#define INTL            0x0040          /* Internal Loopback */
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#define DRTY            0x0020          /* Disable Retry */
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#define FCOLL           0x0010          /* Force Collision */
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#define DXMTFCS         0x0008          /* Disable Transmit CRC */
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#define LOOP            0x0004          /* Loopback Enable */
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#define DTX             0x0002          /* Disable Transmitter */
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#define DRX             0x0001          /* Disable Receiver */
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/*
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 *              Receive Descriptor Ring Entry
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 */
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struct RDRE {
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        volatile u_short RMD0;          /* LADR[15:0] */
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        volatile u_short RMD1;          /* HADR[23:16] | Receive Flags */
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        volatile u_short RMD2;          /* Buffer Byte Count
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                                           (two's complement) */
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        volatile u_short RMD3;          /* Message Byte Count */
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};
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/*
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 *              Transmit Descriptor Ring Entry
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 */
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struct TDRE {
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        volatile u_short TMD0;          /* LADR[15:0] */
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        volatile u_short TMD1;          /* HADR[23:16] | Transmit Flags */
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        volatile u_short TMD2;          /* Buffer Byte Count
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                                           (two's complement) */
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        volatile u_short TMD3;          /* Error Flags */
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};
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/*
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 *              Receive Flags
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 */
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#define RF_OWN          0x8000          /* LANCE owns the descriptor */
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#define RF_ERR          0x4000          /* Error */
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#define RF_FRAM         0x2000          /* Framing Error */
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#define RF_OFLO         0x1000          /* Overflow Error */
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#define RF_CRC          0x0800          /* CRC Error */
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#define RF_BUFF         0x0400          /* Buffer Error */
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#define RF_STP          0x0200          /* Start of Packet */
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#define RF_ENP          0x0100          /* End of Packet */
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/*
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 *              Transmit Flags
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 */
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#define TF_OWN          0x8000          /* LANCE owns the descriptor */
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#define TF_ERR          0x4000          /* Error */
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#define TF_RES          0x2000          /* Reserved,
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                                           LANCE writes this with a zero */
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#define TF_MORE         0x1000          /* More than one retry needed */
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#define TF_ONE          0x0800          /* One retry needed */
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#define TF_DEF          0x0400          /* Deferred */
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#define TF_STP          0x0200          /* Start of Packet */
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#define TF_ENP          0x0100          /* End of Packet */
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/*
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 *              Error Flags
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 */
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#define EF_BUFF         0x8000          /* Buffer Error */
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#define EF_UFLO         0x4000          /* Underflow Error */
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#define EF_LCOL         0x1000          /* Late Collision */
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#define EF_LCAR         0x0800          /* Loss of Carrier */
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#define EF_RTRY         0x0400          /* Retry Error */
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#define EF_TDR          0x003f          /* Time Domain Reflectometry */
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/*
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 *              A2065 Expansion Board Structure
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 */
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struct A2065Board {
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        u_char Pad1[0x4000];
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        struct Am7990 Lance;
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        u_char Pad2[0x3ffc];
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        volatile u_char RAM[0x8000];
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};

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