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/* lance.c: An AMD LANCE/PCnet ethernet driver for Linux. */

/*

        Written/copyright 1993-1998 by Donald Becker.

        Copyright 1993 United States Government as represented by the

        Director, National Security Agency.

        This software may be used and distributed according to the terms

        of the GNU Public License, incorporated herein by reference.

        This driver is for the Allied Telesis AT1500 and HP J2405A, and should work

        with most other LANCE-based bus-master (NE2100/NE2500) ethercards.

        The author may be reached as becker@CESDIS.gsfc.nasa.gov, or C/O

        Center of Excellence in Space Data and Information Sciences

           Code 930.5, Goddard Space Flight Center, Greenbelt MD 20771

        Fixing alignment problem with 1.3.* kernel and some minor changes

        by Andrey V. Savochkin, 1996.

        Problems or questions may be send to Donald Becker (see above) or to

        Andrey Savochkin -- saw@shade.msu.ru or

                Laboratory of Computation Methods,

                Department of Mathematics and Mechanics,

                Moscow State University,

                Leninskye Gory, Moscow 119899

        But I should to inform you that I'm not an expert in the LANCE card

        and it may occurs that you will receive no answer on your mail

        to Donald Becker. I didn't receive any answer on all my letters

        to him. Who knows why... But may be you are more lucky?  ;->

                                                          SAW

        Thomas Bogendoerfer (tsbogend@bigbug.franken.de):

        - added support for Linux/Alpha, but removed most of it, because

        it worked only for the PCI chip.

      - added hook for the 32bit lance driver

      - added PCnetPCI II (79C970A) to chip table

        Paul Gortmaker (gpg109@rsphy1.anu.edu.au):

        - hopefully fix above so Linux/Alpha can use ISA cards too.

    8/20/96 Fixed 7990 autoIRQ failure and reversed unneeded alignment -djb

    v1.12 10/27/97 Module support -djb

    v1.14  2/3/98 Module support modified, made PCI support optional -djb

*/

static const char *version = "lance.c:v1.14 2/3/1998 dplatt@3do.com, becker@cesdis.gsfc.nasa.gov\n";

#ifdef MODULE

#ifdef MODVERSIONS

#include <linux/modversions.h>

#endif

#include <linux/module.h>

#include <linux/version.h>

#else

#define MOD_INC_USE_COUNT

#define MOD_DEC_USE_COUNT

#endif

#include <linux/config.h>

#include <linux/kernel.h>

#include <linux/sched.h>

#include <linux/string.h>

#include <linux/ptrace.h>

#include <linux/errno.h>

#include <linux/ioport.h>

#include <linux/malloc.h>

#include <linux/interrupt.h>

#include <linux/pci.h>

#include <linux/bios32.h>

#include <asm/bitops.h>

#include <asm/io.h>

#include <asm/dma.h>

#include <linux/netdevice.h>

#include <linux/etherdevice.h>

#include <linux/skbuff.h>

static unsigned int lance_portlist[] = { 0x300, 0x320, 0x340, 0x360, 0};

int lance_probe(struct device *dev);

int lance_probe1(struct device *dev, int ioaddr, int irq, int options);

#ifdef HAVE_DEVLIST

struct netdev_entry lance_drv =

{"lance", lance_probe1, LANCE_TOTAL_SIZE, lance_portlist};

#endif

#ifdef LANCE_DEBUG

int lance_debug = LANCE_DEBUG;

#else

int lance_debug = 1;

#endif

/*

                                Theory of Operation

I. Board Compatibility

This device driver is designed for the AMD 79C960, the "PCnet-ISA

single-chip ethernet controller for ISA".  This chip is used in a wide

variety of boards from vendors such as Allied Telesis, HP, Kingston,

and Boca.  This driver is also intended to work with older AMD 7990

designs, such as the NE1500 and NE2100, and newer 79C961.  For convenience,

I use the name LANCE to refer to all of the AMD chips, even though it properly

refers only to the original 7990.

II. Board-specific settings

The driver is designed to work the boards that use the faster

bus-master mode, rather than in shared memory mode.      (Only older designs

have on-board buffer memory needed to support the slower shared memory mode.)

Most ISA boards have jumpered settings for the I/O base, IRQ line, and DMA

channel.  This driver probes the likely base addresses:

{0x300, 0x320, 0x340, 0x360}.

After the board is found it generates a DMA-timeout interrupt and uses

autoIRQ to find the IRQ line.  The DMA channel can be set with the low bits

of the otherwise-unused dev->mem_start value (aka PARAM1).  If unset it is

probed for by enabling each free DMA channel in turn and checking if

initialization succeeds.

The HP-J2405A board is an exception: with this board it is easy to read the

EEPROM-set values for the base, IRQ, and DMA.  (Of course you must already

_know_ the base address -- that field is for writing the EEPROM.)

III. Driver operation

IIIa. Ring buffers

The LANCE uses ring buffers of Tx and Rx descriptors.  Each entry describes

the base and length of the data buffer, along with status bits.  The length

of these buffers is set by LANCE_LOG_{RX,TX}_BUFFERS, which is log_2() of

the buffer length (rather than being directly the buffer length) for

implementation ease.  The current values are 2 (Tx) and 4 (Rx), which leads to

ring sizes of 4 (Tx) and 16 (Rx).  Increasing the number of ring entries

needlessly uses extra space and reduces the chance that an upper layer will

be able to reorder queued Tx packets based on priority.  Decreasing the number

of entries makes it more difficult to achieve back-to-back packet transmission

and increases the chance that Rx ring will overflow.  (Consider the worst case

of receiving back-to-back minimum-sized packets.)

The LANCE has the capability to "chain" both Rx and Tx buffers, but this driver

statically allocates full-sized (slightly oversized -- PKT_BUF_SZ) buffers to

avoid the administrative overhead. For the Rx side this avoids dynamically

allocating full-sized buffers "just in case", at the expense of a

memory-to-memory data copy for each packet received.  For most systems this

is a good tradeoff: the Rx buffer will always be in low memory, the copy

is inexpensive, and it primes the cache for later packet processing.  For Tx

the buffers are only used when needed as low-memory bounce buffers.

IIIB. 16M memory limitations.

For the ISA bus master mode all structures used directly by the LANCE,

the initialization block, Rx and Tx rings, and data buffers, must be

accessible from the ISA bus, i.e. in the lower 16M of real memory.

This is a problem for current Linux kernels on >16M machines. The network

devices are initialized after memory initialization, and the kernel doles out

memory from the top of memory downward.  The current solution is to have a

special network initialization routine that's called before memory

initialization; this will eventually be generalized for all network devices.

As mentioned before, low-memory "bounce-buffers" are used when needed.

IIIC. Synchronization

The driver runs as two independent, single-threaded flows of control.  One

is the send-packet routine, which enforces single-threaded use by the

dev->tbusy flag.  The other thread is the interrupt handler, which is single

threaded by the hardware and other software.

The send packet thread has partial control over the Tx ring and 'dev->tbusy'

flag.  It sets the tbusy flag whenever it's queuing a Tx packet. If the next

queue slot is empty, it clears the tbusy flag when finished otherwise it sets

the 'lp->tx_full' flag.

The interrupt handler has exclusive control over the Rx ring and records stats

from the Tx ring.  (The Tx-done interrupt can't be selectively turned off, so

we can't avoid the interrupt overhead by having the Tx routine reap the Tx

stats.)  After reaping the stats, it marks the queue entry as empty by setting

the 'base' to zero.      Iff the 'lp->tx_full' flag is set, it clears both the

tx_full and tbusy flags.

*/

/* Set the number of Tx and Rx buffers, using Log_2(# buffers).

   Reasonable default values are 16 Tx buffers, and 16 Rx buffers.

   That translates to 4 and 4 (16 == 2^^4).

   This is a compile-time option for efficiency.

   */

#ifndef LANCE_LOG_TX_BUFFERS

#define LANCE_LOG_TX_BUFFERS 4

#define LANCE_LOG_RX_BUFFERS 4

#endif

#define TX_RING_SIZE                    (1 << (LANCE_LOG_TX_BUFFERS))

#define TX_RING_MOD_MASK                (TX_RING_SIZE - 1)

#define TX_RING_LEN_BITS                ((LANCE_LOG_TX_BUFFERS) << 29)

#define RX_RING_SIZE                    (1 << (LANCE_LOG_RX_BUFFERS))

#define RX_RING_MOD_MASK                (RX_RING_SIZE - 1)

#define RX_RING_LEN_BITS                ((LANCE_LOG_RX_BUFFERS) << 29)

#define PKT_BUF_SZ              1544

/* Offsets from base I/O address. */

#define LANCE_DATA 0x10

#define LANCE_ADDR 0x12

#define LANCE_RESET 0x14

#define LANCE_BUS_IF 0x16

#define LANCE_TOTAL_SIZE 0x18

/* The LANCE Rx and Tx ring descriptors. */

struct lance_rx_head {

        s32 base;

        s16 buf_length;                 /* This length is 2s complement (negative)! */

        s16 msg_length;                 /* This length is "normal". */

};

struct lance_tx_head {

        s32 base;

        s16 length;                             /* Length is 2s complement (negative)! */

        s16 misc;

};

/* The LANCE initialization block, described in databook. */

struct lance_init_block {

        u16 mode;               /* Pre-set mode (reg. 15) */

        u8  phys_addr[6]; /* Physical ethernet address */

        u32 filter[2];                  /* Multicast filter (unused). */

        /* Receive and transmit ring base, along with extra bits. */

        u32  rx_ring;                   /* Tx and Rx ring base pointers */

        u32  tx_ring;

};

struct lance_private {

        /* The Tx and Rx ring entries must be aligned on 8-byte boundaries. */

        struct lance_rx_head rx_ring[RX_RING_SIZE];

        struct lance_tx_head tx_ring[TX_RING_SIZE];

        struct lance_init_block init_block;

        const char *name;

        /* The saved address of a sent-in-place packet/buffer, for skfree(). */

        struct sk_buff* tx_skbuff[TX_RING_SIZE];

        /* The addresses of receive-in-place skbuffs. */

        struct sk_buff* rx_skbuff[RX_RING_SIZE];

        unsigned long rx_buffs;         /* Address of Rx and Tx buffers. */

        /* Tx low-memory "bounce buffer" address. */

        char (*tx_bounce_buffs)[PKT_BUF_SZ];

        int cur_rx, cur_tx;                     /* The next free ring entry */

        int dirty_rx, dirty_tx;         /* The ring entries to be free()ed. */

        int dma;

        struct enet_statistics stats;

        unsigned char chip_version;     /* See lance_chip_type. */

        char tx_full;

        unsigned long lock;

};

#define LANCE_MUST_PAD          0x00000001

#define LANCE_ENABLE_AUTOSELECT 0x00000002

#define LANCE_MUST_REINIT_RING  0x00000004

#define LANCE_MUST_UNRESET      0x00000008

#define LANCE_HAS_MISSED_FRAME  0x00000010

/* A mapping from the chip ID number to the part number and features.

   These are from the datasheets -- in real life the '970 version

   reportedly has the same ID as the '965. */

static struct lance_chip_type {

        int id_number;

        const char *name;

        int flags;

} chip_table[] = {

        {0x0000, "LANCE 7990",                          /* Ancient lance chip.  */

                LANCE_MUST_PAD + LANCE_MUST_UNRESET},

        {0x0003, "PCnet/ISA 79C960",            /* 79C960 PCnet/ISA.  */

                LANCE_ENABLE_AUTOSELECT + LANCE_MUST_REINIT_RING +

                        LANCE_HAS_MISSED_FRAME},

        {0x2260, "PCnet/ISA+ 79C961",           /* 79C961 PCnet/ISA+, Plug-n-Play.  */

                LANCE_ENABLE_AUTOSELECT + LANCE_MUST_REINIT_RING +

                        LANCE_HAS_MISSED_FRAME},

        {0x2420, "PCnet/PCI 79C970",            /* 79C970 or 79C974 PCnet-SCSI, PCI. */

                LANCE_ENABLE_AUTOSELECT + LANCE_MUST_REINIT_RING +

                        LANCE_HAS_MISSED_FRAME},

        /* Bug: the PCnet/PCI actually uses the PCnet/VLB ID number, so just call

                it the PCnet32. */

        {0x2430, "PCnet32",                                     /* 79C965 PCnet for VL bus. */

                LANCE_ENABLE_AUTOSELECT + LANCE_MUST_REINIT_RING +

                        LANCE_HAS_MISSED_FRAME},

        {0x2621, "PCnet/PCI-II 79C970A",        /* 79C970A PCInetPCI II. */

                LANCE_ENABLE_AUTOSELECT + LANCE_MUST_REINIT_RING +

                        LANCE_HAS_MISSED_FRAME},

        {0x0,    "PCnet (unknown)",

                LANCE_ENABLE_AUTOSELECT + LANCE_MUST_REINIT_RING +

                        LANCE_HAS_MISSED_FRAME},

};

enum {OLD_LANCE = 0, PCNET_ISA=1, PCNET_ISAP=2, PCNET_PCI=3, PCNET_VLB=4, PCNET_PCI_II=5, LANCE_UNKNOWN=6};

/* Non-zero only if the current card is a PCI with BIOS-set IRQ. */

static unsigned char pci_irq_line = 0;

/* Non-zero if lance_probe1() needs to allocate low-memory bounce buffers.

   Assume yes until we know the memory size. */

static unsigned char lance_need_isa_bounce_buffers = 1;

static int lance_open(struct device *dev);

static int lance_open_fail(struct device *dev);

static void lance_init_ring(struct device *dev, int mode);

static int lance_start_xmit(struct sk_buff *skb, struct device *dev);

static int lance_rx(struct device *dev);

static void lance_interrupt(int irq, void *dev_id, struct pt_regs *regs);

static int lance_close(struct device *dev);

static struct enet_statistics *lance_get_stats(struct device *dev);

static void set_multicast_list(struct device *dev);

#ifdef MODULE

#define MAX_CARDS               8       /* Max number of interfaces (cards) per module */

#define IF_NAMELEN              8       /* # of chars for storing dev->name */

static int io[MAX_CARDS] = { 0, };

static int dma[MAX_CARDS] = { 0, };

static int irq[MAX_CARDS]  = { 0, };

static char ifnames[MAX_CARDS][IF_NAMELEN] = { {0, }, };

static struct device dev_lance[MAX_CARDS] =

{{

    0, /* device name is inserted by linux/drivers/net/net_init.c */

        0, 0, 0, 0,

        0, 0,

        0, 0, 0, NULL, NULL}};

int init_module(void)

{

        int this_dev, found = 0;

        for (this_dev = 0; this_dev < MAX_CARDS; this_dev++) {

                struct device *dev = &dev_lance[this_dev];

                dev->name = ifnames[this_dev];

                dev->irq = irq[this_dev];

                dev->base_addr = io[this_dev];

                dev->dma = dma[this_dev];

                dev->init = lance_probe;

#if NO_AUTOPROBE_MODULE

                if (io[this_dev] == 0)  {

                        if (this_dev != 0) break; /* only complain once */

                        printk(KERN_NOTICE "lance.c: Module autoprobing not allowed. Append \"io=0xNNN\" value(s).\n");

                        return -EPERM;

                }

#endif

                if (register_netdev(dev) != 0) {

                        if (found != 0)

                                return 0;        /* Got at least one. */

                        printk(KERN_WARNING "lance.c: No PCnet/LANCE card found\n");

                        return -ENXIO;

                }

                found++;

        }

        return 0;

}

void cleanup_module(void)

{

        int this_dev;

        for (this_dev = 0; this_dev < MAX_CARDS; this_dev++) {

                struct device *dev = &dev_lance[this_dev];

                if (dev->priv != NULL) {

                        kfree(dev->priv);

                        dev->priv = NULL;

                        free_dma(dev->dma);

                        release_region(dev->base_addr, LANCE_TOTAL_SIZE);

                        unregister_netdev(dev);

                }

        }

}

#endif /* MODULE */

/* Starting in v2.1.*, the LANCE/PCnet probe is now similar to the other

   board probes now that kmalloc() can allocate ISA DMA-able regions.

   This also allows the LANCE driver to be used as a module.

   */

int lance_probe(struct device *dev)

{

        int *port, result;

        if (high_memory <= 16*1024*1024)

                lance_need_isa_bounce_buffers = 0;

#if defined(CONFIG_PCI)

    if (pcibios_present()) {

            int pci_index;

                if (lance_debug > 1)

                        printk("lance.c: PCI bios is present, checking for devices...\n");

                for (pci_index = 0; pci_index < 8; pci_index++) {

                        unsigned char pci_bus, pci_device_fn;

                        unsigned int pci_ioaddr;

                        unsigned short pci_command;

                        if (pcibios_find_device (PCI_VENDOR_ID_AMD,

                                                 PCI_DEVICE_ID_AMD_LANCE, pci_index,

                                                 &pci_bus, &pci_device_fn) != 0)

                                break;

                        pcibios_read_config_byte(pci_bus, pci_device_fn,

                                                 PCI_INTERRUPT_LINE, &pci_irq_line);

                        pcibios_read_config_dword(pci_bus, pci_device_fn,

                                                  PCI_BASE_ADDRESS_0, &pci_ioaddr);

                        /* Remove I/O space marker in bit 0. */

                        pci_ioaddr &= ~3;

                        /* Avoid already found cards from previous calls

                         */

                        if (check_region(pci_ioaddr, LANCE_TOTAL_SIZE))

                                continue;

                        /* PCI Spec 2.1 states that it is either the driver or PCI card's

                         * responsibility to set the PCI Master Enable Bit if needed.

                         *      (From Mark Stockton <marks@schooner.sys.hou.compaq.com>)

                         */

                        pcibios_read_config_word(pci_bus, pci_device_fn,

                                                                         PCI_COMMAND, &pci_command);

                        if ( ! (pci_command & PCI_COMMAND_MASTER)) {

                                printk("PCI Master Bit has not been set. Setting...\n");

                                pci_command |= PCI_COMMAND_MASTER;

                                pcibios_write_config_word(pci_bus, pci_device_fn,

                                                                                  PCI_COMMAND, pci_command);

                        }

                        printk("Found PCnet/PCI at %#x, irq %d.\n",

                                   pci_ioaddr, pci_irq_line);

                        result = lance_probe1(dev, pci_ioaddr, pci_irq_line, 0);

                        pci_irq_line = 0;

                        if (!result) return 0;

                }

        }

#endif  /* defined(CONFIG_PCI) */

        for (port = lance_portlist; *port; port++) {

                int ioaddr = *port;

                if ( check_region(ioaddr, LANCE_TOTAL_SIZE) == 0) {

                        /* Detect "normal" 0x57 0x57 and the NI6510EB 0x52 0x44

                           signatures w/ minimal I/O reads */

                        char offset15, offset14 = inb(ioaddr + 14);

                        if ((offset14 == 0x52 || offset14 == 0x57) &&

                                ((offset15 = inb(ioaddr + 15)) == 0x57 || offset15 == 0x44)) {

                                result = lance_probe1(dev, ioaddr, 0, 0);

                                if ( !result ) return 0;

                        }

                }

        }

        return -ENODEV;

}

int lance_probe1(struct device *dev, int ioaddr, int irq, int options)

{

        struct lance_private *lp;

        short dma_channels;                                     /* Mark spuriously-busy DMA channels */

        int i, reset_val, lance_version;

        const char *chipname;

        /* Flags for specific chips or boards. */

        unsigned char hpJ2405A = 0;                      /* HP ISA adaptor */

        int hp_builtin = 0;                                      /* HP on-board ethernet. */

        static int did_version = 0;                      /* Already printed version info. */

        /* First we look for special cases.

           Check for HP's on-board ethernet by looking for 'HP' in the BIOS.

           There are two HP versions, check the BIOS for the configuration port.

           This method provided by L. Julliard, Laurent_Julliard@grenoble.hp.com.

           */

        if (readw(0x000f0102) == 0x5048)  {

                static const short ioaddr_table[] = { 0x300, 0x320, 0x340, 0x360};

                int hp_port = (readl(0x000f00f1) & 1)  ? 0x499 : 0x99;

                /* We can have boards other than the built-in!  Verify this is on-board. */

                if ((inb(hp_port) & 0xc0) == 0x80

                        && ioaddr_table[inb(hp_port) & 3] == ioaddr)

                        hp_builtin = hp_port;

        }

        /* We also recognize the HP Vectra on-board here, but check below. */

        hpJ2405A = (inb(ioaddr) == 0x08 && inb(ioaddr+1) == 0x00

                                && inb(ioaddr+2) == 0x09);

        /* Reset the LANCE.      */

        reset_val = inw(ioaddr+LANCE_RESET); /* Reset the LANCE */

        /* The Un-Reset needed is only needed for the real NE2100, and will

           confuse the HP board. */

        if (!hpJ2405A)

                outw(reset_val, ioaddr+LANCE_RESET);

        outw(0x0000, ioaddr+LANCE_ADDR); /* Switch to window 0 */

        if (inw(ioaddr+LANCE_DATA) != 0x0004)

                return -ENODEV;

        /* Get the version of the chip. */

        outw(88, ioaddr+LANCE_ADDR);

        if (inw(ioaddr+LANCE_ADDR) != 88) {

                lance_version = 0;

        } else {                                                        /* Good, it's a newer chip. */

                int chip_version = inw(ioaddr+LANCE_DATA);

                outw(89, ioaddr+LANCE_ADDR);

                chip_version |= inw(ioaddr+LANCE_DATA) << 16;

                if (lance_debug > 2)

                        printk("  LANCE chip version is %#x.\n", chip_version);

                if ((chip_version & 0xfff) != 0x003)

                        return -ENODEV;

                chip_version = (chip_version >> 12) & 0xffff;

                for (lance_version = 1; chip_table[lance_version].id_number; lance_version++) {

                        if (chip_table[lance_version].id_number == chip_version)

                                break;

                }

        }

        /* We can't use init_etherdev() to allocate dev->priv because it must

           a ISA DMA-able region. */

        dev = init_etherdev(dev, 0);

        dev->open = lance_open_fail;

        chipname = chip_table[lance_version].name;

        printk("%s: %s at %#3x,", dev->name, chipname, ioaddr);

        /* There is a 16 byte station address PROM at the base address.

           The first six bytes are the station address. */

        for (i = 0; i < 6; i++)

                printk(" %2.2x", dev->dev_addr[i] = inb(ioaddr + i));

        dev->base_addr = ioaddr;

        request_region(ioaddr, LANCE_TOTAL_SIZE, chip_table[lance_version].name);

        /* Make certain the data structures used by the LANCE are aligned and DMAble. */

        lp = (struct lance_private *)(((unsigned long)kmalloc(sizeof(*lp)+7,

                                                                                   GFP_DMA | GFP_KERNEL)+7) & ~7);

        if (lance_debug > 6) printk(" (#0x%05lx)", (unsigned long)lp);

        memset(lp, 0, sizeof(*lp));

        dev->priv = lp;

        lp->name = chipname;

        lp->rx_buffs = (unsigned long)kmalloc(PKT_BUF_SZ*RX_RING_SIZE,

                                                                                  GFP_DMA | GFP_KERNEL);

        if (lance_need_isa_bounce_buffers)

                lp->tx_bounce_buffs = kmalloc(PKT_BUF_SZ*TX_RING_SIZE,

                                                                          GFP_DMA | GFP_KERNEL);

        else

                lp->tx_bounce_buffs = NULL;

        lp->chip_version = lance_version;

        lp->init_block.mode = 0x0003;           /* Disable Rx and Tx. */

        for (i = 0; i < 6; i++)

                lp->init_block.phys_addr[i] = dev->dev_addr[i];

        lp->init_block.filter[0] = 0x00000000;

        lp->init_block.filter[1] = 0x00000000;

        lp->init_block.rx_ring = ((u32)virt_to_bus(lp->rx_ring) & 0xffffff) | RX_RING_LEN_BITS;

        lp->init_block.tx_ring = ((u32)virt_to_bus(lp->tx_ring) & 0xffffff) | TX_RING_LEN_BITS;

        outw(0x0001, ioaddr+LANCE_ADDR);

        inw(ioaddr+LANCE_ADDR);

        outw((short) (u32) virt_to_bus(&lp->init_block), ioaddr+LANCE_DATA);

        outw(0x0002, ioaddr+LANCE_ADDR);

        inw(ioaddr+LANCE_ADDR);

        outw(((u32)virt_to_bus(&lp->init_block)) >> 16, ioaddr+LANCE_DATA);

        outw(0x0000, ioaddr+LANCE_ADDR);

        inw(ioaddr+LANCE_ADDR);

        if (irq) {                                      /* Set iff PCI card. */

                dev->dma = 4;                   /* Native bus-master, no DMA channel needed. */

                dev->irq = irq;

        } else if (hp_builtin) {

                static const char dma_tbl[4] = {3, 5, 6, 0};

                static const char irq_tbl[4] = {3, 4, 5, 9};

                unsigned char port_val = inb(hp_builtin);

                dev->dma = dma_tbl[(port_val >> 4) & 3];

                dev->irq = irq_tbl[(port_val >> 2) & 3];

                printk(" HP Vectra IRQ %d DMA %d.\n", dev->irq, dev->dma);

        } else if (hpJ2405A) {

                static const char dma_tbl[4] = {3, 5, 6, 7};

                static const char irq_tbl[8] = {3, 4, 5, 9, 10, 11, 12, 15};

                short reset_val = inw(ioaddr+LANCE_RESET);

                dev->dma = dma_tbl[(reset_val >> 2) & 3];

                dev->irq = irq_tbl[(reset_val >> 4) & 7];

                printk(" HP J2405A IRQ %d DMA %d.\n", dev->irq, dev->dma);

        } else if (lance_version == PCNET_ISAP) {               /* The plug-n-play version. */

                short bus_info;

                outw(8, ioaddr+LANCE_ADDR);

                bus_info = inw(ioaddr+LANCE_BUS_IF);

                dev->dma = bus_info & 0x07;

                dev->irq = (bus_info >> 4) & 0x0F;

        } else {

                /* The DMA channel may be passed in PARAM1. */

                if (dev->mem_start & 0x07)

                        dev->dma = dev->mem_start & 0x07;

        }

        if (dev->dma == 0) {

                /* Read the DMA channel status register, so that we can avoid

                   stuck DMA channels in the DMA detection below. */

                dma_channels = ((inb(DMA1_STAT_REG) >> 4) & 0x0f) |

                        (inb(DMA2_STAT_REG) & 0xf0);

        }

        if (dev->irq >= 2)

                printk(" assigned IRQ %d", dev->irq);

        else if (lance_version != 0)  {  /* 7990 boards need DMA detection first. */

                /* To auto-IRQ we enable the initialization-done and DMA error

                   interrupts. For ISA boards we get a DMA error, but VLB and PCI

                   boards will work. */

                autoirq_setup(0);

                /* Trigger an initialization just for the interrupt. */

                outw(0x0041, ioaddr+LANCE_DATA);

                dev->irq = autoirq_report(2);

                if (dev->irq)

                        printk(", probed IRQ %d", dev->irq);

                else {

                        printk(", failed to detect IRQ line.\n");

                        return -ENODEV;

                }

                /* Check for the initialization done bit, 0x0100, which means

                   that we don't need a DMA channel. */

                if (inw(ioaddr+LANCE_DATA) & 0x0100)

                        dev->dma = 4;

        }

        if (dev->dma == 4) {

                printk(", no DMA needed.\n");

        } else if (dev->dma) {

                if (request_dma(dev->dma, chipname)) {

                        printk("DMA %d allocation failed.\n", dev->dma);

                        return -ENODEV;

                } else

                        printk(", assigned DMA %d.\n", dev->dma);

        } else {                        /* OK, we have to auto-DMA. */

                for (i = 0; i < 4; i++) {

                        static const char dmas[] = { 5, 6, 7, 3 };

                        int dma = dmas[i];

                        int boguscnt;

                        /* Don't enable a permanently busy DMA channel, or the machine

                           will hang. */

                        if (test_bit(dma, &dma_channels))

                                continue;

                        outw(0x7f04, ioaddr+LANCE_DATA); /* Clear the memory error bits. */

                        if (request_dma(dma, chipname))

                                continue;

                        set_dma_mode(dma, DMA_MODE_CASCADE);

                        enable_dma(dma);

                        /* Trigger an initialization. */

                        outw(0x0001, ioaddr+LANCE_DATA);

                        for (boguscnt = 100; boguscnt > 0; --boguscnt)

                                if (inw(ioaddr+LANCE_DATA) & 0x0900)

                                        break;

                        if (inw(ioaddr+LANCE_DATA) & 0x0100) {

                                dev->dma = dma;

                                printk(", DMA %d.\n", dev->dma);

                                break;

                        } else {

                                disable_dma(dma);

                                free_dma(dma);

                        }

                }

                if (i == 4) {                   /* Failure: bail. */

                        printk("DMA detection failed.\n");

                        return -ENODEV;