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#ifndef __ALPHA_CIA__H__
#define __ALPHA_CIA__H__
 
#include <linux/config.h>
#include <linux/types.h>
 
/*
 * CIA is the internal name for the 2117x chipset which provides
 * memory controller and PCI access for the 21164 chip based systems.
 *
 * This file is based on:
 *
 * DECchip 21171 Core Logic Chipset
 * Technical Reference Manual
 *
 * EC-QE18B-TE
 *
 * david.rusling@reo.mts.dec.com Initial Version.
 *
 */
 
/*------------------------------------------------------------------------**
**                                                                        **
**  EB164 I/O procedures                                                   **
**                                                                        **
**      inport[b|w|t|l], outport[b|w|t|l] 8:16:24:32 IO xfers             **
**      inportbxt: 8 bits only                                            **
**      inport:    alias of inportw                                       **
**      outport:   alias of outportw                                      **
**                                                                        **
**      inmem[b|w|t|l], outmem[b|w|t|l] 8:16:24:32 ISA memory xfers       **
**      inmembxt: 8 bits only                                             **
**      inmem:    alias of inmemw                                         **
**      outmem:   alias of outmemw                                        **
**                                                                        **
**------------------------------------------------------------------------*/
 
 
/* CIA ADDRESS BIT DEFINITIONS
 *
 *  3 3 3 3|3 3 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
 *  9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 * |1| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |0|0|0|
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 *  |                                                                        \_/ \_/
 *  |                                                                         |   |
 *  +-- IO space, not cached.                                   Byte Enable --+   |
 *                                                              Transfer Length --+
 *
 *
 *
 *   Byte      Transfer
 *   Enable    Length    Transfer  Byte    Address
 *   adr<6:5>  adr<4:3>  Length    Enable  Adder
 *   ---------------------------------------------
 *      00        00      Byte      1110   0x000
 *      01        00      Byte      1101   0x020
 *      10        00      Byte      1011   0x040
 *      11        00      Byte      0111   0x060
 *
 *      00        01      Word      1100   0x008
 *      01        01      Word      1001   0x028 <= Not supported in this code.
 *      10        01      Word      0011   0x048
 *
 *      00        10      Tribyte   1000   0x010
 *      01        10      Tribyte   0001   0x030
 *
 *      10        11      Longword  0000   0x058
 *
 *      Note that byte enables are asserted low.
 *
 */
 
#define BYTE_ENABLE_SHIFT 5
#define TRANSFER_LENGTH_SHIFT 3
 
#define MEM_R1_MASK 0x1fffffff  /* SPARSE Mem region 1 mask is 29 bits */
#define MEM_R2_MASK 0x07ffffff  /* SPARSE Mem region 2 mask is 27 bits */
#define MEM_R3_MASK 0x03ffffff  /* SPARSE Mem region 3 mask is 26 bits */
 
#ifdef CONFIG_ALPHA_SRM_SETUP
/* if we are using the SRM PCI setup, we'll need to use variables instead */
#define CIA_DMA_WIN_BASE_DEFAULT    (1024*1024*1024)
#define CIA_DMA_WIN_SIZE_DEFAULT    (1024*1024*1024)
 
extern unsigned int CIA_DMA_WIN_BASE;
extern unsigned int CIA_DMA_WIN_SIZE;
 
#else /* SRM_SETUP */
#define CIA_DMA_WIN_BASE            (1024*1024*1024)
#define CIA_DMA_WIN_SIZE        (1024*1024*1024)
#endif /* SRM_SETUP */
 
/*
 * 21171-CA Control and Status Registers (p4-1)
 */
#define CIA_IOC_CIA_REV               (IDENT_ADDR + 0x8740000080UL)
#define CIA_IOC_PCI_LAT               (IDENT_ADDR + 0x87400000C0UL)
#define CIA_IOC_CIA_CTRL              (IDENT_ADDR + 0x8740000100UL)
#define CIA_IOC_CIA_CNFG              (IDENT_ADDR + 0x8740000140UL)
#define CIA_IOC_HAE_MEM               (IDENT_ADDR + 0x8740000400UL)
#define CIA_IOC_HAE_IO                (IDENT_ADDR + 0x8740000440UL)
#define CIA_IOC_CFG                   (IDENT_ADDR + 0x8740000480UL)
#define CIA_IOC_CACK_EN               (IDENT_ADDR + 0x8740000600UL)
 
/*
 * 21171-CA Diagnostic Registers (p4-2)
 */
#define CIA_IOC_CIA_DIAG              (IDENT_ADDR + 0x8740002000UL)
#define CIA_IOC_DIAG_CHECK            (IDENT_ADDR + 0x8740003000UL)
 
/*
 * 21171-CA Performance Monitor registers (p4-3)
 */
#define CIA_IOC_PERF_MONITOR          (IDENT_ADDR + 0x8740004000UL)
#define CIA_IOC_PERF_CONTROL          (IDENT_ADDR + 0x8740004040UL)
 
/*
 * 21171-CA Error registers (p4-3)
 */
#define CIA_IOC_CPU_ERR0              (IDENT_ADDR + 0x8740008000UL)
#define CIA_IOC_CPU_ERR1              (IDENT_ADDR + 0x8740008040UL)
#define CIA_IOC_CIA_ERR               (IDENT_ADDR + 0x8740008200UL)
#define CIA_IOC_CIA_STAT              (IDENT_ADDR + 0x8740008240UL)
#define CIA_IOC_ERR_MASK              (IDENT_ADDR + 0x8740008280UL)
#define CIA_IOC_CIA_SYN               (IDENT_ADDR + 0x8740008300UL)
#define CIA_IOC_MEM_ERR0              (IDENT_ADDR + 0x8740008400UL)
#define CIA_IOC_MEM_ERR1              (IDENT_ADDR + 0x8740008440UL)
#define CIA_IOC_PCI_ERR0              (IDENT_ADDR + 0x8740008800UL)
#define CIA_IOC_PCI_ERR1              (IDENT_ADDR + 0x8740008840UL)
#define CIA_IOC_PCI_ERR3              (IDENT_ADDR + 0x8740008880UL)
 
/*
 * 2117A-CA PCI Address Translation Registers.
 */
#define CIA_IOC_PCI_TBIA              (IDENT_ADDR + 0x8760000100UL)
 
#define CIA_IOC_PCI_W0_BASE           (IDENT_ADDR + 0x8760000400UL)
#define CIA_IOC_PCI_W0_MASK           (IDENT_ADDR + 0x8760000440UL)
#define CIA_IOC_PCI_T0_BASE           (IDENT_ADDR + 0x8760000480UL)
 
#define CIA_IOC_PCI_W1_BASE           (IDENT_ADDR + 0x8760000500UL)
#define CIA_IOC_PCI_W1_MASK           (IDENT_ADDR + 0x8760000540UL)
#define CIA_IOC_PCI_T1_BASE           (IDENT_ADDR + 0x8760000580UL)
 
#define CIA_IOC_PCI_W2_BASE           (IDENT_ADDR + 0x8760000600UL)
#define CIA_IOC_PCI_W2_MASK           (IDENT_ADDR + 0x8760000640UL)
#define CIA_IOC_PCI_T2_BASE           (IDENT_ADDR + 0x8760000680UL)
 
#define CIA_IOC_PCI_W3_BASE           (IDENT_ADDR + 0x8760000700UL)
#define CIA_IOC_PCI_W3_MASK           (IDENT_ADDR + 0x8760000740UL)
#define CIA_IOC_PCI_T3_BASE           (IDENT_ADDR + 0x8760000780UL)
 
/*
 * 21171-CA System configuration registers (p4-3)
 */
#define CIA_IOC_MCR                   (IDENT_ADDR + 0x8750000000UL)
#define CIA_IOC_MBA0                  (IDENT_ADDR + 0x8750000600UL)
#define CIA_IOC_MBA2                  (IDENT_ADDR + 0x8750000680UL)
#define CIA_IOC_MBA4                  (IDENT_ADDR + 0x8750000700UL)
#define CIA_IOC_MBA6                  (IDENT_ADDR + 0x8750000780UL)
#define CIA_IOC_MBA8                  (IDENT_ADDR + 0x8750000800UL)
#define CIA_IOC_MBAA                  (IDENT_ADDR + 0x8750000880UL)
#define CIA_IOC_MBAC                  (IDENT_ADDR + 0x8750000900UL)
#define CIA_IOC_MBAE                  (IDENT_ADDR + 0x8750000980UL)
#define CIA_IOC_TMG0                  (IDENT_ADDR + 0x8750000B00UL)
#define CIA_IOC_TMG1                  (IDENT_ADDR + 0x8750000B40UL)
#define CIA_IOC_TMG2                  (IDENT_ADDR + 0x8750000B80UL)
 
/*
 * Memory spaces:
 */
#define CIA_IACK_SC                     (IDENT_ADDR + 0x8720000000UL)
#define CIA_CONF                        (IDENT_ADDR + 0x8700000000UL)
#define CIA_IO                          (IDENT_ADDR + 0x8580000000UL)
#define CIA_SPARSE_MEM                  (IDENT_ADDR + 0x8000000000UL)
#define CIA_SPARSE_MEM_R2               (IDENT_ADDR + 0x8400000000UL)
#define CIA_SPARSE_MEM_R3               (IDENT_ADDR + 0x8500000000UL)
#define CIA_DENSE_MEM                   (IDENT_ADDR + 0x8600000000UL)
 
/*
 * ALCOR's GRU ASIC registers
 */
#define GRU_INT_REQ                     (IDENT_ADDR + 0x8780000000UL)
#define GRU_INT_MASK                    (IDENT_ADDR + 0x8780000040UL)
#define GRU_INT_EDGE                    (IDENT_ADDR + 0x8780000080UL)
#define GRU_INT_HILO                    (IDENT_ADDR + 0x87800000C0UL)
#define GRU_INT_CLEAR                   (IDENT_ADDR + 0x8780000100UL)
 
#define GRU_CACHE_CNFG                  (IDENT_ADDR + 0x8780000200UL)
#define GRU_SCR                         (IDENT_ADDR + 0x8780000300UL)
#define GRU_LED                         (IDENT_ADDR + 0x8780000800UL)
#define GRU_RESET                       (IDENT_ADDR + 0x8780000900UL)
 
#if defined(CONFIG_ALPHA_ALCOR)
#define GRU_INT_REQ_BITS                0x800fffffUL
#elif defined(CONFIG_ALPHA_XLT)
#define GRU_INT_REQ_BITS                0x80003fffUL
#else
#define GRU_INT_REQ_BITS                0xffffffffUL
#endif
 
/*
 * Bit definitions for I/O Controller status register 0:
 */
#define CIA_IOC_STAT0_CMD               0xf
#define CIA_IOC_STAT0_ERR               (1<<4)
#define CIA_IOC_STAT0_LOST              (1<<5)
#define CIA_IOC_STAT0_THIT              (1<<6)
#define CIA_IOC_STAT0_TREF              (1<<7)
#define CIA_IOC_STAT0_CODE_SHIFT        8
#define CIA_IOC_STAT0_CODE_MASK         0x7
#define CIA_IOC_STAT0_P_NBR_SHIFT       13
#define CIA_IOC_STAT0_P_NBR_MASK        0x7ffff
 
#define HAE_ADDRESS                     CIA_IOC_HAE_MEM
 
#ifdef __KERNEL__
 
/*
 * Translate physical memory address as seen on (PCI) bus into
 * a kernel virtual address and vv.
 */
extern inline unsigned long virt_to_bus(void * address)
{
        return virt_to_phys(address) + CIA_DMA_WIN_BASE;
}
 
extern inline void * bus_to_virt(unsigned long address)
{
        return phys_to_virt(address - CIA_DMA_WIN_BASE);
}
 
/*
 * I/O functions:
 *
 * CIA (the 2117x PCI/memory support chipset for the EV5 (21164)
 * series of processors uses a sparse address mapping scheme to
 * get at PCI memory and I/O.
 */
 
#define vuip    volatile unsigned int *
 
extern inline unsigned int __inb(unsigned long addr)
{
        long result = *(vuip) ((addr << 5) + CIA_IO + 0x00);
        result >>= (addr & 3) * 8;
        return 0xffUL & result;
}
 
extern inline void __outb(unsigned char b, unsigned long addr)
{
        unsigned int w;
 
        asm ("insbl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b));
        *(vuip) ((addr << 5) + CIA_IO + 0x00) = w;
        mb();
}
 
extern inline unsigned int __inw(unsigned long addr)
{
        long result = *(vuip) ((addr << 5) + CIA_IO + 0x08);
        result >>= (addr & 3) * 8;
        return 0xffffUL & result;
}
 
extern inline void __outw(unsigned short b, unsigned long addr)
{
        unsigned int w;
 
        asm ("inswl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b));
        *(vuip) ((addr << 5) + CIA_IO + 0x08) = w;
        mb();
}
 
extern inline unsigned int __inl(unsigned long addr)
{
        return *(vuip) ((addr << 5) + CIA_IO + 0x18);
}
 
extern inline void __outl(unsigned int b, unsigned long addr)
{
        *(vuip) ((addr << 5) + CIA_IO + 0x18) = b;
        mb();
}
 
 
/*
 * Memory functions.  64-bit and 32-bit accesses are done through
 * dense memory space, everything else through sparse space.
 *
 * For reading and writing 8 and 16 bit quantities we need to
 * go through one of the three sparse address mapping regions
 * and use the HAE_MEM CSR to provide some bits of the address.
 * The following few routines use only sparse address region 1
 * which gives 1Gbyte of accessible space which relates exactly
 * to the amount of PCI memory mapping *into* system address space.
 * See p 6-17 of the specification but it looks something like this:
 *
 * 21164 Address:
 *
 *          3         2         1
 * 9876543210987654321098765432109876543210
 * 1ZZZZ0.PCI.QW.Address............BBLL
 *
 * ZZ = SBZ
 * BB = Byte offset
 * LL = Transfer length
 *
 * PCI Address:
 *
 * 3         2         1
 * 10987654321098765432109876543210
 * HHH....PCI.QW.Address........ 00
 *
 * HHH = 31:29 HAE_MEM CSR
 *
 */
 
#ifdef CONFIG_ALPHA_SRM_SETUP
 
extern unsigned long cia_sm_base_r1, cia_sm_base_r2, cia_sm_base_r3;
 
extern inline unsigned long __readb(unsigned long addr)
{
        unsigned long result, shift, work;
 
        if ((addr >= cia_sm_base_r1) &&
            (addr <= (cia_sm_base_r1 + MEM_R1_MASK)))
          work = (((addr & MEM_R1_MASK) << 5) + CIA_SPARSE_MEM + 0x00);
        else
        if ((addr >= cia_sm_base_r2) &&
            (addr <= (cia_sm_base_r2 + MEM_R2_MASK)))
          work = (((addr & MEM_R2_MASK) << 5) + CIA_SPARSE_MEM_R2 + 0x00);
        else
        if ((addr >= cia_sm_base_r3) &&
            (addr <= (cia_sm_base_r3 + MEM_R3_MASK)))
          work = (((addr & MEM_R3_MASK) << 5) + CIA_SPARSE_MEM_R3 + 0x00);
        else
        {
#if 0
          printk("__readb: address 0x%lx not covered by HAE\n", addr);
#endif
          return 0x0ffUL;
        }
        shift = (addr & 0x3) << 3;
        result = *(vuip) work;
        result >>= shift;
        return 0x0ffUL & result;
}
 
extern inline unsigned long __readw(unsigned long addr)
{
        unsigned long result, shift, work;
 
        if ((addr >= cia_sm_base_r1) &&
            (addr <= (cia_sm_base_r1 + MEM_R1_MASK)))
          work = (((addr & MEM_R1_MASK) << 5) + CIA_SPARSE_MEM + 0x08);
        else
        if ((addr >= cia_sm_base_r2) &&
            (addr <= (cia_sm_base_r2 + MEM_R2_MASK)))
          work = (((addr & MEM_R2_MASK) << 5) + CIA_SPARSE_MEM_R2 + 0x08);
        else
        if ((addr >= cia_sm_base_r3) &&
            (addr <= (cia_sm_base_r3 + MEM_R3_MASK)))
          work = (((addr & MEM_R3_MASK) << 5) + CIA_SPARSE_MEM_R3 + 0x08);
        else
        {
#if 0
          printk("__readw: address 0x%lx not covered by HAE\n", addr);
#endif
          return 0x0ffUL;
        }
        shift = (addr & 0x3) << 3;
        result = *(vuip) work;
        result >>= shift;
        return 0x0ffffUL & result;
}
 
extern inline void __writeb(unsigned char b, unsigned long addr)
{
        unsigned long work;
 
        if ((addr >= cia_sm_base_r1) &&
            (addr <= (cia_sm_base_r1 + MEM_R1_MASK)))
          work = (((addr & MEM_R1_MASK) << 5) + CIA_SPARSE_MEM + 0x00);
        else
        if ((addr >= cia_sm_base_r2) &&
            (addr <= (cia_sm_base_r2 + MEM_R2_MASK)))
          work = (((addr & MEM_R2_MASK) << 5) + CIA_SPARSE_MEM_R2 + 0x00);
        else
        if ((addr >= cia_sm_base_r3) &&
            (addr <= (cia_sm_base_r3 + MEM_R3_MASK)))
          work = (((addr & MEM_R3_MASK) << 5) + CIA_SPARSE_MEM_R3 + 0x00);
        else
        {
#if 0
          printk("__writeb: address 0x%lx not covered by HAE\n", addr);
#endif
          return;
        }
        *(vuip) work = b * 0x01010101;
}
 
extern inline void __writew(unsigned short b, unsigned long addr)
{
        unsigned long work;
 
        if ((addr >= cia_sm_base_r1) &&
            (addr <= (cia_sm_base_r1 + MEM_R1_MASK)))
          work = (((addr & MEM_R1_MASK) << 5) + CIA_SPARSE_MEM + 0x00);
        else
        if ((addr >= cia_sm_base_r2) &&
            (addr <= (cia_sm_base_r2 + MEM_R2_MASK)))
          work = (((addr & MEM_R2_MASK) << 5) + CIA_SPARSE_MEM_R2 + 0x00);
        else
        if ((addr >= cia_sm_base_r3) &&
            (addr <= (cia_sm_base_r3 + MEM_R3_MASK)))
          work = (((addr & MEM_R3_MASK) << 5) + CIA_SPARSE_MEM_R3 + 0x00);
        else
        {
#if 0
          printk("__writew: address 0x%lx not covered by HAE\n", addr);
#endif
          return;
        }
        *(vuip) work = b * 0x00010001;
}
 
#else /* SRM_SETUP */
 
extern inline unsigned long __readb(unsigned long addr)
{
        unsigned long result, shift, msb;
 
        shift = (addr & 0x3) * 8 ;
        msb = addr & 0xE0000000 ;
        addr &= MEM_R1_MASK ;
        if (msb != hae.cache) {
          set_hae(msb);
        }
        result = *(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x00) ;
        result >>= shift;
        return 0xffUL & result;
}
 
extern inline unsigned long __readw(unsigned long addr)
{
        unsigned long result, shift, msb;
 
        shift = (addr & 0x3) * 8;
        msb = addr & 0xE0000000 ;
        addr &= MEM_R1_MASK ;
        if (msb != hae.cache) {
          set_hae(msb);
        }
        result = *(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x08);
        result >>= shift;
        return 0xffffUL & result;
}
 
extern inline void __writeb(unsigned char b, unsigned long addr)
{
        unsigned long msb ;
 
        msb = addr & 0xE0000000 ;
        addr &= MEM_R1_MASK ;
        if (msb != hae.cache) {
          set_hae(msb);
        }
        *(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x00) = b * 0x01010101;
}
 
extern inline void __writew(unsigned short b, unsigned long addr)
{
        unsigned long msb ;
 
        msb = addr & 0xE0000000 ;
        addr &= MEM_R1_MASK ;
        if (msb != hae.cache) {
          set_hae(msb);
        }
        *(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x08) = b * 0x00010001;
}
 
#endif /* SRM_SETUP */
 
extern inline unsigned long __readl(unsigned long addr)
{
        return *(vuip) (addr + CIA_DENSE_MEM);
}
 
extern inline void __writel(unsigned int b, unsigned long addr)
{
        *(vuip) (addr + CIA_DENSE_MEM) = b;
}
 
#define inb(port) \
(__builtin_constant_p((port))?__inb(port):_inb(port))
 
#define outb(x, port) \
(__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port)))
 
#define readl(a)        __readl((unsigned long)(a))
#define writel(v,a)     __writel((v),(unsigned long)(a))
 
#undef vuip
 
extern unsigned long cia_init (unsigned long mem_start,
                                 unsigned long mem_end);
 
#endif /* __KERNEL__ */
 
/*
 * Data structure for handling CIA machine checks:
 */
/* ev5-specific info: */
struct el_procdata {
        unsigned long shadow[8];        /* PALmode shadow registers */
        unsigned long paltemp[24];      /* PAL temporary registers */
        /* EV5-specific fields */
        unsigned long exc_addr;         /* Address of excepting instruction. */
        unsigned long exc_sum;          /* Summary of arithmetic traps. */
        unsigned long exc_mask;         /* Exception mask (from exc_sum). */
        unsigned long exc_base;         /* PALbase at time of exception. */
        unsigned long isr;              /* Interrupt summary register. */
        unsigned long icsr;             /* Ibox control register. */
        unsigned long ic_perr_stat;
        unsigned long dc_perr_stat;
        unsigned long va;               /* Effective VA of fault or miss. */
        unsigned long mm_stat;
        unsigned long sc_addr;
        unsigned long sc_stat;
        unsigned long bc_tag_addr;
        unsigned long ei_addr;
        unsigned long fill_syn;
        unsigned long ei_stat;
        unsigned long ld_lock;
};
 
/* system-specific info: */
struct el_CIA_sysdata_mcheck {
    unsigned long      coma_gcr;
    unsigned long      coma_edsr;
    unsigned long      coma_ter;
    unsigned long      coma_elar;
    unsigned long      coma_ehar;
    unsigned long      coma_ldlr;
    unsigned long      coma_ldhr;
    unsigned long      coma_base0;
    unsigned long      coma_base1;
    unsigned long      coma_base2;
    unsigned long      coma_cnfg0;
    unsigned long      coma_cnfg1;
    unsigned long      coma_cnfg2;
    unsigned long      epic_dcsr;
    unsigned long      epic_pear;
    unsigned long      epic_sear;
    unsigned long      epic_tbr1;
    unsigned long      epic_tbr2;
    unsigned long      epic_pbr1;
    unsigned long      epic_pbr2;
    unsigned long      epic_pmr1;
    unsigned long      epic_pmr2;
    unsigned long      epic_harx1;
    unsigned long      epic_harx2;
    unsigned long      epic_pmlt;
    unsigned long      epic_tag0;
    unsigned long      epic_tag1;
    unsigned long      epic_tag2;
    unsigned long      epic_tag3;
    unsigned long      epic_tag4;
    unsigned long      epic_tag5;
    unsigned long      epic_tag6;
    unsigned long      epic_tag7;
    unsigned long      epic_data0;
    unsigned long      epic_data1;
    unsigned long      epic_data2;
    unsigned long      epic_data3;
    unsigned long      epic_data4;
    unsigned long      epic_data5;
    unsigned long      epic_data6;
    unsigned long      epic_data7;
};
 
#define RTC_PORT(x)     (0x70 + (x))
#define RTC_ADDR(x)     (0x80 | (x))
#define RTC_ALWAYS_BCD  0
 
#endif /* __ALPHA_CIA__H__ */

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[/] [or1k/] [trunk/] [uclinux/] [uClinux-2.0.x/] [include/] [asm-alpha/] [cia.h] - Blame information for rev 1778

Line No.	Rev	Author	Line
1	199	simons	`#ifndef __ALPHA_CIA__H__`
2			`#define __ALPHA_CIA__H__`
3
4			`#include <linux/config.h>`
5			`#include <linux/types.h>`
6
7			`/*`
8			`* CIA is the internal name for the 2117x chipset which provides`
9			`* memory controller and PCI access for the 21164 chip based systems.`
10			`*`
11			`* This file is based on:`
12			`*`
13			`* DECchip 21171 Core Logic Chipset`
14			`* Technical Reference Manual`
15			`*`
16			`* EC-QE18B-TE`
17			`*`
18			`* david.rusling@reo.mts.dec.com Initial Version.`
19			`*`
20			`*/`
21
22			`/------------------------------------------------------------------------*`
23			` `
24			` EB164 I/O procedures `
25			` `
26			` inport[b\|w\|t\|l], outport[b\|w\|t\|l] 8:16:24:32 IO xfers `
27			` inportbxt: 8 bits only `
28			` inport: alias of inportw `
29			` outport: alias of outportw `
30			` `
31			` inmem[b\|w\|t\|l], outmem[b\|w\|t\|l] 8:16:24:32 ISA memory xfers `
32			` inmembxt: 8 bits only `
33			` inmem: alias of inmemw `
34			` outmem: alias of outmemw `
35			` `
36			`*------------------------------------------------------------------------/`
37
38
39			`/* CIA ADDRESS BIT DEFINITIONS`
40			`*`
41			`* 3 3 3 3\|3 3 3 3\|3 3 2 2\|2 2 2 2\|2 2 2 2\|1 1 1 1\|1 1 1 1\|1 1`
42			`* 9 8 7 6\|5 4 3 2\|1 0 9 8\|7 6 5 4\|3 2 1 0\|9 8 7 6\|5 4 3 2\|1 0 9 8\|7 6 5 4\|3 2 1 0`
43			`* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+`
44			`* \|1\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|0\|0\|0\|`
45			`* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+`
46			`* \| \_/ \_/`
47			`* \| \| \|`
48			`* +-- IO space, not cached. Byte Enable --+ \|`
49			`* Transfer Length --+`
50			`*`
51			`*`
52			`*`
53			`* Byte Transfer`
54			`* Enable Length Transfer Byte Address`
55			`* adr<6:5> adr<4:3> Length Enable Adder`
56			`* ---------------------------------------------`
57			`* 00 00 Byte 1110 0x000`
58			`* 01 00 Byte 1101 0x020`
59			`* 10 00 Byte 1011 0x040`
60			`* 11 00 Byte 0111 0x060`
61			`*`
62			`* 00 01 Word 1100 0x008`
63			`* 01 01 Word 1001 0x028 <= Not supported in this code.`
64			`* 10 01 Word 0011 0x048`
65			`*`
66			`* 00 10 Tribyte 1000 0x010`
67			`* 01 10 Tribyte 0001 0x030`
68			`*`
69			`* 10 11 Longword 0000 0x058`
70			`*`
71			`* Note that byte enables are asserted low.`
72			`*`
73			`*/`
74
75			`#define BYTE_ENABLE_SHIFT 5`
76			`#define TRANSFER_LENGTH_SHIFT 3`
77
78			`#define MEM_R1_MASK 0x1fffffff /* SPARSE Mem region 1 mask is 29 bits */`
79			`#define MEM_R2_MASK 0x07ffffff /* SPARSE Mem region 2 mask is 27 bits */`
80			`#define MEM_R3_MASK 0x03ffffff /* SPARSE Mem region 3 mask is 26 bits */`
81
82			`#ifdef CONFIG_ALPHA_SRM_SETUP`
83			`/* if we are using the SRM PCI setup, we'll need to use variables instead */`
84			`#define CIA_DMA_WIN_BASE_DEFAULT (102410241024)`
85			`#define CIA_DMA_WIN_SIZE_DEFAULT (102410241024)`
86
87			`extern unsigned int CIA_DMA_WIN_BASE;`
88			`extern unsigned int CIA_DMA_WIN_SIZE;`
89
90			`#else /* SRM_SETUP */`
91			`#define CIA_DMA_WIN_BASE (102410241024)`
92			`#define CIA_DMA_WIN_SIZE (102410241024)`
93			`#endif /* SRM_SETUP */`
94
95			`/*`
96			`* 21171-CA Control and Status Registers (p4-1)`
97			`*/`
98			`#define CIA_IOC_CIA_REV (IDENT_ADDR + 0x8740000080UL)`
99			`#define CIA_IOC_PCI_LAT (IDENT_ADDR + 0x87400000C0UL)`
100			`#define CIA_IOC_CIA_CTRL (IDENT_ADDR + 0x8740000100UL)`
101			`#define CIA_IOC_CIA_CNFG (IDENT_ADDR + 0x8740000140UL)`
102			`#define CIA_IOC_HAE_MEM (IDENT_ADDR + 0x8740000400UL)`
103			`#define CIA_IOC_HAE_IO (IDENT_ADDR + 0x8740000440UL)`
104			`#define CIA_IOC_CFG (IDENT_ADDR + 0x8740000480UL)`
105			`#define CIA_IOC_CACK_EN (IDENT_ADDR + 0x8740000600UL)`
106
107			`/*`
108			`* 21171-CA Diagnostic Registers (p4-2)`
109			`*/`
110			`#define CIA_IOC_CIA_DIAG (IDENT_ADDR + 0x8740002000UL)`
111			`#define CIA_IOC_DIAG_CHECK (IDENT_ADDR + 0x8740003000UL)`
112
113			`/*`
114			`* 21171-CA Performance Monitor registers (p4-3)`
115			`*/`
116			`#define CIA_IOC_PERF_MONITOR (IDENT_ADDR + 0x8740004000UL)`
117			`#define CIA_IOC_PERF_CONTROL (IDENT_ADDR + 0x8740004040UL)`
118
119			`/*`
120			`* 21171-CA Error registers (p4-3)`
121			`*/`
122			`#define CIA_IOC_CPU_ERR0 (IDENT_ADDR + 0x8740008000UL)`
123			`#define CIA_IOC_CPU_ERR1 (IDENT_ADDR + 0x8740008040UL)`
124			`#define CIA_IOC_CIA_ERR (IDENT_ADDR + 0x8740008200UL)`
125			`#define CIA_IOC_CIA_STAT (IDENT_ADDR + 0x8740008240UL)`
126			`#define CIA_IOC_ERR_MASK (IDENT_ADDR + 0x8740008280UL)`
127			`#define CIA_IOC_CIA_SYN (IDENT_ADDR + 0x8740008300UL)`
128			`#define CIA_IOC_MEM_ERR0 (IDENT_ADDR + 0x8740008400UL)`
129			`#define CIA_IOC_MEM_ERR1 (IDENT_ADDR + 0x8740008440UL)`
130			`#define CIA_IOC_PCI_ERR0 (IDENT_ADDR + 0x8740008800UL)`
131			`#define CIA_IOC_PCI_ERR1 (IDENT_ADDR + 0x8740008840UL)`
132			`#define CIA_IOC_PCI_ERR3 (IDENT_ADDR + 0x8740008880UL)`
133
134			`/*`
135			`* 2117A-CA PCI Address Translation Registers.`
136			`*/`
137			`#define CIA_IOC_PCI_TBIA (IDENT_ADDR + 0x8760000100UL)`
138
139			`#define CIA_IOC_PCI_W0_BASE (IDENT_ADDR + 0x8760000400UL)`
140			`#define CIA_IOC_PCI_W0_MASK (IDENT_ADDR + 0x8760000440UL)`
141			`#define CIA_IOC_PCI_T0_BASE (IDENT_ADDR + 0x8760000480UL)`
142
143			`#define CIA_IOC_PCI_W1_BASE (IDENT_ADDR + 0x8760000500UL)`
144			`#define CIA_IOC_PCI_W1_MASK (IDENT_ADDR + 0x8760000540UL)`
145			`#define CIA_IOC_PCI_T1_BASE (IDENT_ADDR + 0x8760000580UL)`
146
147			`#define CIA_IOC_PCI_W2_BASE (IDENT_ADDR + 0x8760000600UL)`
148			`#define CIA_IOC_PCI_W2_MASK (IDENT_ADDR + 0x8760000640UL)`
149			`#define CIA_IOC_PCI_T2_BASE (IDENT_ADDR + 0x8760000680UL)`
150
151			`#define CIA_IOC_PCI_W3_BASE (IDENT_ADDR + 0x8760000700UL)`
152			`#define CIA_IOC_PCI_W3_MASK (IDENT_ADDR + 0x8760000740UL)`
153			`#define CIA_IOC_PCI_T3_BASE (IDENT_ADDR + 0x8760000780UL)`
154
155			`/*`
156			`* 21171-CA System configuration registers (p4-3)`
157			`*/`
158			`#define CIA_IOC_MCR (IDENT_ADDR + 0x8750000000UL)`
159			`#define CIA_IOC_MBA0 (IDENT_ADDR + 0x8750000600UL)`
160			`#define CIA_IOC_MBA2 (IDENT_ADDR + 0x8750000680UL)`
161			`#define CIA_IOC_MBA4 (IDENT_ADDR + 0x8750000700UL)`
162			`#define CIA_IOC_MBA6 (IDENT_ADDR + 0x8750000780UL)`
163			`#define CIA_IOC_MBA8 (IDENT_ADDR + 0x8750000800UL)`
164			`#define CIA_IOC_MBAA (IDENT_ADDR + 0x8750000880UL)`
165			`#define CIA_IOC_MBAC (IDENT_ADDR + 0x8750000900UL)`
166			`#define CIA_IOC_MBAE (IDENT_ADDR + 0x8750000980UL)`
167			`#define CIA_IOC_TMG0 (IDENT_ADDR + 0x8750000B00UL)`
168			`#define CIA_IOC_TMG1 (IDENT_ADDR + 0x8750000B40UL)`
169			`#define CIA_IOC_TMG2 (IDENT_ADDR + 0x8750000B80UL)`
170
171			`/*`
172			`* Memory spaces:`
173			`*/`
174			`#define CIA_IACK_SC (IDENT_ADDR + 0x8720000000UL)`
175			`#define CIA_CONF (IDENT_ADDR + 0x8700000000UL)`
176			`#define CIA_IO (IDENT_ADDR + 0x8580000000UL)`
177			`#define CIA_SPARSE_MEM (IDENT_ADDR + 0x8000000000UL)`
178			`#define CIA_SPARSE_MEM_R2 (IDENT_ADDR + 0x8400000000UL)`
179			`#define CIA_SPARSE_MEM_R3 (IDENT_ADDR + 0x8500000000UL)`
180			`#define CIA_DENSE_MEM (IDENT_ADDR + 0x8600000000UL)`
181
182			`/*`
183			`* ALCOR's GRU ASIC registers`
184			`*/`
185			`#define GRU_INT_REQ (IDENT_ADDR + 0x8780000000UL)`
186			`#define GRU_INT_MASK (IDENT_ADDR + 0x8780000040UL)`
187			`#define GRU_INT_EDGE (IDENT_ADDR + 0x8780000080UL)`
188			`#define GRU_INT_HILO (IDENT_ADDR + 0x87800000C0UL)`
189			`#define GRU_INT_CLEAR (IDENT_ADDR + 0x8780000100UL)`
190
191			`#define GRU_CACHE_CNFG (IDENT_ADDR + 0x8780000200UL)`
192			`#define GRU_SCR (IDENT_ADDR + 0x8780000300UL)`
193			`#define GRU_LED (IDENT_ADDR + 0x8780000800UL)`
194			`#define GRU_RESET (IDENT_ADDR + 0x8780000900UL)`
195
196			`#if defined(CONFIG_ALPHA_ALCOR)`
197			`#define GRU_INT_REQ_BITS 0x800fffffUL`
198			`#elif defined(CONFIG_ALPHA_XLT)`
199			`#define GRU_INT_REQ_BITS 0x80003fffUL`
200			`#else`
201			`#define GRU_INT_REQ_BITS 0xffffffffUL`
202			`#endif`
203
204			`/*`
205			`* Bit definitions for I/O Controller status register 0:`
206			`*/`
207			`#define CIA_IOC_STAT0_CMD 0xf`
208			`#define CIA_IOC_STAT0_ERR (1<<4)`
209			`#define CIA_IOC_STAT0_LOST (1<<5)`
210			`#define CIA_IOC_STAT0_THIT (1<<6)`
211			`#define CIA_IOC_STAT0_TREF (1<<7)`
212			`#define CIA_IOC_STAT0_CODE_SHIFT 8`
213			`#define CIA_IOC_STAT0_CODE_MASK 0x7`
214			`#define CIA_IOC_STAT0_P_NBR_SHIFT 13`
215			`#define CIA_IOC_STAT0_P_NBR_MASK 0x7ffff`
216
217			`#define HAE_ADDRESS CIA_IOC_HAE_MEM`
218
219			`#ifdef __KERNEL__`
220
221			`/*`
222			`* Translate physical memory address as seen on (PCI) bus into`
223			`* a kernel virtual address and vv.`
224			`*/`
225			`extern inline unsigned long virt_to_bus(void * address)`
226			`{`
227			`return virt_to_phys(address) + CIA_DMA_WIN_BASE;`
228			`}`
229
230			`extern inline void * bus_to_virt(unsigned long address)`
231			`{`
232			`return phys_to_virt(address - CIA_DMA_WIN_BASE);`
233			`}`
234
235			`/*`
236			`* I/O functions:`
237			`*`
238			`* CIA (the 2117x PCI/memory support chipset for the EV5 (21164)`
239			`* series of processors uses a sparse address mapping scheme to`
240			`* get at PCI memory and I/O.`
241			`*/`
242
243			`#define vuip volatile unsigned int *`
244
245			`extern inline unsigned int __inb(unsigned long addr)`
246			`{`
247			`long result = *(vuip) ((addr << 5) + CIA_IO + 0x00);`
248			`result >>= (addr & 3) * 8;`
249			`return 0xffUL & result;`
250			`}`
251
252			`extern inline void __outb(unsigned char b, unsigned long addr)`
253			`{`
254			`unsigned int w;`
255
256			`asm ("insbl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b));`
257			`*(vuip) ((addr << 5) + CIA_IO + 0x00) = w;`
258			`mb();`
259			`}`
260
261			`extern inline unsigned int __inw(unsigned long addr)`
262			`{`
263			`long result = *(vuip) ((addr << 5) + CIA_IO + 0x08);`
264			`result >>= (addr & 3) * 8;`
265			`return 0xffffUL & result;`
266			`}`
267
268			`extern inline void __outw(unsigned short b, unsigned long addr)`
269			`{`
270			`unsigned int w;`
271
272			`asm ("inswl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b));`
273			`*(vuip) ((addr << 5) + CIA_IO + 0x08) = w;`
274			`mb();`
275			`}`
276
277			`extern inline unsigned int __inl(unsigned long addr)`
278			`{`
279			`return *(vuip) ((addr << 5) + CIA_IO + 0x18);`
280			`}`
281
282			`extern inline void __outl(unsigned int b, unsigned long addr)`
283			`{`
284			`*(vuip) ((addr << 5) + CIA_IO + 0x18) = b;`
285			`mb();`
286			`}`
287
288
289			`/*`
290			`* Memory functions. 64-bit and 32-bit accesses are done through`
291			`* dense memory space, everything else through sparse space.`
292			`*`
293			`* For reading and writing 8 and 16 bit quantities we need to`
294			`* go through one of the three sparse address mapping regions`
295			`* and use the HAE_MEM CSR to provide some bits of the address.`
296			`* The following few routines use only sparse address region 1`
297			`* which gives 1Gbyte of accessible space which relates exactly`
298			`* to the amount of PCI memory mapping into system address space.`
299			`* See p 6-17 of the specification but it looks something like this:`
300			`*`
301			`* 21164 Address:`
302			`*`
303			`* 3 2 1`
304			`* 9876543210987654321098765432109876543210`
305			`* 1ZZZZ0.PCI.QW.Address............BBLL`
306			`*`
307			`* ZZ = SBZ`
308			`* BB = Byte offset`
309			`* LL = Transfer length`
310			`*`
311			`* PCI Address:`
312			`*`
313			`* 3 2 1`
314			`* 10987654321098765432109876543210`
315			`* HHH....PCI.QW.Address........ 00`
316			`*`
317			`* HHH = 31:29 HAE_MEM CSR`
318			`*`
319			`*/`
320
321			`#ifdef CONFIG_ALPHA_SRM_SETUP`
322
323			`extern unsigned long cia_sm_base_r1, cia_sm_base_r2, cia_sm_base_r3;`
324
325			`extern inline unsigned long __readb(unsigned long addr)`
326			`{`
327			`unsigned long result, shift, work;`
328
329			`if ((addr >= cia_sm_base_r1) &&`
330			`(addr <= (cia_sm_base_r1 + MEM_R1_MASK)))`
331			`work = (((addr & MEM_R1_MASK) << 5) + CIA_SPARSE_MEM + 0x00);`
332			`else`
333			`if ((addr >= cia_sm_base_r2) &&`
334			`(addr <= (cia_sm_base_r2 + MEM_R2_MASK)))`
335			`work = (((addr & MEM_R2_MASK) << 5) + CIA_SPARSE_MEM_R2 + 0x00);`
336			`else`
337			`if ((addr >= cia_sm_base_r3) &&`
338			`(addr <= (cia_sm_base_r3 + MEM_R3_MASK)))`
339			`work = (((addr & MEM_R3_MASK) << 5) + CIA_SPARSE_MEM_R3 + 0x00);`
340			`else`
341			`{`
342			`#if 0`
343			`printk("__readb: address 0x%lx not covered by HAE\n", addr);`
344			`#endif`
345			`return 0x0ffUL;`
346			`}`
347			`shift = (addr & 0x3) << 3;`
348			`result = *(vuip) work;`
349			`result >>= shift;`
350			`return 0x0ffUL & result;`
351			`}`
352
353			`extern inline unsigned long __readw(unsigned long addr)`
354			`{`
355			`unsigned long result, shift, work;`
356
357			`if ((addr >= cia_sm_base_r1) &&`
358			`(addr <= (cia_sm_base_r1 + MEM_R1_MASK)))`
359			`work = (((addr & MEM_R1_MASK) << 5) + CIA_SPARSE_MEM + 0x08);`
360			`else`
361			`if ((addr >= cia_sm_base_r2) &&`
362			`(addr <= (cia_sm_base_r2 + MEM_R2_MASK)))`
363			`work = (((addr & MEM_R2_MASK) << 5) + CIA_SPARSE_MEM_R2 + 0x08);`
364			`else`
365			`if ((addr >= cia_sm_base_r3) &&`
366			`(addr <= (cia_sm_base_r3 + MEM_R3_MASK)))`
367			`work = (((addr & MEM_R3_MASK) << 5) + CIA_SPARSE_MEM_R3 + 0x08);`
368			`else`
369			`{`
370			`#if 0`
371			`printk("__readw: address 0x%lx not covered by HAE\n", addr);`
372			`#endif`
373			`return 0x0ffUL;`
374			`}`
375			`shift = (addr & 0x3) << 3;`
376			`result = *(vuip) work;`
377			`result >>= shift;`
378			`return 0x0ffffUL & result;`
379			`}`
380
381			`extern inline void __writeb(unsigned char b, unsigned long addr)`
382			`{`
383			`unsigned long work;`
384
385			`if ((addr >= cia_sm_base_r1) &&`
386			`(addr <= (cia_sm_base_r1 + MEM_R1_MASK)))`
387			`work = (((addr & MEM_R1_MASK) << 5) + CIA_SPARSE_MEM + 0x00);`
388			`else`
389			`if ((addr >= cia_sm_base_r2) &&`
390			`(addr <= (cia_sm_base_r2 + MEM_R2_MASK)))`
391			`work = (((addr & MEM_R2_MASK) << 5) + CIA_SPARSE_MEM_R2 + 0x00);`
392			`else`
393			`if ((addr >= cia_sm_base_r3) &&`
394			`(addr <= (cia_sm_base_r3 + MEM_R3_MASK)))`
395			`work = (((addr & MEM_R3_MASK) << 5) + CIA_SPARSE_MEM_R3 + 0x00);`
396			`else`
397			`{`
398			`#if 0`
399			`printk("__writeb: address 0x%lx not covered by HAE\n", addr);`
400			`#endif`
401			`return;`
402			`}`
403			`(vuip) work = b 0x01010101;`
404			`}`
405
406			`extern inline void __writew(unsigned short b, unsigned long addr)`
407			`{`
408			`unsigned long work;`
409
410			`if ((addr >= cia_sm_base_r1) &&`
411			`(addr <= (cia_sm_base_r1 + MEM_R1_MASK)))`
412			`work = (((addr & MEM_R1_MASK) << 5) + CIA_SPARSE_MEM + 0x00);`
413			`else`
414			`if ((addr >= cia_sm_base_r2) &&`
415			`(addr <= (cia_sm_base_r2 + MEM_R2_MASK)))`
416			`work = (((addr & MEM_R2_MASK) << 5) + CIA_SPARSE_MEM_R2 + 0x00);`
417			`else`
418			`if ((addr >= cia_sm_base_r3) &&`
419			`(addr <= (cia_sm_base_r3 + MEM_R3_MASK)))`
420			`work = (((addr & MEM_R3_MASK) << 5) + CIA_SPARSE_MEM_R3 + 0x00);`
421			`else`
422			`{`
423			`#if 0`
424			`printk("__writew: address 0x%lx not covered by HAE\n", addr);`
425			`#endif`
426			`return;`
427			`}`
428			`(vuip) work = b 0x00010001;`
429			`}`
430
431			`#else /* SRM_SETUP */`
432
433			`extern inline unsigned long __readb(unsigned long addr)`
434			`{`
435			`unsigned long result, shift, msb;`
436
437			`shift = (addr & 0x3) * 8 ;`
438			`msb = addr & 0xE0000000 ;`
439			`addr &= MEM_R1_MASK ;`
440			`if (msb != hae.cache) {`
441			`set_hae(msb);`
442			`}`
443			`result = *(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x00) ;`
444			`result >>= shift;`
445			`return 0xffUL & result;`
446			`}`
447
448			`extern inline unsigned long __readw(unsigned long addr)`
449			`{`
450			`unsigned long result, shift, msb;`
451
452			`shift = (addr & 0x3) * 8;`
453			`msb = addr & 0xE0000000 ;`
454			`addr &= MEM_R1_MASK ;`
455			`if (msb != hae.cache) {`
456			`set_hae(msb);`
457			`}`
458			`result = *(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x08);`
459			`result >>= shift;`
460			`return 0xffffUL & result;`
461			`}`
462
463			`extern inline void __writeb(unsigned char b, unsigned long addr)`
464			`{`
465			`unsigned long msb ;`
466
467			`msb = addr & 0xE0000000 ;`
468			`addr &= MEM_R1_MASK ;`
469			`if (msb != hae.cache) {`
470			`set_hae(msb);`
471			`}`
472			`(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x00) = b 0x01010101;`
473			`}`
474
475			`extern inline void __writew(unsigned short b, unsigned long addr)`
476			`{`
477			`unsigned long msb ;`
478
479			`msb = addr & 0xE0000000 ;`
480			`addr &= MEM_R1_MASK ;`
481			`if (msb != hae.cache) {`
482			`set_hae(msb);`
483			`}`
484			`(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x08) = b 0x00010001;`
485			`}`
486
487			`#endif /* SRM_SETUP */`
488
489			`extern inline unsigned long __readl(unsigned long addr)`
490			`{`
491			`return *(vuip) (addr + CIA_DENSE_MEM);`
492			`}`
493
494			`extern inline void __writel(unsigned int b, unsigned long addr)`
495			`{`
496			`*(vuip) (addr + CIA_DENSE_MEM) = b;`
497			`}`
498
499			`#define inb(port) \`
500			`(__builtin_constant_p((port))?__inb(port):_inb(port))`
501
502			`#define outb(x, port) \`
503			`(__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port)))`
504
505			`#define readl(a) __readl((unsigned long)(a))`
506			`#define writel(v,a) __writel((v),(unsigned long)(a))`
507
508			`#undef vuip`
509
510			`extern unsigned long cia_init (unsigned long mem_start,`
511			`unsigned long mem_end);`
512
513			`#endif /* __KERNEL__ */`
514
515			`/*`
516			`* Data structure for handling CIA machine checks:`
517			`*/`
518			`/* ev5-specific info: */`
519			`struct el_procdata {`
520			`unsigned long shadow[8]; /* PALmode shadow registers */`
521			`unsigned long paltemp[24]; /* PAL temporary registers */`
522			`/* EV5-specific fields */`
523			`unsigned long exc_addr; /* Address of excepting instruction. */`
524			`unsigned long exc_sum; /* Summary of arithmetic traps. */`
525			`unsigned long exc_mask; /* Exception mask (from exc_sum). */`
526			`unsigned long exc_base; /* PALbase at time of exception. */`
527			`unsigned long isr; /* Interrupt summary register. */`
528			`unsigned long icsr; /* Ibox control register. */`
529			`unsigned long ic_perr_stat;`
530			`unsigned long dc_perr_stat;`
531			`unsigned long va; /* Effective VA of fault or miss. */`
532			`unsigned long mm_stat;`
533			`unsigned long sc_addr;`
534			`unsigned long sc_stat;`
535			`unsigned long bc_tag_addr;`
536			`unsigned long ei_addr;`
537			`unsigned long fill_syn;`
538			`unsigned long ei_stat;`
539			`unsigned long ld_lock;`
540			`};`
541
542			`/* system-specific info: */`
543			`struct el_CIA_sysdata_mcheck {`
544			`unsigned long coma_gcr;`
545			`unsigned long coma_edsr;`
546			`unsigned long coma_ter;`
547			`unsigned long coma_elar;`
548			`unsigned long coma_ehar;`
549			`unsigned long coma_ldlr;`
550			`unsigned long coma_ldhr;`
551			`unsigned long coma_base0;`
552			`unsigned long coma_base1;`
553			`unsigned long coma_base2;`
554			`unsigned long coma_cnfg0;`
555			`unsigned long coma_cnfg1;`
556			`unsigned long coma_cnfg2;`
557			`unsigned long epic_dcsr;`
558			`unsigned long epic_pear;`
559			`unsigned long epic_sear;`
560			`unsigned long epic_tbr1;`
561			`unsigned long epic_tbr2;`
562			`unsigned long epic_pbr1;`
563			`unsigned long epic_pbr2;`
564			`unsigned long epic_pmr1;`
565			`unsigned long epic_pmr2;`
566			`unsigned long epic_harx1;`
567			`unsigned long epic_harx2;`
568			`unsigned long epic_pmlt;`
569			`unsigned long epic_tag0;`
570			`unsigned long epic_tag1;`
571			`unsigned long epic_tag2;`
572			`unsigned long epic_tag3;`
573			`unsigned long epic_tag4;`
574			`unsigned long epic_tag5;`
575			`unsigned long epic_tag6;`
576			`unsigned long epic_tag7;`
577			`unsigned long epic_data0;`
578			`unsigned long epic_data1;`
579			`unsigned long epic_data2;`
580			`unsigned long epic_data3;`
581			`unsigned long epic_data4;`
582			`unsigned long epic_data5;`
583			`unsigned long epic_data6;`
584			`unsigned long epic_data7;`
585			`};`
586
587			`#define RTC_PORT(x) (0x70 + (x))`
588			`#define RTC_ADDR(x) (0x80 \| (x))`
589			`#define RTC_ALWAYS_BCD 0`
590
591			`#endif /* __ALPHA_CIA__H__ */`