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[/] [or1k/] [trunk/] [uclinux/] [uClinux-2.0.x/] [include/] [asm-alpha/] [pyxis.h] - Blame information for rev 1765

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1 199 simons 
#ifndef __ALPHA_PYXIS__H__
2 
#define __ALPHA_PYXIS__H__
3 
 
4 
#include <linux/config.h>
5 
#include <linux/types.h>
6 
 
7 
/*
8 
 * PYXIS is the internal name for a core logic chipset which provides
9 
 * memory controller and PCI access for the 21164A chip based systems.
10 
 *
11 
 * This file is based on:
12 
 *
13 
 * Pyxis Chipset Spec
14 
 * 14-Jun-96
15 
 * Rev. X2.0
16 
 *
17 
 */
18 
 
19 
/*------------------------------------------------------------------------**
20 
**                                                                        **
21 
**  I/O procedures                                                   **
22 
**                                                                        **
23 
**      inport[b|w|t|l], outport[b|w|t|l] 8:16:24:32 IO xfers             **
24 
**      inportbxt: 8 bits only                                            **
25 
**      inport:    alias of inportw                                       **
26 
**      outport:   alias of outportw                                      **
27 
**                                                                        **
28 
**      inmem[b|w|t|l], outmem[b|w|t|l] 8:16:24:32 ISA memory xfers       **
29 
**      inmembxt: 8 bits only                                             **
30 
**      inmem:    alias of inmemw                                         **
31 
**      outmem:   alias of outmemw                                        **
32 
**                                                                        **
33 
**------------------------------------------------------------------------*/
34 
 
35 
 
36 
/* CIA ADDRESS BIT DEFINITIONS
37 
 *
38 
 *  3 3 3 3|3 3 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
39 
 *  9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
40 
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
41 
 * |1| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |0|0|0|
42 
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
43 
 *  |                                                                        \_/ \_/
44 
 *  |                                                                         |   |
45 
 *  +-- IO space, not cached.                                   Byte Enable --+   |
46 
 *                                                              Transfer Length --+
47 
 *
48 
 *
49 
 *
50 
 *   Byte      Transfer
51 
 *   Enable    Length    Transfer  Byte    Address
52 
 *   adr<6:5>  adr<4:3>  Length    Enable  Adder
53 
 *   ---------------------------------------------
54 
 *      00        00      Byte      1110   0x000
55 
 *      01        00      Byte      1101   0x020
56 
 *      10        00      Byte      1011   0x040
57 
 *      11        00      Byte      0111   0x060
58 
 *
59 
 *      00        01      Word      1100   0x008
60 
 *      01        01      Word      1001   0x028 <= Not supported in this code.
61 
 *      10        01      Word      0011   0x048
62 
 *
63 
 *      00        10      Tribyte   1000   0x010
64 
 *      01        10      Tribyte   0001   0x030
65 
 *
66 
 *      10        11      Longword  0000   0x058
67 
 *
68 
 *      Note that byte enables are asserted low.
69 
 *
70 
 */
71 
 
72 
#define BYTE_ENABLE_SHIFT 5
73 
#define TRANSFER_LENGTH_SHIFT 3
74 
 
75 
#define MEM_R1_MASK 0x1fffffff  /* SPARSE Mem region 1 mask is 29 bits */
76 
#define MEM_R2_MASK 0x07ffffff  /* SPARSE Mem region 2 mask is 27 bits */
77 
#define MEM_R3_MASK 0x03ffffff  /* SPARSE Mem region 3 mask is 26 bits */
78 
 
79 
#ifdef CONFIG_ALPHA_SRM_SETUP
80 
/* if we are using the SRM PCI setup, we'll need to use variables instead */
81 
#define PYXIS_DMA_WIN_BASE_DEFAULT    (1024*1024*1024)
82 
#define PYXIS_DMA_WIN_SIZE_DEFAULT    (1024*1024*1024)
83 
 
84 
extern unsigned int PYXIS_DMA_WIN_BASE;
85 
extern unsigned int PYXIS_DMA_WIN_SIZE;
86 
 
87 
#else /* SRM_SETUP */
88 
#define PYXIS_DMA_WIN_BASE      (1024*1024*1024)
89 
#define PYXIS_DMA_WIN_SIZE      (1024*1024*1024)
90 
#endif /* SRM_SETUP */
91 
 
92 
/*
93 
 *  General Registers
94 
 */
95 
#define PYXIS_REV                       (IDENT_ADDR + 0x8740000080UL)
96 
#define PYXIS_PCI_LAT                   (IDENT_ADDR + 0x87400000C0UL)
97 
#define PYXIS_CTRL                      (IDENT_ADDR + 0x8740000100UL)
98 
#define PYXIS_CTRL1                     (IDENT_ADDR + 0x8740000140UL)
99 
#define PYXIS_FLASH_CTRL                (IDENT_ADDR + 0x8740000200UL)
100 
 
101 
#define PYXIS_HAE_MEM                   (IDENT_ADDR + 0x8740000400UL)
102 
#define PYXIS_HAE_IO                    (IDENT_ADDR + 0x8740000440UL)
103 
#define PYXIS_CFG                       (IDENT_ADDR + 0x8740000480UL)
104 
 
105 
/*
106 
 * Diagnostic Registers
107 
 */
108 
#define PYXIS_DIAG                      (IDENT_ADDR + 0x8740002000UL)
109 
#define PYXIS_DIAG_CHECK                (IDENT_ADDR + 0x8740003000UL)
110 
 
111 
/*
112 
 * Performance Monitor registers
113 
 */
114 
#define PYXIS_PERF_MONITOR              (IDENT_ADDR + 0x8740004000UL)
115 
#define PYXIS_PERF_CONTROL              (IDENT_ADDR + 0x8740004040UL)
116 
 
117 
/*
118 
 * Error registers
119 
 */
120 
#define PYXIS_ERR                       (IDENT_ADDR + 0x8740008200UL)
121 
#define PYXIS_STAT                      (IDENT_ADDR + 0x8740008240UL)
122 
#define PYXIS_ERR_MASK                  (IDENT_ADDR + 0x8740008280UL)
123 
#define PYXIS_SYN                       (IDENT_ADDR + 0x8740008300UL)
124 
#define PYXIS_ERR_DATA                  (IDENT_ADDR + 0x8740008308UL)
125 
 
126 
#define PYXIS_MEAR                      (IDENT_ADDR + 0x8740008400UL)
127 
#define PYXIS_MESR                      (IDENT_ADDR + 0x8740008440UL)
128 
#define PYXIS_PCI_ERR0                  (IDENT_ADDR + 0x8740008800UL)
129 
#define PYXIS_PCI_ERR1                  (IDENT_ADDR + 0x8740008840UL)
130 
#define PYXIS_PCI_ERR2                  (IDENT_ADDR + 0x8740008880UL)
131 
 
132 
/*
133 
 * PCI Address Translation Registers.
134 
 */
135 
#define PYXIS_TBIA                      (IDENT_ADDR + 0x8760000100UL)
136 
 
137 
#define PYXIS_W0_BASE                   (IDENT_ADDR + 0x8760000400UL)
138 
#define PYXIS_W0_MASK                   (IDENT_ADDR + 0x8760000440UL)
139 
#define PYXIS_T0_BASE                   (IDENT_ADDR + 0x8760000480UL)
140 
 
141 
#define PYXIS_W1_BASE                   (IDENT_ADDR + 0x8760000500UL)
142 
#define PYXIS_W1_MASK                   (IDENT_ADDR + 0x8760000540UL)
143 
#define PYXIS_T1_BASE                   (IDENT_ADDR + 0x8760000580UL)
144 
 
145 
#define PYXIS_W2_BASE                   (IDENT_ADDR + 0x8760000600UL)
146 
#define PYXIS_W2_MASK                   (IDENT_ADDR + 0x8760000640UL)
147 
#define PYXIS_T2_BASE                   (IDENT_ADDR + 0x8760000680UL)
148 
 
149 
#define PYXIS_W3_BASE                   (IDENT_ADDR + 0x8760000700UL)
150 
#define PYXIS_W3_MASK                   (IDENT_ADDR + 0x8760000740UL)
151 
#define PYXIS_T3_BASE                   (IDENT_ADDR + 0x8760000780UL)
152 
 
153 
/*
154 
 * Memory Control registers
155 
 */
156 
#define PYXIS_MCR                       (IDENT_ADDR + 0x8750000000UL)
157 
 
158 
/*
159 
 * Memory spaces:
160 
 */
161 
#define PYXIS_IACK_SC                   (IDENT_ADDR + 0x8720000000UL)
162 
#define PYXIS_CONF                      (IDENT_ADDR + 0x8700000000UL)
163 
#define PYXIS_IO                        (IDENT_ADDR + 0x8580000000UL)
164 
#define PYXIS_SPARSE_MEM                (IDENT_ADDR + 0x8000000000UL)
165 
#define PYXIS_SPARSE_MEM_R2             (IDENT_ADDR + 0x8400000000UL)
166 
#define PYXIS_SPARSE_MEM_R3             (IDENT_ADDR + 0x8500000000UL)
167 
#define PYXIS_DENSE_MEM                 (IDENT_ADDR + 0x8600000000UL)
168 
 
169 
/*
170 
 * Byte/Word PCI Memory Spaces:
171 
 */
172 
#define PYXIS_BW_MEM                    (IDENT_ADDR + 0x8800000000UL)
173 
#define PYXIS_BW_IO                     (IDENT_ADDR + 0x8900000000UL)
174 
#define PYXIS_BW_CFG_0                  (IDENT_ADDR + 0x8a00000000UL)
175 
#define PYXIS_BW_CFG_1                  (IDENT_ADDR + 0x8b00000000UL)
176 
 
177 
/*
178 
 * Interrupt Control registers
179 
 */
180 
#define PYXIS_INT_REQ                   (IDENT_ADDR + 0x87A0000000UL)
181 
#define PYXIS_INT_MASK                  (IDENT_ADDR + 0x87A0000040UL)
182 
#define PYXIS_INT_HILO                  (IDENT_ADDR + 0x87A00000C0UL)
183 
#define PYXIS_INT_ROUTE                 (IDENT_ADDR + 0x87A0000140UL)
184 
#define PYXIS_GPO                       (IDENT_ADDR + 0x87A0000180UL)
185 
#define PYXIS_INT_CNFG                  (IDENT_ADDR + 0x87A00001C0UL)
186 
#define PYXIS_RT_COUNT                  (IDENT_ADDR + 0x87A0000200UL)
187 
#define PYXIS_INT_TIME                  (IDENT_ADDR + 0x87A0000240UL)
188 
#define PYXIS_IIC_CTRL                  (IDENT_ADDR + 0x87A00002C0UL)
189 
 
190 
/*
191 
 * Bit definitions for I/O Controller status register 0:
192 
 */
193 
#define PYXIS_STAT0_CMD                 0xf
194 
#define PYXIS_STAT0_ERR                 (1<<4)
195 
#define PYXIS_STAT0_LOST                (1<<5)
196 
#define PYXIS_STAT0_THIT                (1<<6)
197 
#define PYXIS_STAT0_TREF                (1<<7)
198 
#define PYXIS_STAT0_CODE_SHIFT          8
199 
#define PYXIS_STAT0_CODE_MASK           0x7
200 
#define PYXIS_STAT0_P_NBR_SHIFT         13
201 
#define PYXIS_STAT0_P_NBR_MASK          0x7ffff
202 
 
203 
#define HAE_ADDRESS                     PYXIS_HAE_MEM
204 
 
205 
#ifdef __KERNEL__
206 
 
207 
/*
208 
 * Translate physical memory address as seen on (PCI) bus into
209 
 * a kernel virtual address and vv.
210 
 */
211 
#if defined(CONFIG_ALPHA_RUFFIAN)
212 
#if 0
213 
/* Ruffian doesn't do 1G PCI window */
214 
extern inline unsigned long virt_to_bus(void * address)
215 
{
216 
        return virt_to_phys(address);
217 
}
218 
 
219 
extern inline void * bus_to_virt(unsigned long address)
220 
{
221 
        return phys_to_virt(address);
222 
}
223 
#else
224 
/* Oh, yes, it does (at least with the latest FW) */
225 
extern inline unsigned long virt_to_bus(void * address)
226 
{
227 
        return virt_to_phys(address) + PYXIS_DMA_WIN_BASE;
228 
}
229 
 
230 
extern inline void * bus_to_virt(unsigned long address)
231 
{
232 
        return phys_to_virt(address - PYXIS_DMA_WIN_BASE);
233 
}
234 
#endif
235 
#else /* RUFFIAN */
236 
extern inline unsigned long virt_to_bus(void * address)
237 
{
238 
        return virt_to_phys(address) + PYXIS_DMA_WIN_BASE;
239 
}
240 
 
241 
extern inline void * bus_to_virt(unsigned long address)
242 
{
243 
        return phys_to_virt(address - PYXIS_DMA_WIN_BASE);
244 
}
245 
#endif /* RUFFIAN */
246 
 
247 
/*
248 
 * I/O functions:
249 
 *
250 
 * PYXIS, the 21174 PCI/memory support chipset for the EV56 (21164)
251 
 * and PCA56 (21164PC) processors, can use either a sparse address
252 
 * mapping scheme, or the so-called byte-word PCI address space, to
253 
 * get at PCI memory and I/O.
254 
 */
255 
 
256 
#define vuip    volatile unsigned int *
257 
 
258 
#if defined(BWIO_ENABLED)
259 
# if defined(CONFIG_ALPHA_LX164) || \
260 
     defined(CONFIG_ALPHA_SX164)
261 
/* only for the above platforms can we be sure this will work */
262 
#  define BWIO_REALLY_ENABLED
263 
# else
264 
#  undef BWIO_REALLY_ENABLED
265 
# endif
266 
#else
267 
# undef BWIO_REALLY_ENABLED
268 
#endif
269 
 
270 
#ifdef BWIO_REALLY_ENABLED
271 
 
272 
extern inline unsigned int __inb(unsigned long addr)
273 
{
274 
        register unsigned long result;
275 
 
276 
        __asm__ __volatile__ (
277 
                 "ldbu %0,%1"
278 
                 : "=r" (result)
279 
                 : "m"  (*(unsigned char *)(addr+PYXIS_BW_IO)));
280 
 
281 
        return result;
282 
}
283 
 
284 
extern inline void __outb(unsigned char b, unsigned long addr)
285 
{
286 
        __asm__ __volatile__ (
287 
                 "stb %1,%0\n\t"
288 
                 "mb"
289 
                 : : "m" (*(unsigned char *)(addr+PYXIS_BW_IO)), "r" (b));
290 
}
291 
 
292 
extern inline unsigned int __inw(unsigned long addr)
293 
{
294 
        register unsigned long result;
295 
 
296 
        __asm__ __volatile__ (
297 
                 "ldwu %0,%1"
298 
                 : "=r" (result)
299 
                 : "m"  (*(unsigned short *)(addr+PYXIS_BW_IO)));
300 
 
301 
        return result;
302 
}
303 
 
304 
extern inline void __outw(unsigned short b, unsigned long addr)
305 
{
306 
        __asm__ __volatile__ (
307 
                 "stw %1,%0\n\t"
308 
                 "mb"
309 
                 : : "m" (*(unsigned short *)(addr+PYXIS_BW_IO)), "r" (b));
310 
}
311 
 
312 
extern inline unsigned int __inl(unsigned long addr)
313 
{
314 
        register unsigned long result;
315 
 
316 
        __asm__ __volatile__ (
317 
                 "ldl %0,%1"
318 
                 : "=r" (result)
319 
                 : "m"  (*(unsigned int *)(addr+PYXIS_BW_IO)));
320 
 
321 
        return result;
322 
}
323 
 
324 
extern inline void __outl(unsigned int b, unsigned long addr)
325 
{
326 
        __asm__ __volatile__ (
327 
                 "stl %1,%0\n\t"
328 
                 "mb"
329 
                 : : "m" (*(unsigned int *)(addr+PYXIS_BW_IO)), "r" (b));
330 
}
331 
 
332 
#define inb(port) __inb((port))
333 
#define inw(port) __inw((port))
334 
#define inl(port) __inl((port))
335 
 
336 
#define outb(x, port) __outb((x),(port))
337 
#define outw(x, port) __outw((x),(port))
338 
#define outl(x, port) __outl((x),(port))
339 
 
340 
#else /* BWIO_REALLY_ENABLED */
341 
 
342 
extern inline unsigned int __inb(unsigned long addr)
343 
{
344 
        long result = *(vuip) ((addr << 5) + PYXIS_IO + 0x00);
345 
        result >>= (addr & 3) * 8;
346 
        return 0xffUL & result;
347 
}
348 
 
349 
extern inline void __outb(unsigned char b, unsigned long addr)
350 
{
351 
        unsigned int w;
352 
 
353 
        asm ("insbl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b));
354 
        *(vuip) ((addr << 5) + PYXIS_IO + 0x00) = w;
355 
        mb();
356 
}
357 
 
358 
extern inline unsigned int __inw(unsigned long addr)
359 
{
360 
        long result = *(vuip) ((addr << 5) + PYXIS_IO + 0x08);
361 
        result >>= (addr & 3) * 8;
362 
        return 0xffffUL & result;
363 
}
364 
 
365 
extern inline void __outw(unsigned short b, unsigned long addr)
366 
{
367 
        unsigned int w;
368 
 
369 
        asm ("inswl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b));
370 
        *(vuip) ((addr << 5) + PYXIS_IO + 0x08) = w;
371 
        mb();
372 
}
373 
 
374 
extern inline unsigned int __inl(unsigned long addr)
375 
{
376 
        return *(vuip) ((addr << 5) + PYXIS_IO + 0x18);
377 
}
378 
 
379 
extern inline void __outl(unsigned int b, unsigned long addr)
380 
{
381 
        *(vuip) ((addr << 5) + PYXIS_IO + 0x18) = b;
382 
        mb();
383 
}
384 
 
385 
#define inb(port) \
386 
(__builtin_constant_p((port))?__inb(port):_inb(port))
387 
 
388 
#define outb(x, port) \
389 
(__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port)))
390 
 
391 
#endif /* BWIO_REALLY_ENABLED */
392 
 
393 
 
394 
/*
395 
 * Memory functions.  64-bit and 32-bit accesses are done through
396 
 * dense memory space, everything else through sparse space.
397 
 *
398 
 * For reading and writing 8 and 16 bit quantities we need to
399 
 * go through one of the three sparse address mapping regions
400 
 * and use the HAE_MEM CSR to provide some bits of the address.
401 
 * The following few routines use only sparse address region 1
402 
 * which gives 1Gbyte of accessible space which relates exactly
403 
 * to the amount of PCI memory mapping *into* system address space.
404 
 * See p 6-17 of the specification but it looks something like this:
405 
 *
406 
 * 21164 Address:
407 
 *
408 
 *          3         2         1
409 
 * 9876543210987654321098765432109876543210
410 
 * 1ZZZZ0.PCI.QW.Address............BBLL
411 
 *
412 
 * ZZ = SBZ
413 
 * BB = Byte offset
414 
 * LL = Transfer length
415 
 *
416 
 * PCI Address:
417 
 *
418 
 * 3         2         1
419 
 * 10987654321098765432109876543210
420 
 * HHH....PCI.QW.Address........ 00
421 
 *
422 
 * HHH = 31:29 HAE_MEM CSR
423 
 *
424 
 */
425 
 
426 
#ifdef BWIO_REALLY_ENABLED
427 
 
428 
extern inline unsigned long __readb(unsigned long addr)
429 
{
430 
        register unsigned long result;
431 
 
432 
        __asm__ __volatile__ (
433 
                 "ldbu %0,%1"
434 
                 : "=r" (result)
435 
                 : "m"  (*(unsigned char *)(addr+PYXIS_BW_MEM)));
436 
 
437 
        return result;
438 
}
439 
 
440 
extern inline unsigned long __readw(unsigned long addr)
441 
{
442 
        register unsigned long result;
443 
 
444 
        __asm__ __volatile__ (
445 
                 "ldwu %0,%1"
446 
                 : "=r" (result)
447 
                 : "m"  (*(unsigned short *)(addr+PYXIS_BW_MEM)));
448 
 
449 
        return result;
450 
}
451 
 
452 
extern inline unsigned long __readl(unsigned long addr)
453 
{
454 
        register unsigned long result;
455 
 
456 
        __asm__ __volatile__ (
457 
                 "ldl %0,%1"
458 
                 : "=r" (result)
459 
                 : "m"  (*(unsigned int *)(addr+PYXIS_BW_MEM)));
460 
 
461 
        return result;
462 
}
463 
 
464 
extern inline void __writeb(unsigned char b, unsigned long addr)
465 
{
466 
        __asm__ __volatile__ (
467 
                 "stb %1,%0\n\t"
468 
                 "mb"
469 
                 : : "m" (*(unsigned char *)(addr+PYXIS_BW_MEM)), "r" (b));
470 
}
471 
 
472 
extern inline void __writew(unsigned short b, unsigned long addr)
473 
{
474 
        __asm__ __volatile__ (
475 
                 "stw %1,%0\n\t"
476 
                 "mb"
477 
                 : : "m" (*(unsigned short *)(addr+PYXIS_BW_MEM)), "r" (b));
478 
}
479 
 
480 
extern inline void __writel(unsigned int b, unsigned long addr)
481 
{
482 
        __asm__ __volatile__ (
483 
                 "stl %1,%0\n\t"
484 
                 "mb"
485 
                 : : "m" (*(unsigned int *)(addr+PYXIS_BW_MEM)), "r" (b));
486 
}
487 
 
488 
#define readb(addr) __readb((addr))
489 
#define readw(addr) __readw((addr))
490 
 
491 
#define writeb(b, addr) __writeb((b),(addr))
492 
#define writew(b, addr) __writew((b),(addr))
493 
 
494 
#else /* BWIO_REALLY_ENABLED */
495 
 
496 
#ifdef CONFIG_ALPHA_SRM_SETUP
497 
 
498 
extern unsigned long pyxis_sm_base_r1, pyxis_sm_base_r2, pyxis_sm_base_r3;
499 
 
500 
extern inline unsigned long __readb(unsigned long addr)
501 
{
502 
        unsigned long result, shift, work;
503 
 
504 
        if ((addr >= pyxis_sm_base_r1) &&
505 
            (addr <= (pyxis_sm_base_r1 + MEM_R1_MASK)))
506 
          work = (((addr & MEM_R1_MASK) << 5) + PYXIS_SPARSE_MEM + 0x00);
507 
        else
508 
        if ((addr >= pyxis_sm_base_r2) &&
509 
            (addr <= (pyxis_sm_base_r2 + MEM_R2_MASK)))
510 
          work = (((addr & MEM_R2_MASK) << 5) + PYXIS_SPARSE_MEM_R2 + 0x00);
511 
        else
512 
        if ((addr >= pyxis_sm_base_r3) &&
513 
            (addr <= (pyxis_sm_base_r3 + MEM_R3_MASK)))
514 
          work = (((addr & MEM_R3_MASK) << 5) + PYXIS_SPARSE_MEM_R3 + 0x00);
515 
        else
516 
        {
517 
#if 0
518 
          printk("__readb: address 0x%lx not covered by HAE\n", addr);
519 
#endif
520 
          return 0x0ffUL;
521 
        }
522 
        shift = (addr & 0x3) << 3;
523 
        result = *(vuip) work;
524 
        result >>= shift;
525 
        return 0x0ffUL & result;
526 
}
527 
 
528 
extern inline unsigned long __readw(unsigned long addr)
529 
{
530 
        unsigned long result, shift, work;
531 
 
532 
        if ((addr >= pyxis_sm_base_r1) &&
533 
            (addr <= (pyxis_sm_base_r1 + MEM_R1_MASK)))
534 
          work = (((addr & MEM_R1_MASK) << 5) + PYXIS_SPARSE_MEM + 0x08);
535 
        else
536 
        if ((addr >= pyxis_sm_base_r2) &&
537 
            (addr <= (pyxis_sm_base_r2 + MEM_R2_MASK)))
538 
          work = (((addr & MEM_R2_MASK) << 5) + PYXIS_SPARSE_MEM_R2 + 0x08);
539 
        else
540 
        if ((addr >= pyxis_sm_base_r3) &&
541 
            (addr <= (pyxis_sm_base_r3 + MEM_R3_MASK)))
542 
          work = (((addr & MEM_R3_MASK) << 5) + PYXIS_SPARSE_MEM_R3 + 0x08);
543 
        else
544 
        {
545 
#if 0
546 
          printk("__readw: address 0x%lx not covered by HAE\n", addr);
547 
#endif
548 
          return 0x0ffUL;
549 
        }
550 
        shift = (addr & 0x3) << 3;
551 
        result = *(vuip) work;
552 
        result >>= shift;
553 
        return 0x0ffffUL & result;
554 
}
555 
 
556 
extern inline void __writeb(unsigned char b, unsigned long addr)
557 
{
558 
        unsigned long work;
559 
 
560 
        if ((addr >= pyxis_sm_base_r1) &&
561 
            (addr <= (pyxis_sm_base_r1 + MEM_R1_MASK)))
562 
          work = (((addr & MEM_R1_MASK) << 5) + PYXIS_SPARSE_MEM + 0x00);
563 
        else
564 
        if ((addr >= pyxis_sm_base_r2) &&
565 
            (addr <= (pyxis_sm_base_r2 + MEM_R2_MASK)))
566 
          work = (((addr & MEM_R2_MASK) << 5) + PYXIS_SPARSE_MEM_R2 + 0x00);
567 
        else
568 
        if ((addr >= pyxis_sm_base_r3) &&
569 
            (addr <= (pyxis_sm_base_r3 + MEM_R3_MASK)))
570 
          work = (((addr & MEM_R3_MASK) << 5) + PYXIS_SPARSE_MEM_R3 + 0x00);
571 
        else
572 
        {
573 
#if 0
574 
          printk("__writeb: address 0x%lx not covered by HAE\n", addr);
575 
#endif
576 
          return;
577 
        }
578 
        *(vuip) work = b * 0x01010101;
579 
}
580 
 
581 
extern inline void __writew(unsigned short b, unsigned long addr)
582 
{
583 
        unsigned long work;
584 
 
585 
        if ((addr >= pyxis_sm_base_r1) &&
586 
            (addr <= (pyxis_sm_base_r1 + MEM_R1_MASK)))
587 
          work = (((addr & MEM_R1_MASK) << 5) + PYXIS_SPARSE_MEM + 0x00);
588 
        else
589 
        if ((addr >= pyxis_sm_base_r2) &&
590 
            (addr <= (pyxis_sm_base_r2 + MEM_R2_MASK)))
591 
          work = (((addr & MEM_R2_MASK) << 5) + PYXIS_SPARSE_MEM_R2 + 0x00);
592 
        else
593 
        if ((addr >= pyxis_sm_base_r3) &&
594 
            (addr <= (pyxis_sm_base_r3 + MEM_R3_MASK)))
595 
          work = (((addr & MEM_R3_MASK) << 5) + PYXIS_SPARSE_MEM_R3 + 0x00);
596 
        else
597 
        {
598 
#if 0
599 
          printk("__writew: address 0x%lx not covered by HAE\n", addr);
600 
#endif
601 
          return;
602 
        }
603 
        *(vuip) work = b * 0x00010001;
604 
}
605 
 
606 
#else /* SRM_SETUP */
607 
 
608 
extern inline unsigned long __readb(unsigned long addr)
609 
{
610 
        unsigned long result, shift, msb, work, temp;
611 
 
612 
        shift = (addr & 0x3) << 3;
613 
        msb = addr & 0xE0000000UL;
614 
        temp = addr & MEM_R1_MASK ;
615 
        if (msb != hae.cache) {
616 
          set_hae(msb);
617 
        }
618 
        work = ((temp << 5) + PYXIS_SPARSE_MEM + 0x00);
619 
        result = *(vuip) work;
620 
        result >>= shift;
621 
        return 0x0ffUL & result;
622 
}
623 
 
624 
extern inline unsigned long __readw(unsigned long addr)
625 
{
626 
        unsigned long result, shift, msb, work, temp;
627 
 
628 
        shift = (addr & 0x3) << 3;
629 
        msb = addr & 0xE0000000UL;
630 
        temp = addr & MEM_R1_MASK ;
631 
        if (msb != hae.cache) {
632 
          set_hae(msb);
633 
        }
634 
        work = ((temp << 5) + PYXIS_SPARSE_MEM + 0x08);
635 
        result = *(vuip) work;
636 
        result >>= shift;
637 
        return 0x0ffffUL & result;
638 
}
639 
 
640 
extern inline void __writeb(unsigned char b, unsigned long addr)
641 
{
642 
        unsigned long msb ;
643 
 
644 
        msb = addr & 0xE0000000 ;
645 
        addr &= MEM_R1_MASK ;
646 
        if (msb != hae.cache) {
647 
          set_hae(msb);
648 
        }
649 
        *(vuip) ((addr << 5) + PYXIS_SPARSE_MEM + 0x00) = b * 0x01010101;
650 
}
651 
 
652 
extern inline void __writew(unsigned short b, unsigned long addr)
653 
{
654 
        unsigned long msb ;
655 
 
656 
        msb = addr & 0xE0000000 ;
657 
        addr &= MEM_R1_MASK ;
658 
        if (msb != hae.cache) {
659 
          set_hae(msb);
660 
        }
661 
        *(vuip) ((addr << 5) + PYXIS_SPARSE_MEM + 0x08) = b * 0x00010001;
662 
}
663 
#endif /* SRM_SETUP */
664 
 
665 
extern inline unsigned long __readl(unsigned long addr)
666 
{
667 
        return *(vuip) (addr + PYXIS_DENSE_MEM);
668 
}
669 
 
670 
extern inline void __writel(unsigned int b, unsigned long addr)
671 
{
672 
        *(vuip) (addr + PYXIS_DENSE_MEM) = b;
673 
}
674 
 
675 
#endif /* BWIO_REALLY_ENABLED */
676 
 
677 
#define readl(a)        __readl((unsigned long)(a))
678 
#define writel(v,a)     __writel((v),(unsigned long)(a))
679 
 
680 
#undef vuip
681 
 
682 
extern unsigned long pyxis_init (unsigned long mem_start,
683 
                                 unsigned long mem_end);
684 
 
685 
#endif /* __KERNEL__ */
686 
 
687 
/*
688 
 * Data structure for handling PYXIS machine checks:
689 
 */
690 
struct el_PYXIS_sysdata_mcheck {
691 
    u_long      coma_gcr;
692 
    u_long      coma_edsr;
693 
    u_long      coma_ter;
694 
    u_long      coma_elar;
695 
    u_long      coma_ehar;
696 
    u_long      coma_ldlr;
697 
    u_long      coma_ldhr;
698 
    u_long      coma_base0;
699 
    u_long      coma_base1;
700 
    u_long      coma_base2;
701 
    u_long      coma_cnfg0;
702 
    u_long      coma_cnfg1;
703 
    u_long      coma_cnfg2;
704 
    u_long      epic_dcsr;
705 
    u_long      epic_pear;
706 
    u_long      epic_sear;
707 
    u_long      epic_tbr1;
708 
    u_long      epic_tbr2;
709 
    u_long      epic_pbr1;
710 
    u_long      epic_pbr2;
711 
    u_long      epic_pmr1;
712 
    u_long      epic_pmr2;
713 
    u_long      epic_harx1;
714 
    u_long      epic_harx2;
715 
    u_long      epic_pmlt;
716 
    u_long      epic_tag0;
717 
    u_long      epic_tag1;
718 
    u_long      epic_tag2;
719 
    u_long      epic_tag3;
720 
    u_long      epic_tag4;
721 
    u_long      epic_tag5;
722 
    u_long      epic_tag6;
723 
    u_long      epic_tag7;
724 
    u_long      epic_data0;
725 
    u_long      epic_data1;
726 
    u_long      epic_data2;
727 
    u_long      epic_data3;
728 
    u_long      epic_data4;
729 
    u_long      epic_data5;
730 
    u_long      epic_data6;
731 
    u_long      epic_data7;
732 
};
733 
 
734 
#define RTC_PORT(x)     (0x70 + (x))
735 
#define RTC_ADDR(x)     (0x80 | (x))
736 
#ifdef CONFIG_ALPHA_RUFFIAN
737 
#define RTC_ALWAYS_BCD 1
738 
#else /* RUFFIAN */
739 
#define RTC_ALWAYS_BCD 0
740 
#endif /* RUFFIAN */
741 
 
742 
#endif /* __ALPHA_PYXIS__H__ */

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