| 1 |
199 |
simons |
/****************************************************************************/
|
| 2 |
|
|
|
| 3 |
|
|
/*
|
| 4 |
|
|
* mcfsim.h -- ColdFire System Integration Module support.
|
| 5 |
|
|
*
|
| 6 |
|
|
* (C) Copyright 1999, Greg Ungerer (gerg@moreton.com.au)
|
| 7 |
|
|
*/
|
| 8 |
|
|
|
| 9 |
|
|
/****************************************************************************/
|
| 10 |
|
|
#ifndef mcfsim_h
|
| 11 |
|
|
#define mcfsim_h
|
| 12 |
|
|
/****************************************************************************/
|
| 13 |
|
|
|
| 14 |
|
|
#include <linux/config.h>
|
| 15 |
|
|
|
| 16 |
|
|
/*
|
| 17 |
|
|
* Include 5206 or 5307 specific addresses.
|
| 18 |
|
|
*/
|
| 19 |
|
|
#if defined(CONFIG_M5206) || defined(CONFIG_M5206e)
|
| 20 |
|
|
#include <asm/m5206sim.h>
|
| 21 |
|
|
#elif defined(CONFIG_M5204)
|
| 22 |
|
|
#include <asm/m5204sim.h>
|
| 23 |
|
|
#elif defined(CONFIG_M5307)
|
| 24 |
|
|
#include <asm/m5307sim.h>
|
| 25 |
|
|
#endif
|
| 26 |
|
|
|
| 27 |
|
|
|
| 28 |
|
|
/*
|
| 29 |
|
|
* Define the base address of the SIM within the MBAR address space.
|
| 30 |
|
|
*/
|
| 31 |
|
|
#define MCFSIM_BASE 0x0 /* Base address of SIM */
|
| 32 |
|
|
|
| 33 |
|
|
|
| 34 |
|
|
/*
|
| 35 |
|
|
* Bit definitions for the ICR family of registers.
|
| 36 |
|
|
*/
|
| 37 |
|
|
#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
|
| 38 |
|
|
#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
|
| 39 |
|
|
#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
|
| 40 |
|
|
#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
|
| 41 |
|
|
#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
|
| 42 |
|
|
#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
|
| 43 |
|
|
#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
|
| 44 |
|
|
#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
|
| 45 |
|
|
#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
|
| 46 |
|
|
|
| 47 |
|
|
#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
|
| 48 |
|
|
#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
|
| 49 |
|
|
#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
|
| 50 |
|
|
#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
|
| 51 |
|
|
|
| 52 |
|
|
/*
|
| 53 |
|
|
* Bit definitions for the Interrupt Mask register (IMR).
|
| 54 |
|
|
*/
|
| 55 |
|
|
#define MCFSIM_IMR_EINT1 0x0002 /* External intr # 1 */
|
| 56 |
|
|
#define MCFSIM_IMR_EINT2 0x0004 /* External intr # 2 */
|
| 57 |
|
|
#define MCFSIM_IMR_EINT3 0x0008 /* External intr # 3 */
|
| 58 |
|
|
#define MCFSIM_IMR_EINT4 0x0010 /* External intr # 4 */
|
| 59 |
|
|
#define MCFSIM_IMR_EINT5 0x0020 /* External intr # 5 */
|
| 60 |
|
|
#define MCFSIM_IMR_EINT6 0x0040 /* External intr # 6 */
|
| 61 |
|
|
#define MCFSIM_IMR_EINT7 0x0080 /* External intr # 7 */
|
| 62 |
|
|
|
| 63 |
|
|
#define MCFSIM_IMR_SWD 0x0100 /* Software Watchdog intr */
|
| 64 |
|
|
#define MCFSIM_IMR_TIMER1 0x0200 /* TIMER 1 intr */
|
| 65 |
|
|
#define MCFSIM_IMR_TIMER2 0x0400 /* TIMER 2 intr */
|
| 66 |
|
|
#define MCFSIM_IMR_MBUS 0x0800 /* MBUS intr */
|
| 67 |
|
|
#define MCFSIM_IMR_UART1 0x1000 /* UART 1 intr */
|
| 68 |
|
|
#define MCFSIM_IMR_UART2 0x2000 /* UART 2 intr */
|
| 69 |
|
|
|
| 70 |
|
|
#if defined(CONFIG_M5206e)
|
| 71 |
|
|
#define MCFSIM_IMR_DMA1 0x4000 /* DMA 1 intr */
|
| 72 |
|
|
#define MCFSIM_IMR_DMA2 0x8000 /* DMA 2 intr */
|
| 73 |
|
|
#elif defined(CONFIG_M5307)
|
| 74 |
|
|
#define MCFSIM_IMR_DMA0 0x4000 /* DMA 0 intr */
|
| 75 |
|
|
#define MCFSIM_IMR_DMA1 0x8000 /* DMA 1 intr */
|
| 76 |
|
|
#define MCFSIM_IMR_DMA2 0x10000 /* DMA 2 intr */
|
| 77 |
|
|
#define MCFSIM_IMR_DMA3 0x20000 /* DMA 3 intr */
|
| 78 |
|
|
#endif
|
| 79 |
|
|
|
| 80 |
|
|
#if defined(CONFIG_M5307)
|
| 81 |
|
|
#define MCFSIM_IMR_MASKALL 0x3fffe /* All intr sources */
|
| 82 |
|
|
#elif defined(CONFIG_M5206e)
|
| 83 |
|
|
#define MCFSIM_IMR_MASKALL 0xfffe /* All intr sources */
|
| 84 |
|
|
#else
|
| 85 |
|
|
#define MCFSIM_IMR_MASKALL 0x3ffe /* All intr sources */
|
| 86 |
|
|
#endif
|
| 87 |
|
|
|
| 88 |
|
|
/****************************************************************************/
|
| 89 |
|
|
#endif /* mcfsim_h */
|
