OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [uclinux/] [uClinux-2.0.x/] [include/] [asm-m68knommu/] [mcfuart.h] - Blame information for rev 1765

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 199 simons 
/****************************************************************************/
2 
 
3 
/*
4 
 *      mcfuart.h -- ColdFire internal UART support defines.
5 
 *
6 
 *      (C) Copyright 1999, Greg Ungerer (gerg@moreton.com.au)
7 
 */
8 
 
9 
/****************************************************************************/
10 
#ifndef mcfuart_h
11 
#define mcfuart_h
12 
/****************************************************************************/
13 
 
14 
#include <linux/config.h>
15 
 
16 
/*
17 
 *      Define the base address of the UARTS within the MBAR address
18 
 *      space.
19 
 */
20 
#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5204)
21 
#if defined(CONFIG_NETtel)
22 
#define MCFUART_BASE1           0x180           /* Base address of UART1 */
23 
#define MCFUART_BASE2           0x140           /* Base address of UART2 */
24 
#else
25 
#define MCFUART_BASE1           0x140           /* Base address of UART1 */
26 
#define MCFUART_BASE2           0x180           /* Base address of UART2 */
27 
#endif
28 
#elif defined(CONFIG_M5307)
29 
#if defined(CONFIG_NETtel) || defined(CONFIG_MATtel)
30 
#define MCFUART_BASE1           0x200           /* Base address of UART1 */
31 
#define MCFUART_BASE2           0x1c0           /* Base address of UART2 */
32 
#else
33 
#define MCFUART_BASE1           0x1c0           /* Base address of UART1 */
34 
#define MCFUART_BASE2           0x200           /* Base address of UART2 */
35 
#endif
36 
#endif
37 
 
38 
 
39 
/*
40 
 *      Define the ColdFire UART register set addresses.
41 
 */
42 
#define MCFUART_UMR             0x00            /* Mode register (r/w) */
43 
#define MCFUART_USR             0x04            /* Status register (r) */
44 
#define MCFUART_UCSR            0x04            /* Clock Select (w) */
45 
#define MCFUART_UCR             0x08            /* Command register (w) */
46 
#define MCFUART_URB             0x0c            /* Receiver Buffer (r) */
47 
#define MCFUART_UTB             0x0c            /* Transmit Buffer (w) */
48 
#define MCFUART_UIPCR           0x10            /* Input Port Change (r) */
49 
#define MCFUART_UACR            0x10            /* Auxiliary Control (w) */
50 
#define MCFUART_UISR            0x14            /* Interrup Status (r) */
51 
#define MCFUART_UIMR            0x14            /* Interrupt Mask (w) */
52 
#define MCFUART_UBG1            0x18            /* Baud Rate MSB (r/w) */
53 
#define MCFUART_UBG2            0x1c            /* Baud Rate LSB (r/w) */
54 
#define MCFUART_UIVR            0x30            /* Interrupt Vector (r/w) */
55 
#define MCFUART_UIPR            0x34            /* Input Port (r) */
56 
#define MCFUART_UOP1            0x38            /* Output Port Bit Set (w) */
57 
#define MCFUART_UOP0            0x3c            /* Output Port Bit Reset (w) */
58 
 
59 
 
60 
/*
61 
 *      Define bit flags in Mode Register 1 (MR1).
62 
 */
63 
#define MCFUART_MR1_RXRTS       0x80            /* Auto RTS flow control */
64 
#define MCFUART_MR1_RXIRQFULL   0x40            /* RX IRQ type FULL */
65 
#define MCFUART_MR1_RXIRQRDY    0x00            /* RX IRQ type RDY */
66 
#define MCFUART_MR1_RXERRBLOCK  0x20            /* RX block error mode */
67 
#define MCFUART_MR1_RXERRCHAR   0x00            /* RX char error mode */
68 
 
69 
#define MCFUART_MR1_PARITYNONE  0x10            /* No parity */
70 
#define MCFUART_MR1_PARITYEVEN  0x00            /* Even parity */
71 
#define MCFUART_MR1_PARITYODD   0x04            /* Odd parity */
72 
#define MCFUART_MR1_PARITYSPACE 0x08            /* Space parity */
73 
#define MCFUART_MR1_PARITYMARK  0x06            /* Mark parity */
74 
 
75 
#define MCFUART_MR1_CS5         0x00            /* 5 bits per char */
76 
#define MCFUART_MR1_CS6         0x01            /* 6 bits per char */
77 
#define MCFUART_MR1_CS7         0x02            /* 7 bits per char */
78 
#define MCFUART_MR1_CS8         0x03            /* 8 bits per char */
79 
 
80 
/*
81 
 *      Define bit flags in Mode Register 2 (MR2).
82 
 */
83 
#define MCFUART_MR2_LOOPBACK    0x80            /* Loopback mode */
84 
#define MCFUART_MR2_REMOTELOOP  0xc0            /* Remote loopback mode */
85 
#define MCFUART_MR2_AUTOECHO    0x40            /* Automatic echo */
86 
#define MCFUART_MR2_TXRTS       0x20            /* Assert RTS on TX */
87 
#define MCFUART_MR2_TXCTS       0x10            /* Auto CTS flow control */
88 
 
89 
#define MCFUART_MR2_STOP1       0x07            /* 1 stop bit */
90 
#define MCFUART_MR2_STOP15      0x08            /* 1.5 stop bits */
91 
#define MCFUART_MR2_STOP2       0x0f            /* 2 stop bits */
92 
 
93 
/*
94 
 *      Define bit flags in Status Register (USR).
95 
 */
96 
#define MCFUART_USR_RXBREAK     0x80            /* Received BREAK */
97 
#define MCFUART_USR_RXFRAMING   0x40            /* Received framing error */
98 
#define MCFUART_USR_RXPARITY    0x20            /* Received parity error */
99 
#define MCFUART_USR_RXOVERRUN   0x10            /* Received overrun error */
100 
#define MCFUART_USR_TXEMPTY     0x08            /* Transmitter empty */
101 
#define MCFUART_USR_TXREADY     0x04            /* Transmitter ready */
102 
#define MCFUART_USR_RXFULL      0x02            /* Receiver full */
103 
#define MCFUART_USR_RXREADY     0x01            /* Receiver ready */
104 
 
105 
#define MCFUART_USR_RXERR       (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \
106 
                                MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN)
107 
 
108 
/*
109 
 *      Define bit flags in Clock Select Register (UCSR).
110 
 */
111 
#define MCFUART_UCSR_RXCLKTIMER 0xd0            /* RX clock is timer */
112 
#define MCFUART_UCSR_RXCLKEXT16 0xe0            /* RX clock is external x16 */
113 
#define MCFUART_UCSR_RXCLKEXT1  0xf0            /* RX clock is external x1 */
114 
 
115 
#define MCFUART_UCSR_TXCLKTIMER 0x0d            /* TX clock is timer */
116 
#define MCFUART_UCSR_TXCLKEXT16 0x0e            /* TX clock is external x16 */
117 
#define MCFUART_UCSR_TXCLKEXT1  0x0f            /* TX clock is external x1 */
118 
 
119 
/*
120 
 *      Define bit flags in Command Register (UCR).
121 
 */
122 
#define MCFUART_UCR_CMDNULL             0x00    /* No command */
123 
#define MCFUART_UCR_CMDRESETMRPTR       0x10    /* Reset MR pointer */
124 
#define MCFUART_UCR_CMDRESETRX          0x20    /* Reset receiver */
125 
#define MCFUART_UCR_CMDRESETTX          0x30    /* Reset transmitter */
126 
#define MCFUART_UCR_CMDRESETERR         0x40    /* Reset error status */
127 
#define MCFUART_UCR_CMDRESETBREAK       0x50    /* Reset BREAK change */
128 
#define MCFUART_UCR_CMDBREAKSTART       0x60    /* Start BREAK */
129 
#define MCFUART_UCR_CMDBREAKSTOP        0x70    /* Stop BREAK */
130 
 
131 
#define MCFUART_UCR_TXNULL      0x00            /* No TX command */
132 
#define MCFUART_UCR_TXENABLE    0x04            /* Enable TX */
133 
#define MCFUART_UCR_TXDISABLE   0x08            /* Disable TX */
134 
#define MCFUART_UCR_RXNULL      0x00            /* No RX command */
135 
#define MCFUART_UCR_RXENABLE    0x01            /* Enable RX */
136 
#define MCFUART_UCR_RXDISABLE   0x02            /* Disable RX */
137 
 
138 
/*
139 
 *      Define bit flags in Input Port Change Register (UIPCR).
140 
 */
141 
#define MCFUART_UIPCR_CTSCOS    0x10            /* CTS change of state */
142 
#define MCFUART_UIPCR_CTS       0x01            /* CTS value */
143 
 
144 
/*
145 
 *      Define bit flags in Input Port Register (UIP).
146 
 */
147 
#define MCFUART_UIPR_CTS        0x01            /* CTS value */
148 
 
149 
/*
150 
 *      Define bit flags in Output Port Registers (UOP).
151 
 *      Clear bit by writing to UOP0, set by writing to UOP1.
152 
 */
153 
#define MCFUART_UOP_RTS         0x01            /* RTS set or clear */
154 
 
155 
/*
156 
 *      Define bit flags in the Auxiliary Control Register (UACR).
157 
 */
158 
#define MCFUART_UACR_IEC        0x01            /* Input enable control */
159 
 
160 
/*
161 
 *      Define bit flags in Interrupt Status Register (UISR).
162 
 *      These same bits are used for the Interrupt Mask Register (UIMR).
163 
 */
164 
#define MCFUART_UIR_COS         0x80            /* Change of state (CTS) */
165 
#define MCFUART_UIR_DELTABREAK  0x04            /* Break start or stop */
166 
#define MCFUART_UIR_RXREADY     0x02            /* Receiver ready */
167 
#define MCFUART_UIR_TXREADY     0x01            /* Transmitter ready */
168 
 
169 
/****************************************************************************/
170 
#endif  /* mcfuart_h */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.