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#ifndef __ASM_MIPS_IO_H
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#define __ASM_MIPS_IO_H
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#include <asm/mipsconfig.h>
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#include <asm/segment.h>
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/*
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* This file contains the definitions for the MIPS counterpart of the
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* x86 in/out instructions. This heap of macros and C results in much
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* better code than the approach of doing it in plain C, though that's
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* probably not needed.
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*
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* Ralf
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*
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* This file contains the definitions for the x86 IO instructions
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* inb/inw/inl/outb/outw/outl and the "string versions" of the same
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* (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
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* versions of the single-IO instructions (inb_p/inw_p/..).
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*
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* This file is not meant to be obfuscating: it's just complicated
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* to (a) handle it all in a way that makes gcc able to optimize it
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* as well as possible and (b) trying to avoid writing the same thing
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* over and over again with slight variations and possibly making a
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* mistake somewhere.
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*/
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/*
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* Thanks to James van Artsdalen for a better timing-fix than
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* the two short jumps: using outb's to a nonexistent port seems
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* to guarantee better timings even on fast machines.
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*
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* On the other hand, I'd like to be sure of a non-existent port:
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* I feel a bit unsafe about using 0x80 (should be safe, though)
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*
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* Linus
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*/
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#define __SLOW_DOWN_IO \
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__asm__ __volatile__( \
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"sb\t$0,0x80(%0)" \
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: : "r" (PORT_BASE));
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#ifdef REALLY_SLOW_IO
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#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
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#else
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#define SLOW_DOWN_IO __SLOW_DOWN_IO
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#endif
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/*
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* Change virtual addresses to physical addresses and vv.
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* These are trivial on the 1:1 Linux/MIPS mapping
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*/
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extern inline unsigned long virt_to_phys(volatile void * address)
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{
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return (unsigned long) address - KSEG0;
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}
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extern inline void * phys_to_virt(unsigned long address)
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{
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return (void *) address + KSEG0;
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}
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/*
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* IO bus memory addresses are also 1:1 with the physical address
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* FIXME: This assumption is wrong for the Deskstation Tyne
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*/
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#define virt_to_bus virt_to_phys
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#define bus_to_virt phys_to_virt
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/*
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* readX/writeX() are used to access memory mapped devices. On some
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* architectures the memory mapped IO stuff needs to be accessed
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* differently. On the x86 architecture, we just read/write the
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* memory location directly.
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*/
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#define readb(addr) (*(volatile unsigned char *) (addr))
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#define readw(addr) (*(volatile unsigned short *) (addr))
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#define readl(addr) (*(volatile unsigned int *) (addr))
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#define writeb(b,addr) ((*(volatile unsigned char *) (addr)) = (b))
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#define writew(b,addr) ((*(volatile unsigned short *) (addr)) = (b))
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#define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b))
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#define memset_io(a,b,c) memset((void *)(a),(b),(c))
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#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
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#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
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/*
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* Again, MIPS does not require mem IO specific function.
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*/
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#define eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(void *)(b),(c),(d))
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/*
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* Talk about misusing macros..
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*/
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#define __OUT1(s) \
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extern inline void __out##s(unsigned int value, unsigned int port) {
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#define __OUT2(m) \
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__asm__ __volatile__ ("s" #m "\t%0,%1(%2)"
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#define __OUT(m,s) \
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__OUT1(s) __OUT2(m) : : "r" (value), "i" (0), "r" (PORT_BASE+port)); } \
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__OUT1(s##c) __OUT2(m) : : "r" (value), "ir" (port), "r" (PORT_BASE)); } \
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__OUT1(s##_p) __OUT2(m) : : "r" (value), "i" (0), "r" (PORT_BASE+port)); \
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SLOW_DOWN_IO; } \
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__OUT1(s##c_p) __OUT2(m) : : "r" (value), "ir" (port), "r" (PORT_BASE)); \
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SLOW_DOWN_IO; }
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#define __IN1(t,s) \
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extern __inline__ t __in##s(unsigned int port) { t _v;
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/*
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* Useless nops will be removed by the assembler
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*/
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#define __IN2(m) \
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__asm__ __volatile__ ("l" #m "u\t%0,%1(%2)\n\tnop"
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#define __IN(t,m,s) \
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__IN1(t,s) __IN2(m) : "=r" (_v) : "i" (0), "r" (PORT_BASE+port)); return _v; } \
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__IN1(t,s##c) __IN2(m) : "=r" (_v) : "ir" (port), "r" (PORT_BASE)); return _v; } \
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__IN1(t,s##_p) __IN2(m) : "=r" (_v) : "i" (0), "r" (PORT_BASE+port)); SLOW_DOWN_IO; return _v; } \
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__IN1(t,s##c_p) __IN2(m) : "=r" (_v) : "ir" (port), "r" (PORT_BASE)); SLOW_DOWN_IO; return _v; }
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#define __INS1(s) \
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extern inline void __ins##s(unsigned int port, void * addr, unsigned long count) {
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#define __INS2(m) \
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__asm__ __volatile__ ( \
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".set\tnoreorder\n\t" \
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".set\tnoat\n" \
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"1:\tl" #m "u\t$1,%4(%5)\n\t" \
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"subu\t%1,1\n\t" \
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"s" #m "\t$1,(%0)\n\t" \
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"bne\t$0,%1,1b\n\t" \
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"addiu\t%0,%6\n\t" \
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".set\tat\n\t" \
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".set\treorder"
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#define __INS(m,s,i) \
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__INS1(s) __INS2(m) \
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: "=r" (addr), "=r" (count) \
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: "0" (addr), "1" (count), "i" (0), "r" (PORT_BASE+port), "I" (i) \
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: "$1");} \
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__INS1(s##c) __INS2(m) \
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: "=r" (addr), "=r" (count) \
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: "0" (addr), "1" (count), "ir" (port), "r" (PORT_BASE), "I" (i) \
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: "$1");}
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#define __OUTS1(s) \
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extern inline void __outs##s(unsigned int port, const void * addr, unsigned long count) {
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#define __OUTS2(m) \
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__asm__ __volatile__ ( \
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".set\tnoreorder\n\t" \
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".set\tnoat\n" \
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"1:\tl" #m "u\t$1,(%0)\n\t" \
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"subu\t%1,%1,1\n\t" \
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"s" #m "\t$1,%4(%5)\n\t" \
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"bne\t$0,%1,1b\n\t" \
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"addiu\t%0,%0,%6\n\t" \
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".set\tat\n\t" \
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".set\treorder"
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#define __OUTS(m,s,i) \
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__OUTS1(s) __OUTS2(m) \
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: "=r" (addr), "=r" (count) \
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: "0" (addr), "1" (count), "i" (0), "r" (PORT_BASE+port), "I" (i) \
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: "$1");} \
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__OUTS1(s##c) __OUTS2(m) \
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: "=r" (addr), "=r" (count) \
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: "0" (addr), "1" (count), "ir" (port), "r" (PORT_BASE), "I" (i) \
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: "$1");}
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__IN(unsigned char,b,b)
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__IN(unsigned short,h,w)
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__IN(unsigned int,w,l)
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__OUT(b,b)
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__OUT(h,w)
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__OUT(w,l)
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__INS(b,b,1)
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__INS(h,w,2)
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__INS(w,l,4)
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__OUTS(b,b,1)
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__OUTS(h,w,2)
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__OUTS(w,l,4)
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/*
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* Note that due to the way __builtin_constant_p() works, you
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* - can't use it inside a inline function (it will never be true)
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* - you don't have to worry about side effects within the __builtin..
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*/
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#define outb(val,port) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__outbc((val),(port)) : \
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__outb((val),(port)))
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#define inb(port) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__inbc(port) : \
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__inb(port))
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#define outb_p(val,port) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__outbc_p((val),(port)) : \
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__outb_p((val),(port)))
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#define inb_p(port) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__inbc_p(port) : \
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__inb_p(port))
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#define outw(val,port) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__outwc((val),(port)) : \
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__outw((val),(port)))
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#define inw(port) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__inwc(port) : \
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__inw(port))
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#define outw_p(val,port) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__outwc_p((val),(port)) : \
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__outw_p((val),(port)))
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#define inw_p(port) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__inwc_p(port) : \
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__inw_p(port))
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#define outl(val,port) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__outlc((val),(port)) : \
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__outl((val),(port)))
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#define inl(port) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__inlc(port) : \
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__inl(port))
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#define outl_p(val,port) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__outlc_p((val),(port)) : \
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__outl_p((val),(port)))
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#define inl_p(port) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__inlc_p(port) : \
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__inl_p(port))
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#define outsb(port,addr,count) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__outsbc((port),(addr),(count)) : \
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__outsb ((port),(addr),(count)))
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#define insb(port,addr,count) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__insbc((port),(addr),(count)) : \
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__insb((port),(addr),(count)))
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#define outsw(port,addr,count) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__outswc((port),(addr),(count)) : \
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__outsw ((port),(addr),(count)))
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#define insw(port,addr,count) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__inswc((port),(addr),(count)) : \
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__insw((port),(addr),(count)))
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#define outsl(port,addr,count) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__outslc((port),(addr),(count)) : \
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__outsl ((port),(addr),(count)))
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#define insl(port,addr,count) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__inslc((port),(addr),(count)) : \
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__insl((port),(addr),(count)))
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#endif /* __ASM_MIPS_IO_H */
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