URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [uclinux/] [uClinux-2.0.x/] [include/] [asm-or32/] [traps.h] - Blame information for rev 1765

Details | Compare with Previous | View Log


/*
 *  linux/include/asm/traps.h
 *
 *  Copyright (C) 1993        Hamish Macdonald
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file COPYING in the main directory of this archive
 * for more details.
 */
 
#ifndef _OR32_TRAPS_H
#define _OR32_TRAPS_H
 
typedef void (*e_vector)(void);
 
extern e_vector vectors[];
 
#define VEC_BUSERR  (2)
#define VEC_ADDRERR (3)
#define VEC_ILLEGAL (4)
#define VEC_ZERODIV (5)
#define VEC_CHK     (6)
#define VEC_TRAP    (7)
#define VEC_PRIV    (8)
#define VEC_TRACE   (9)
#define VEC_LINE10  (10)
#define VEC_LINE11  (11)
#define VEC_RESV1   (12)
#define VEC_COPROC  (13)
#define VEC_FORMAT  (14)
#define VEC_UNINT   (15)
 
 
#define VEC_SYS     (32)
#define VEC_TRAP1   (33)
#define VEC_TRAP2   (34)
#define VEC_TRAP3   (35)
#define VEC_TRAP4   (36)
#define VEC_TRAP5   (37)
#define VEC_TRAP6   (38)
#define VEC_TRAP7   (39)
#define VEC_TRAP8   (40)
#define VEC_TRAP9   (41)
#define VEC_TRAP10  (42)
#define VEC_TRAP11  (43)
#define VEC_TRAP12  (44)
#define VEC_TRAP13  (45)
#define VEC_TRAP14  (46)
#define VEC_TRAP15  (47)
#define VEC_FPBRUC  (48)
#define VEC_FPIR    (49)
#define VEC_FPDIVZ  (50)
#define VEC_FPUNDER (51)
#define VEC_FPOE    (52)
#define VEC_FPOVER  (53)
#define VEC_FPNAN   (54)
#define VEC_FPUNSUP (55)
#define VEC_UNIMPEA (60)
#define VEC_UNIMPII (61)
 
#define VEC_SPUR    (64)
#define VEC_INT1    (65)
#define VEC_INT2    (66)
#define VEC_INT3    (67)
#define VEC_INT4    (68)
#define VEC_INT5    (69)
#define VEC_INT6    (70)
#define VEC_INT7    (71)
 
#define VECOFF(vec) ((vec)<<2)
 
/* Status register bits */
#define PS_T  (0x8000)
#define PS_S  (0x2000)
#define PS_M  (0x1000)
#define PS_C  (0x0001)
 
/* bits for 68020/68030 special status word */
 
#define FC    (0x8000)
#define FB    (0x4000)
#define RC    (0x2000)
#define RB    (0x1000)
#define DF    (0x0100)
#define RM    (0x0080)
#define RW    (0x0040)
#define SZ    (0x0030)
#define DFC   (0x0007)
 
/* bits for 68030 MMU status register (mmusr,psr) */
 
#define MMU_B        (0x8000)    /* bus error */
#define MMU_L        (0x4000)    /* limit violation */
#define MMU_S        (0x2000)    /* supervisor violation */
#define MMU_WP       (0x0800)    /* write-protected */
#define MMU_I        (0x0400)    /* invalid descriptor */
#define MMU_M        (0x0200)    /* ATC entry modified */
#define MMU_T        (0x0040)    /* transparent translation */
#define MMU_NUM      (0x0007)    /* number of levels traversed */
 
 
/* bits for 68040 special status word */
#define CP_040  (0x8000)
#define CU_040  (0x4000)
#define CT_040  (0x2000)
#define CM_040  (0x1000)
#define MA_040  (0x0800)
#define ATC_040 (0x0400)
#define LK_040  (0x0200)
#define RW_040  (0x0100)
#define SIZ_040 (0x0060)
#define TT_040  (0x0018)
#define TM_040  (0x0007)
 
/* bits for 68040 write back status word */
#define WBV_040   (0x80)
#define WBSIZ_040 (0x60)
#define WBBYT_040 (0x20)
#define WBWRD_040 (0x40)
#define WBLNG_040 (0x00)
#define WBTT_040  (0x18)
#define WBTM_040  (0x07)
 
/* bus access size codes */
#define BA_SIZE_BYTE    (0x20)
#define BA_SIZE_WORD    (0x40)
#define BA_SIZE_LONG    (0x00)
#define BA_SIZE_LINE    (0x60)
 
/* bus access transfer type codes */
#define BA_TT_MOVE16    (0x08)
 
#ifndef NO_MMU
/* bits for 68040 MMU status register (mmusr) */
#define MMU_B_040   (0x0800)
#define MMU_G_040   (0x0400)
#define MMU_S_040   (0x0080)
#define MMU_CM_040  (0x0060)
#define MMU_M_040   (0x0010)
#define MMU_WP_040  (0x0004)
#define MMU_T_040   (0x0002)
#define MMU_R_040   (0x0001)
 
/* bits in the 68060 fault status long word (FSLW) */
#define MMU060_MA       (0x08000000)    /* misaligned */
#define MMU060_LK       (0x02000000)    /* locked transfer */
#define MMU060_RW       (0x01800000)    /* read/write */
# define MMU060_RW_W    (0x00800000)    /* write */
# define MMU060_RW_R    (0x01000000)    /* read */
# define MMU060_RW_RMW  (0x01800000)    /* read/modify/write */
# define MMU060_W               (0x00800000)    /* general write, includes rmw */
#define MMU060_SIZ      (0x00600000)    /* transfer size */
#define MMU060_TT       (0x00180000)    /* transfer type (TT) bits */
#define MMU060_TM       (0x00070000)    /* transfer modifier (TM) bits */
#define MMU060_IO       (0x00008000)    /* instruction or operand */
#define MMU060_PBE      (0x00004000)    /* push buffer bus error */
#define MMU060_SBE      (0x00002000)    /* store buffer bus error */
#define MMU060_PTA      (0x00001000)    /* pointer A fault */
#define MMU060_PTB      (0x00000800)    /* pointer B fault */
#define MMU060_IL       (0x00000400)    /* double indirect descr fault */
#define MMU060_PF       (0x00000200)    /* page fault (invalid descr) */
#define MMU060_SP       (0x00000100)    /* supervisor protection */
#define MMU060_WP       (0x00000080)    /* write protection */
#define MMU060_TWE      (0x00000040)    /* bus error on table search */
#define MMU060_RE       (0x00000020)    /* bus error on read */
#define MMU060_WE       (0x00000010)    /* bus error on write */
#define MMU060_TTR      (0x00000008)    /* error caused by TTR translation */
#define MMU060_BPE      (0x00000004)    /* branch prediction error */
#define MMU060_SEE      (0x00000001)    /* software emulated error */
 
/* cases of missing or invalid descriptors */
#define MMU060_DESC_ERR (MMU060_TWE | MMU060_PTA | MMU060_PTB | \
                                                 MMU060_IL  | MMU060_PF)
/* bits that indicate real errors */
#define MMU060_ERR_BITS (MMU060_PBE | MMU060_SBE | MMU060_DESC_ERR | \
                                                 MMU060_SP  | MMU060_WP  | MMU060_RE | \
                                                 MMU060_WE)
#endif
 
 
/* structure for stack frames */
 
struct frame {
    struct pt_regs ptregs;
    union {
            struct {
                    unsigned long  iaddr;    /* instruction address */
            } fmt2;
            struct {
                    unsigned long  effaddr;  /* effective address */
            } fmt3;
            struct {
                    unsigned long  effaddr;  /* effective address */
                    unsigned long  pc;       /* pc of faulted instr */
            } fmt4;
            struct {
                    unsigned long  effaddr;  /* effective address */
                    unsigned short ssw;      /* special status word */
                    unsigned short wb3s;     /* write back 3 status */
                    unsigned short wb2s;     /* write back 2 status */
                    unsigned short wb1s;     /* write back 1 status */
                    unsigned long  faddr;    /* fault address */
                    unsigned long  wb3a;     /* write back 3 address */
                    unsigned long  wb3d;     /* write back 3 data */
                    unsigned long  wb2a;     /* write back 2 address */
                    unsigned long  wb2d;     /* write back 2 data */
                    unsigned long  wb1a;     /* write back 1 address */
                    unsigned long  wb1dpd0;  /* write back 1 data/push data 0*/
                    unsigned long  pd1;      /* push data 1*/
                    unsigned long  pd2;      /* push data 2*/
                    unsigned long  pd3;      /* push data 3*/
            } fmt7;
            struct {
                    unsigned long  iaddr;    /* instruction address */
                    unsigned short int1[4];  /* internal registers */
            } fmt9;
            struct {
                    unsigned short int1;
                    unsigned short ssw;      /* special status word */
                    unsigned short isc;      /* instruction stage c */
                    unsigned short isb;      /* instruction stage b */
                    unsigned long  daddr;    /* data cycle fault address */
                    unsigned short int2[2];
                    unsigned long  dobuf;    /* data cycle output buffer */
                    unsigned short int3[2];
            } fmta;
            struct {
                    unsigned short int1;
                    unsigned short ssw;     /* special status word */
                    unsigned short isc;     /* instruction stage c */
                    unsigned short isb;     /* instruction stage b */
                    unsigned long  daddr;   /* data cycle fault address */
                    unsigned short int2[2];
                    unsigned long  dobuf;   /* data cycle output buffer */
                    unsigned short int3[4];
                    unsigned long  baddr;   /* stage B address */
                    unsigned short int4[2];
                    unsigned long  dibuf;   /* data cycle input buffer */
                    unsigned short int5[3];
                    unsigned       ver : 4; /* stack frame version # */
                    unsigned       int6:12;
                    unsigned short int7[18];
            } fmtb;
            struct {
                    unsigned long  faddr;   /* faulted address */
                    unsigned long  dbuf;
                    unsigned long  pc;      /* current instruction PC */
                    unsigned short itc;     /* internal transfer count */
                    unsigned       code :2;
                    unsigned       ssr :14; /* special status word */
            } fmtc;
    } un;
};
 
#endif /* _OR32_TRAPS_H */

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [trunk/] [uclinux/] [uClinux-2.0.x/] [include/] [asm-or32/] [traps.h] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	666	simons	`/*`
2			`* linux/include/asm/traps.h`
3			`*`
4			`* Copyright (C) 1993 Hamish Macdonald`
5			`*`
6			`* This file is subject to the terms and conditions of the GNU General Public`
7			`* License. See the file COPYING in the main directory of this archive`
8			`* for more details.`
9			`*/`
10
11			`#ifndef _OR32_TRAPS_H`
12			`#define _OR32_TRAPS_H`
13
14			`typedef void (*e_vector)(void);`
15
16			`extern e_vector vectors[];`
17
18			`#define VEC_BUSERR (2)`
19			`#define VEC_ADDRERR (3)`
20			`#define VEC_ILLEGAL (4)`
21			`#define VEC_ZERODIV (5)`
22			`#define VEC_CHK (6)`
23			`#define VEC_TRAP (7)`
24			`#define VEC_PRIV (8)`
25			`#define VEC_TRACE (9)`
26			`#define VEC_LINE10 (10)`
27			`#define VEC_LINE11 (11)`
28			`#define VEC_RESV1 (12)`
29			`#define VEC_COPROC (13)`
30			`#define VEC_FORMAT (14)`
31			`#define VEC_UNINT (15)`
32
33
34			`#define VEC_SYS (32)`
35			`#define VEC_TRAP1 (33)`
36			`#define VEC_TRAP2 (34)`
37			`#define VEC_TRAP3 (35)`
38			`#define VEC_TRAP4 (36)`
39			`#define VEC_TRAP5 (37)`
40			`#define VEC_TRAP6 (38)`
41			`#define VEC_TRAP7 (39)`
42			`#define VEC_TRAP8 (40)`
43			`#define VEC_TRAP9 (41)`
44			`#define VEC_TRAP10 (42)`
45			`#define VEC_TRAP11 (43)`
46			`#define VEC_TRAP12 (44)`
47			`#define VEC_TRAP13 (45)`
48			`#define VEC_TRAP14 (46)`
49			`#define VEC_TRAP15 (47)`
50			`#define VEC_FPBRUC (48)`
51			`#define VEC_FPIR (49)`
52			`#define VEC_FPDIVZ (50)`
53			`#define VEC_FPUNDER (51)`
54			`#define VEC_FPOE (52)`
55			`#define VEC_FPOVER (53)`
56			`#define VEC_FPNAN (54)`
57			`#define VEC_FPUNSUP (55)`
58			`#define VEC_UNIMPEA (60)`
59			`#define VEC_UNIMPII (61)`
60
61			`#define VEC_SPUR (64)`
62			`#define VEC_INT1 (65)`
63			`#define VEC_INT2 (66)`
64			`#define VEC_INT3 (67)`
65			`#define VEC_INT4 (68)`
66			`#define VEC_INT5 (69)`
67			`#define VEC_INT6 (70)`
68			`#define VEC_INT7 (71)`
69
70			`#define VECOFF(vec) ((vec)<<2)`
71
72			`/* Status register bits */`
73			`#define PS_T (0x8000)`
74			`#define PS_S (0x2000)`
75			`#define PS_M (0x1000)`
76			`#define PS_C (0x0001)`
77
78			`/* bits for 68020/68030 special status word */`
79
80			`#define FC (0x8000)`
81			`#define FB (0x4000)`
82			`#define RC (0x2000)`
83			`#define RB (0x1000)`
84			`#define DF (0x0100)`
85			`#define RM (0x0080)`
86			`#define RW (0x0040)`
87			`#define SZ (0x0030)`
88			`#define DFC (0x0007)`
89
90			`/* bits for 68030 MMU status register (mmusr,psr) */`
91
92			`#define MMU_B (0x8000) /* bus error */`
93			`#define MMU_L (0x4000) /* limit violation */`
94			`#define MMU_S (0x2000) /* supervisor violation */`
95			`#define MMU_WP (0x0800) /* write-protected */`
96			`#define MMU_I (0x0400) /* invalid descriptor */`
97			`#define MMU_M (0x0200) /* ATC entry modified */`
98			`#define MMU_T (0x0040) /* transparent translation */`
99			`#define MMU_NUM (0x0007) /* number of levels traversed */`
100
101
102			`/* bits for 68040 special status word */`
103			`#define CP_040 (0x8000)`
104			`#define CU_040 (0x4000)`
105			`#define CT_040 (0x2000)`
106			`#define CM_040 (0x1000)`
107			`#define MA_040 (0x0800)`
108			`#define ATC_040 (0x0400)`
109			`#define LK_040 (0x0200)`
110			`#define RW_040 (0x0100)`
111			`#define SIZ_040 (0x0060)`
112			`#define TT_040 (0x0018)`
113			`#define TM_040 (0x0007)`
114
115			`/* bits for 68040 write back status word */`
116			`#define WBV_040 (0x80)`
117			`#define WBSIZ_040 (0x60)`
118			`#define WBBYT_040 (0x20)`
119			`#define WBWRD_040 (0x40)`
120			`#define WBLNG_040 (0x00)`
121			`#define WBTT_040 (0x18)`
122			`#define WBTM_040 (0x07)`
123
124			`/* bus access size codes */`
125			`#define BA_SIZE_BYTE (0x20)`
126			`#define BA_SIZE_WORD (0x40)`
127			`#define BA_SIZE_LONG (0x00)`
128			`#define BA_SIZE_LINE (0x60)`
129
130			`/* bus access transfer type codes */`
131			`#define BA_TT_MOVE16 (0x08)`
132
133			`#ifndef NO_MMU`
134			`/* bits for 68040 MMU status register (mmusr) */`
135			`#define MMU_B_040 (0x0800)`
136			`#define MMU_G_040 (0x0400)`
137			`#define MMU_S_040 (0x0080)`
138			`#define MMU_CM_040 (0x0060)`
139			`#define MMU_M_040 (0x0010)`
140			`#define MMU_WP_040 (0x0004)`
141			`#define MMU_T_040 (0x0002)`
142			`#define MMU_R_040 (0x0001)`
143
144			`/* bits in the 68060 fault status long word (FSLW) */`
145			`#define MMU060_MA (0x08000000) /* misaligned */`
146			`#define MMU060_LK (0x02000000) /* locked transfer */`
147			`#define MMU060_RW (0x01800000) /* read/write */`
148			`# define MMU060_RW_W (0x00800000) /* write */`
149			`# define MMU060_RW_R (0x01000000) /* read */`
150			`# define MMU060_RW_RMW (0x01800000) /* read/modify/write */`
151			`# define MMU060_W (0x00800000) /* general write, includes rmw */`
152			`#define MMU060_SIZ (0x00600000) /* transfer size */`
153			`#define MMU060_TT (0x00180000) /* transfer type (TT) bits */`
154			`#define MMU060_TM (0x00070000) /* transfer modifier (TM) bits */`
155			`#define MMU060_IO (0x00008000) /* instruction or operand */`
156			`#define MMU060_PBE (0x00004000) /* push buffer bus error */`
157			`#define MMU060_SBE (0x00002000) /* store buffer bus error */`
158			`#define MMU060_PTA (0x00001000) /* pointer A fault */`
159			`#define MMU060_PTB (0x00000800) /* pointer B fault */`
160			`#define MMU060_IL (0x00000400) /* double indirect descr fault */`
161			`#define MMU060_PF (0x00000200) /* page fault (invalid descr) */`
162			`#define MMU060_SP (0x00000100) /* supervisor protection */`
163			`#define MMU060_WP (0x00000080) /* write protection */`
164			`#define MMU060_TWE (0x00000040) /* bus error on table search */`
165			`#define MMU060_RE (0x00000020) /* bus error on read */`
166			`#define MMU060_WE (0x00000010) /* bus error on write */`
167			`#define MMU060_TTR (0x00000008) /* error caused by TTR translation */`
168			`#define MMU060_BPE (0x00000004) /* branch prediction error */`
169			`#define MMU060_SEE (0x00000001) /* software emulated error */`
170
171			`/* cases of missing or invalid descriptors */`
172			`#define MMU060_DESC_ERR (MMU060_TWE \| MMU060_PTA \| MMU060_PTB \| \`
173			`MMU060_IL \| MMU060_PF)`
174			`/* bits that indicate real errors */`
175			`#define MMU060_ERR_BITS (MMU060_PBE \| MMU060_SBE \| MMU060_DESC_ERR \| \`
176			`MMU060_SP \| MMU060_WP \| MMU060_RE \| \`
177			`MMU060_WE)`
178			`#endif`
179
180
181			`/* structure for stack frames */`
182
183			`struct frame {`
184			`struct pt_regs ptregs;`
185			`union {`
186			`struct {`
187			`unsigned long iaddr; /* instruction address */`
188			`} fmt2;`
189			`struct {`
190			`unsigned long effaddr; /* effective address */`
191			`} fmt3;`
192			`struct {`
193			`unsigned long effaddr; /* effective address */`
194			`unsigned long pc; /* pc of faulted instr */`
195			`} fmt4;`
196			`struct {`
197			`unsigned long effaddr; /* effective address */`
198			`unsigned short ssw; /* special status word */`
199			`unsigned short wb3s; /* write back 3 status */`
200			`unsigned short wb2s; /* write back 2 status */`
201			`unsigned short wb1s; /* write back 1 status */`
202			`unsigned long faddr; /* fault address */`
203			`unsigned long wb3a; /* write back 3 address */`
204			`unsigned long wb3d; /* write back 3 data */`
205			`unsigned long wb2a; /* write back 2 address */`
206			`unsigned long wb2d; /* write back 2 data */`
207			`unsigned long wb1a; /* write back 1 address */`
208			`unsigned long wb1dpd0; /* write back 1 data/push data 0*/`
209			`unsigned long pd1; /* push data 1*/`
210			`unsigned long pd2; /* push data 2*/`
211			`unsigned long pd3; /* push data 3*/`
212			`} fmt7;`
213			`struct {`
214			`unsigned long iaddr; /* instruction address */`
215			`unsigned short int1[4]; /* internal registers */`
216			`} fmt9;`
217			`struct {`
218			`unsigned short int1;`
219			`unsigned short ssw; /* special status word */`
220			`unsigned short isc; /* instruction stage c */`
221			`unsigned short isb; /* instruction stage b */`
222			`unsigned long daddr; /* data cycle fault address */`
223			`unsigned short int2[2];`
224			`unsigned long dobuf; /* data cycle output buffer */`
225			`unsigned short int3[2];`
226			`} fmta;`
227			`struct {`
228			`unsigned short int1;`
229			`unsigned short ssw; /* special status word */`
230			`unsigned short isc; /* instruction stage c */`
231			`unsigned short isb; /* instruction stage b */`
232			`unsigned long daddr; /* data cycle fault address */`
233			`unsigned short int2[2];`
234			`unsigned long dobuf; /* data cycle output buffer */`
235			`unsigned short int3[4];`
236			`unsigned long baddr; /* stage B address */`
237			`unsigned short int4[2];`
238			`unsigned long dibuf; /* data cycle input buffer */`
239			`unsigned short int5[3];`
240			`unsigned ver : 4; /* stack frame version # */`
241			`unsigned int6:12;`
242			`unsigned short int7[18];`
243			`} fmtb;`
244			`struct {`
245			`unsigned long faddr; /* faulted address */`
246			`unsigned long dbuf;`
247			`unsigned long pc; /* current instruction PC */`
248			`unsigned short itc; /* internal transfer count */`
249			`unsigned code :2;`
250			`unsigned ssr :14; /* special status word */`
251			`} fmtc;`
252			`} un;`
253			`};`
254
255			`#endif /* _OR32_TRAPS_H */`