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[/] [or1k/] [trunk/] [xess/] [xsv_cpld/] [syn/] [synplify/] [xsv_cpld.prj] - Blame information for rev 1765

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#-- Synplicity, Inc.
#-- Version 7.0.3
#-- Project file G:\xess\xsv_cpld\syn\synplify\xsv_cpld.prj
#-- Written on Sat Mar 23 20:12:59 2002
 
 
#add_file options
add_file -verilog "../../rtl/verilog/tdm_master_if.v"
add_file -verilog "../../rtl/verilog/xsv_cpld_top.v"
 
#reporting options
 
 
#implementation: "xsv_cpld_1"
impl -add xsv_cpld_1
 
#device options
set_option -technology XC9500
set_option -part XC95108
set_option -package TQ100
set_option -speed_grade -20
 
#compilation/mapping options
set_option -default_enum_encoding sequential
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1
set_option -top_module "xsv_cpld_top"
 
#map options
set_option -frequency 100.000
set_option -fanout_limit 100
set_option -disable_io_insertion 0
 
#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0
 
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
 
#set result format/file last
project -result_file "xsv_cpld_1/xsv_cpld_top.edf"
impl -active "xsv_cpld_1"

Line No.	Rev	Author	Line
1	767	lampret	`#-- Synplicity, Inc.`
2			`#-- Version 7.0.3`
3			`#-- Project file G:\xess\xsv_cpld\syn\synplify\xsv_cpld.prj`
4			`#-- Written on Sat Mar 23 20:12:59 2002`
5
6
7			`#add_file options`
8			`add_file -verilog "../../rtl/verilog/tdm_master_if.v"`
9			`add_file -verilog "../../rtl/verilog/xsv_cpld_top.v"`
10
11			`#reporting options`
12
13
14			`#implementation: "xsv_cpld_1"`
15			`impl -add xsv_cpld_1`
16
17			`#device options`
18			`set_option -technology XC9500`
19			`set_option -part XC95108`
20			`set_option -package TQ100`
21			`set_option -speed_grade -20`
22
23			`#compilation/mapping options`
24			`set_option -default_enum_encoding sequential`
25			`set_option -symbolic_fsm_compiler 1`
26			`set_option -resource_sharing 1`
27			`set_option -top_module "xsv_cpld_top"`
28
29			`#map options`
30			`set_option -frequency 100.000`
31			`set_option -fanout_limit 100`
32			`set_option -disable_io_insertion 0`
33
34			`#simulation options`
35			`set_option -write_verilog 0`
36			`set_option -write_vhdl 0`
37
38			`#automatic place and route (vendor) options`
39			`set_option -write_apr_constraint 1`
40
41			`#set result format/file last`
42			`project -result_file "xsv_cpld_1/xsv_cpld_top.edf"`
43			`impl -active "xsv_cpld_1"`

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[/] [or1k/] [trunk/] [xess/] [xsv_cpld/] [syn/] [synplify/] [xsv_cpld.prj] - Blame information for rev 1765