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OpenRISC Test Application for XESS XSV800 board

===============================================

Introduction

++++++++++++

This is OpenRISC Test Application. It contains OpenRISC 1200 and a set of

OpenCores peripherals. The whole test application SoC (System-on-Chip) is

designed with the XSV board in mind. Peripherals include UART16550, VGA CRT

controller, Audio controller, debug interface, Ethernet 10/100 MAC, SRAM

and Flash controllers. CRT and Audio controller are optimized for XSV

board.

OR1200 is a 32-bit RISC with harvard architecture. For XSV800 board it is

configured with 4/4KB data/instruction caches, no D/I MMU (lack of

BlockRAMs), and with programmable interrupt controller (PIC), MAC unit,

tick timer unit and debug unit.

Right now the whole system runs only at 10MHz. This is because we are

right now focusing on getting functionality working and not optimizing.

Running heavily constrained P&R takes much longer.

Software for this test application consists of:

- ORP (OpenRISC Reference Platform) monitor

- Linux (uClinux 2.0.36)

- OpenRISC GNU Toolchain (ANSI C compiler GCC, debugger etc)

Directory Structure

+++++++++++++++++++

bench: test bench (for simulation verification)

doc: Some of the documentation (more on the OpenCores web)

rtl: Verilog sources of the XSV FPGA SoC

sim: For running simulation

sw: Software example (OR1K GNU toolchain is available from OpenCores web)

syn: Synthesis scripts/constraints for FPGA and ASIC

exo: Download files for XSV800

Simulation

++++++++++

N/A yet.

Synthesis

+++++++++

N/A yet.

XSV800 Programming Procedure

++++++++++++++++++++++++++++

XSV800 board must be configured for 10MHz operation (see XSV documentation

how to set the clock divisor). If you want to use serial UART16550, or if

you want to use OR1K GDB debugger, you will also have to program the CPLD

with the cpld-tdm.svf file.

Make sure you set the divisor first. Download the .exo file. Then download

the .svf file. Turn the power off.

Connect XSV800 board via RS232 cable to your PC, start terminal software.

Set baud rate to 19200, data/parity/stop to 8/N/1. Now you can turn the

power back on and the FPGA will be configured from the flash and the RISC

will start booting.

What will boot depends what software is compiled and merged into the .exo

file. It can be the ORP (OpenRISC Reference Platform) monitor, or Linux,

or something else.

If you have problems downloading the files to the XSV board, please make sure

you first read the XSV manual and check the XESS website and XESS forum.

Want to help?

+++++++++++++

We need companies, universities and individuals to help us in HW and SW areas.

If you want to help, first go to http://www.opencores.org/cores/or1k-new/ and

check the status and TODOs. Also read the documentation.

Subscribe to the openrisc mailing list (and read OpenCores FAQ before you post):

- if you want more information

- if you want to help with the HW design (test application(s), verification of the

OR1200, optimization of OR1200, development of new units etc)

- if you want to develop software

If you want to help in some other area, please subscribe to main opencores

mailing list.

About OpenCores

===============

OpenCores is an organization that developes free, open source soft cores. If

you would like more information, please visit us at http://www.opencores.org.

We invite companies and individuals to help us in our mission. We need

experienced designers to verify and design new cores.

And we need companies and universities to use our existing verified cores in

projects (the whole purpose of OpenCores is to design free cores that someone

will use !).

--

Damjan Lampret, Mar/2002

$Log: not supported by cvs2svn $

Revision 1.1.1.1  2002/03/21 20:47:47  lampret

First import of the "new" XESS XSV environment.