Subversion Repositories or1k-cf

(*

     Memory access unit test harness

     Copyright 2004 Ken Rose

     All rights reserved

*)

environment "/usr/local/Confluence/lib/Logic.cf"

:RegWidth :AddrWidth

:RegFile

RegFile <- import "reg.cf"

RegWidth <- 32

AddrWidth <- 5

{RegFile.T, {VectorInput, "reg_writeport"   1 RegWidth, $}

            {VectorInput, "reg_writeaddr"   2 AddrWidth, $}

            {VectorInput, "reg_writeenable" 3 1, $}

            {VectorInput, "reg_readaddr1"   4 AddrWidth, $}

            {VectorInput, "reg_readaddr2"   5 AddrWidth, $},

            {VectorOutput, "reg_read1"      6 $}

            {VectorOutput, "reg_read2"      7 $}}

{Set, "FileName" "Regfile2x2"}

{Set, "BuildName" "Regfile2x2"}

{Set, "Header" "Regfile2x2"}

{Set, "GenVerilog" true}

{Set, "GenC" true}