OpenCores
URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] [or1k_old/] [tags/] [tn_m001/] [gdb-5.0/] [sim/] [common/] [sim-hw.h] - Blame information for rev 1782

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 106 markom
/* Device definitions.
2
   Copyright (C) 1998 Free Software Foundation, Inc.
3
   Contributed by Cygnus Support.
4
 
5
This file is part of GDB, the GNU debugger.
6
 
7
This program is free software; you can redistribute it and/or modify
8
it under the terms of the GNU General Public License as published by
9
the Free Software Foundation; either version 2, or (at your option)
10
any later version.
11
 
12
This program is distributed in the hope that it will be useful,
13
but WITHOUT ANY WARRANTY; without even the implied warranty of
14
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
GNU General Public License for more details.
16
 
17
You should have received a copy of the GNU General Public License along
18
with this program; if not, write to the Free Software Foundation, Inc.,
19
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
20
 
21
#ifndef SIM_HW_H
22
#define SIM_HW_H
23
 
24
 
25
/* Establish this object */
26
 
27
SIM_RC sim_hw_install
28
(struct sim_state *sd);
29
 
30
 
31
/* Parse a hardware definition */
32
 
33
struct hw *sim_hw_parse
34
(struct sim_state *sd,
35
 const char *fmt,
36
 ...) __attribute__ ((format (printf, 2, 3)));
37
 
38
 
39
/* Print the hardware tree */
40
 
41
void sim_hw_print
42
(struct sim_state *sd,
43
 void (*print) (struct sim_state *, const char *, va_list ap));
44
 
45
 
46
/* Abort the simulation specifying HW as the reason */
47
 
48
void sim_hw_abort
49
(SIM_DESC sd,
50
 struct hw *hw,
51
 const char *fmt,
52
 ...) __attribute__ ((format (printf, 3, 4)));
53
 
54
 
55
 
56
/* CPU: The simulation is running and the current CPU/CIA
57
   initiates a data transfer. */
58
 
59
void sim_cpu_hw_io_read_buffer
60
(sim_cpu *cpu,
61
 sim_cia cia,
62
 struct hw *hw,
63
 void *dest,
64
 int space,
65
 unsigned_word addr,
66
 unsigned nr_bytes);
67
 
68
void sim_cpu_hw_io_write_buffer
69
(sim_cpu *cpu,
70
 sim_cia cia,
71
 struct hw *hw,
72
 const void *source,
73
 int space,
74
 unsigned_word addr,
75
 unsigned nr_bytes);
76
 
77
 
78
 
79
/* SYSTEM: A data transfer is being initiated by the system. */
80
 
81
unsigned sim_hw_io_read_buffer
82
(struct sim_state *sd,
83
 struct hw *hw,
84
 void *dest,
85
 int space,
86
 unsigned_word addr,
87
 unsigned nr_bytes);
88
 
89
unsigned sim_hw_io_write_buffer
90
(struct sim_state *sd,
91
 struct hw *hw,
92
 const void *source,
93
 int space,
94
 unsigned_word addr,
95
 unsigned nr_bytes);
96
 
97
 
98
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.