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[/] [or1k_old/] [trunk/] [binutils/] [binutils-2.16.1/] [opcodes/] [or32-opc.c] - Blame information for rev 1782

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Line No. Rev Author Line
1 1616 phoenix 
/* Table of opcodes for the OpenRISC 1000 ISA.
2 
   Copyright 1990, 1991, 1992, 1993, 2005 Free Software Foundation, Inc.
3 
   Contributed by Damjan Lampret (lampret@opencores.org).
4 
 
5 
This file is part of gen_or1k_isa, or1ksim, GDB and GAS.
6 
 
7 
This program is free software; you can redistribute it and/or modify
8 
it under the terms of the GNU General Public License as published by
9 
the Free Software Foundation; either version 2 of the License, or
10 
(at your option) any later version.
11 
 
12 
This program is distributed in the hope that it will be useful,
13 
but WITHOUT ANY WARRANTY; without even the implied warranty of
14 
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 
GNU General Public License for more details.
16 
 
17 
You should have received a copy of the GNU General Public License
18 
along with this program; if not, write to the Free Software
19 
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
20 
 
21 
/*
22 
 * $Log: not supported by cvs2svn $
23 
 * Revision 1.50  2005/11/18 18:15:21  nogj
24 
 * Execute l.ff1 instruction
25 
 *
26 
 * Revision 1.49  2005/11/06 16:23:07  nogj
27 
 * Fix parsing the destination register
28 
 *
29 
 * Revision 1.48  2005/11/03 19:01:50  lampret
30 
 * Added l.fl1
31 
 *
32 
 * Revision 1.47  2005/09/05 08:47:44  nogj
33 
 * Fix most warnings issued by gcc4
34 
 *
35 
 * Revision 1.46  2005/08/18 22:13:27  phoenix
36 
 * fixed l.maci encoding
37 
 *
38 
 * Revision 1.45  2005/04/27 19:13:13  nogj
39 
 * l.rfe does not have a delay slot.  Don't mark it as such.
40 
 *
41 
 * Revision 1.44  2005/03/31 16:09:57  nogj
42 
 * Implement a dynamic recompiler to speed up the execution
43 
 *
44 
 * Revision 1.43  2005/03/31 16:01:59  nogj
45 
 * Reclasify l.trap and l.sys to be an exception instruction
46 
 *
47 
 * Revision 1.42  2005/03/16 12:25:56  nogj
48 
 * Fix the parameters to the l.ff1/l.maci instructions
49 
 *
50 
 * Revision 1.41  2005/02/09 17:41:03  nogj
51 
 * Mark a simulated cpu address as such, by introducing the new oraddr_t type
52 
 *
53 
 * Revision 1.40  2005/01/27 14:14:13  nogj
54 
 * Remove the global op structure
55 
 *
56 
 * Revision 1.39  2005/01/27 13:35:40  nogj
57 
 *  * Fix generate.c to produce a execgen.c with less warnings.
58 
 *  * Fix the --enable-simple configure option.
59 
 *
60 
 * Revision 1.38  2005/01/27 13:15:50  nogj
61 
 * Mark wich operand is the destination operand in the architechture definition
62 
 *
63 
 * Revision 1.37  2005/01/11 15:41:58  andreje
64 
 * l.ff1 instruction added
65 
 *
66 
 * Revision 1.36  2004/07/22 20:17:23  phoenix
67 
 * removed includes
68 
 *
69 
 * Revision 1.35  2004/07/19 23:07:37  phoenix
70 
 * Gyorgy Jeney: extensive cleanup
71 
 *
72 
 * Revision 1.34  2004/06/27 22:56:48  lampret
73 
 * Updated instruction set descriptions. Changed FP instructions encoding.
74 
 *
75 
 * Revision 1.33  2004/05/09 19:52:31  lampret
76 
 * Changed desciption of the l.cust5 insns
77 
 *
78 
 * Revision 1.31  2003/07/01 19:34:49  csanchez
79 
 * Added support for l.addc instruction.
80 
 *
81 
 * Revision 1.30  2003/01/28 03:49:24  lampret
82 
 * Added cvs log keywords
83 
 *
84 
 */
85 
 
86 
#include <string.h>
87 
#include <stdio.h>
88 
#include <stdlib.h>
89 
#include <ctype.h>
90 
 
91 
 
92 
#ifdef HAVE_CONFIG_H
93 
# include "config.h"
94 
#endif
95 
#ifdef HAS_EXECUTION
96 
# ifdef HAVE_INTTYPES_H
97 
#  include <inttypes.h> /* ...but to get arch.h we need uint{8,16,32}_t... */
98 
# endif
99 
# include "port.h"
100 
# include "arch.h" /* ...but to get abstract.h, we need oraddr_t... */
101 
# include "abstract.h" /* To get struct iqueue_entry... */
102 
# include "debug.h" /* To get debug() */
103 
#endif
104 
#include "opcode/or32.h"
105 
 
106 
/* **INDENT-OFF** */
107 
 
108 
/* We treat all letters the same in encode/decode routines so
109 
   we need to assign some characteristics to them like signess etc.*/
110 
CONST struct or32_letter or32_letters[] =
111 
{
112 
{ 'A', NUM_UNSIGNED },
113 
{ 'B', NUM_UNSIGNED },
114 
{ 'D', NUM_UNSIGNED },
115 
{ 'I', NUM_SIGNED },
116 
{ 'K', NUM_UNSIGNED },
117 
{ 'L', NUM_UNSIGNED },
118 
{ 'N', NUM_SIGNED },
119 
{ '0', NUM_UNSIGNED },
120 
{ '\0', 0 }     /* dummy entry */
121 
};
122 
 
123 
/* Opcode encoding:
124 
   machine[31:30]: first two bits of opcode
125 
                   00 - neither of source operands is GPR
126 
                   01 - second source operand is GPR (rB)
127 
                   10 - first source operand is GPR (rA)
128 
                   11 - both source operands are GPRs (rA and rB)
129 
   machine[29:26]: next four bits of opcode
130 
   machine[25:00]: instruction operands (specific to individual instruction)
131 
 
132 
  Recommendation: irrelevant instruction bits should be set with a value of
133 
  bits in same positions of instruction preceding current instruction in the
134 
  code (when assembling).
135 
*/
136 
 
137 
#ifdef HAS_EXECUTION
138 
# if SIMPLE_EXECUTION
139 
#  define EFN &l_none
140 
#  define EF(func) &(func)
141 
#  define EFI &l_invalid
142 
# elif COMPLEX_EXECUTION
143 
#  define EFN "l_none"
144 
#  define EFI "l_invalid"
145 
#  ifdef __GNUC__
146 
#   define EF(func) #func
147 
#  else
148 
#   define EF(func) "func"
149 
#  endif
150 
# else /* DYNAMIC_EXECUTION */
151 
#  define EFN &l_none
152 
#  define EF(func) &(gen_ ##func)
153 
#  define EFI &gen_l_invalid
154 
# endif
155 
#else /* HAS_EXECUTION */
156 
# define EFN &l_none
157 
# define EF(func) EFN
158 
# define EFI EFN
159 
#endif /* HAS_EXECUTION */
160 
 
161 
CONST struct or32_opcode or32_opcodes[] =
162 
{
163 
 
164 
{ "l.j",       "N",            "00 0x0  NNNNN NNNNN NNNN NNNN NNNN NNNN",
165 
  EF(l_j), OR32_IF_DELAY, it_jump },
166 
{ "l.jal",     "N",            "00 0x1  NNNNN NNNNN NNNN NNNN NNNN NNNN",
167 
  EF(l_jal), OR32_IF_DELAY, it_jump },
168 
{ "l.bnf",     "N",            "00 0x3  NNNNN NNNNN NNNN NNNN NNNN NNNN",
169 
  EF(l_bnf), OR32_IF_DELAY | OR32_R_FLAG, it_branch },
170 
{ "l.bf",      "N",            "00 0x4  NNNNN NNNNN NNNN NNNN NNNN NNNN",
171 
  EF(l_bf), OR32_IF_DELAY | OR32_R_FLAG, it_branch },
172 
{ "l.nop",     "K",            "00 0x5  01--- ----- KKKK KKKK KKKK KKKK",
173 
  EF(l_nop), 0, it_nop },
174 
{ "l.movhi",   "rD,K",         "00 0x6  DDDDD ----0 KKKK KKKK KKKK KKKK",
175 
  EF(l_movhi), 0, it_movimm },
176 
{ "l.macrc",   "rD",           "00 0x6  DDDDD ----1 0000 0000 0000 0000",
177 
  EF(l_macrc), 0, it_mac },
178 
{ "l.sys",     "K",            "00 0x8  00000 00000 KKKK KKKK KKKK KKKK",
179 
  EF(l_sys), 0, it_exception },
180 
{ "l.trap",    "K",            "00 0x8  01000 00000 KKKK KKKK KKKK KKKK",
181 
  EF(l_trap), 0, it_exception },
182 
{ "l.msync",   "",             "00 0x8  10000 00000 0000 0000 0000 0000", EFN,
183 
  0, it_unknown },
184 
{ "l.psync",   "",             "00 0x8  10100 00000 0000 0000 0000 0000", EFN,
185 
  0, it_unknown },
186 
{ "l.csync",   "",             "00 0x8  11000 00000 0000 0000 0000 0000", EFN,
187 
  0, it_unknown },
188 
{ "l.rfe",     "",             "00 0x9  ----- ----- ---- ---- ---- ----",
189 
  EF(l_rfe), 0, it_exception },
190 
{ "lv.all_eq.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0,
191 
  it_unknown },
192 
{ "lv.all_eq.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0,
193 
  it_unknown },
194 
{ "lv.all_ge.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0,
195 
  it_unknown },
196 
{ "lv.all_ge.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0,
197 
  it_unknown },
198 
{ "lv.all_gt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0,
199 
  it_unknown },
200 
{ "lv.all_gt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0,
201 
  it_unknown },
202 
{ "lv.all_le.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0,
203 
  it_unknown },
204 
{ "lv.all_le.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0,
205 
  it_unknown },
206 
{ "lv.all_lt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x8", EFI, 0,
207 
  it_unknown },
208 
{ "lv.all_lt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x9", EFI, 0,
209 
  it_unknown },
210 
{ "lv.all_ne.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0xA", EFI, 0,
211 
  it_unknown },
212 
{ "lv.all_ne.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0xB", EFI, 0,
213 
  it_unknown },
214 
{ "lv.any_eq.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x0", EFI, 0,
215 
  it_unknown },
216 
{ "lv.any_eq.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x1", EFI, 0,
217 
  it_unknown },
218 
{ "lv.any_ge.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x2", EFI, 0,
219 
  it_unknown },
220 
{ "lv.any_ge.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x3", EFI, 0,
221 
  it_unknown },
222 
{ "lv.any_gt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x4", EFI, 0,
223 
  it_unknown },
224 
{ "lv.any_gt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x5", EFI, 0,
225 
  it_unknown },
226 
{ "lv.any_le.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x6", EFI, 0,
227 
  it_unknown },
228 
{ "lv.any_le.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x7", EFI, 0,
229 
  it_unknown },
230 
{ "lv.any_lt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x8", EFI, 0,
231 
  it_unknown },
232 
{ "lv.any_lt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x9", EFI, 0,
233 
  it_unknown },
234 
{ "lv.any_ne.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0xA", EFI, 0,
235 
  it_unknown },
236 
{ "lv.any_ne.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0xB", EFI, 0,
237 
  it_unknown },
238 
{ "lv.add.b",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x0", EFI, 0,
239 
  it_unknown },
240 
{ "lv.add.h",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x1", EFI, 0,
241 
  it_unknown },
242 
{ "lv.adds.b", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x2", EFI, 0,
243 
  it_unknown },
244 
{ "lv.adds.h", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x3", EFI, 0,
245 
  it_unknown },
246 
{ "lv.addu.b", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x4", EFI, 0,
247 
  it_unknown },
248 
{ "lv.addu.h", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x5", EFI, 0,
249 
  it_unknown },
250 
{ "lv.addus.b","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x6", EFI, 0,
251 
  it_unknown },
252 
{ "lv.addus.h","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x7", EFI, 0,
253 
  it_unknown },
254 
{ "lv.and",    "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x8", EFI, 0,
255 
  it_unknown },
256 
{ "lv.avg.b",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x9", EFI, 0,
257 
  it_unknown },
258 
{ "lv.avg.h",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0xA", EFI, 0,
259 
  it_unknown },
260 
{ "lv.cmp_eq.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x0", EFI, 0,
261 
  it_unknown },
262 
{ "lv.cmp_eq.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x1", EFI, 0,
263 
  it_unknown },
264 
{ "lv.cmp_ge.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x2", EFI, 0,
265 
  it_unknown },
266 
{ "lv.cmp_ge.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x3", EFI, 0,
267 
  it_unknown },
268 
{ "lv.cmp_gt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x4", EFI, 0,
269 
  it_unknown },
270 
{ "lv.cmp_gt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x5", EFI, 0,
271 
  it_unknown },
272 
{ "lv.cmp_le.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x6", EFI, 0,
273 
  it_unknown },
274 
{ "lv.cmp_le.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x7", EFI, 0,
275 
  it_unknown },
276 
{ "lv.cmp_lt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x8", EFI, 0,
277 
  it_unknown },
278 
{ "lv.cmp_lt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x9", EFI, 0,
279 
  it_unknown },
280 
{ "lv.cmp_ne.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0xA", EFI, 0,
281 
  it_unknown },
282 
{ "lv.cmp_ne.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0xB", EFI, 0,
283 
  it_unknown },
284 
{ "lv.madds.h","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x4", EFI, 0,
285 
  it_unknown },
286 
{ "lv.max.b",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x5", EFI, 0,
287 
  it_unknown },
288 
{ "lv.max.h",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x6", EFI, 0,
289 
  it_unknown },
290 
{ "lv.merge.b","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x7", EFI, 0,
291 
  it_unknown },
292 
{ "lv.merge.h","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x8", EFI, 0,
293 
  it_unknown },
294 
{ "lv.min.b",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x9", EFI, 0,
295 
  it_unknown },
296 
{ "lv.min.h",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xA", EFI, 0,
297 
  it_unknown },
298 
{ "lv.msubs.h","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xB", EFI, 0,
299 
  it_unknown },
300 
{ "lv.muls.h", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xC", EFI, 0,
301 
  it_unknown },
302 
{ "lv.nand",   "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xD", EFI, 0,
303 
  it_unknown },
304 
{ "lv.nor",    "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xE", EFI, 0,
305 
  it_unknown },
306 
{ "lv.or",     "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xF", EFI, 0,
307 
  it_unknown },
308 
{ "lv.pack.b", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x0", EFI, 0,
309 
  it_unknown },
310 
{ "lv.pack.h", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x1", EFI, 0,
311 
  it_unknown },
312 
{ "lv.packs.b","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x2", EFI, 0,
313 
  it_unknown },
314 
{ "lv.packs.h","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x3", EFI, 0,
315 
  it_unknown },
316 
{ "lv.packus.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x4", EFI, 0,
317 
  it_unknown },
318 
{ "lv.packus.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x5", EFI, 0,
319 
  it_unknown },
320 
{ "lv.perm.n", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x6", EFI, 0,
321 
  it_unknown },
322 
{ "lv.rl.b",   "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x7", EFI, 0,
323 
  it_unknown },
324 
{ "lv.rl.h",   "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x8", EFI, 0,
325 
  it_unknown },
326 
{ "lv.sll.b",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x9", EFI, 0,
327 
  it_unknown },
328 
{ "lv.sll.h",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xA", EFI, 0,
329 
  it_unknown },
330 
{ "lv.sll",    "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xB", EFI, 0,
331 
  it_unknown },
332 
{ "lv.srl.b",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xC", EFI, 0,
333 
  it_unknown },
334 
{ "lv.srl.h",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xD", EFI, 0,
335 
  it_unknown },
336 
{ "lv.sra.b",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xE", EFI, 0,
337 
  it_unknown },
338 
{ "lv.sra.h",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xF", EFI, 0,
339 
  it_unknown },
340 
{ "lv.srl",    "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x0", EFI, 0,
341 
  it_unknown },
342 
{ "lv.sub.b",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x1", EFI, 0,
343 
  it_unknown },
344 
{ "lv.sub.h",  "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x2", EFI, 0,
345 
  it_unknown },
346 
{ "lv.subs.b", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x3", EFI, 0,
347 
  it_unknown },
348 
{ "lv.subs.h", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x4", EFI, 0,
349 
  it_unknown },
350 
{ "lv.subu.b", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x5", EFI, 0,
351 
  it_unknown },
352 
{ "lv.subu.h", "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x6", EFI, 0,
353 
  it_unknown },
354 
{ "lv.subus.b","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x7", EFI, 0,
355 
  it_unknown },
356 
{ "lv.subus.h","rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x8", EFI, 0,
357 
  it_unknown },
358 
{ "lv.unpack.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x9", EFI, 0,
359 
  it_unknown },
360 
{ "lv.unpack.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0xA", EFI, 0,
361 
  it_unknown },
362 
{ "lv.xor",    "rD,rA,rB",     "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0xB", EFI, 0,
363 
  it_unknown },
364 
{ "lv.cust1",  "",             "00 0xA  ----- ----- ---- ---- 0xC ----", EFI, 0,
365 
  it_unknown },
366 
{ "lv.cust2",  "",             "00 0xA  ----- ----- ---- ---- 0xD ----", EFI, 0,
367 
  it_unknown },
368 
{ "lv.cust3",  "",             "00 0xA  ----- ----- ---- ---- 0xE ----", EFI, 0,
369 
  it_unknown },
370 
{ "lv.cust4",  "",             "00 0xA  ----- ----- ---- ---- 0xF ----", EFI, 0,
371 
  it_unknown },
372 
 
373 
{ "l.jr",      "rB",           "01 0x1  ----- ----- BBBB B--- ---- ----",
374 
  EF(l_jr), OR32_IF_DELAY, it_jump },
375 
{ "l.jalr",    "rB",           "01 0x2  ----- ----- BBBB B--- ---- ----",
376 
  EF(l_jalr), OR32_IF_DELAY, it_jump },
377 
{ "l.maci",    "rA,I",         "01 0x3  IIIII AAAAA ---- -III IIII IIII",
378 
  EF(l_mac), 0, it_mac },
379 
{ "l.cust1",   "",             "01 0xC  ----- ----- ---- ---- ---- ----",
380 
  EF(l_cust1), 0, it_unknown },
381 
{ "l.cust2",   "",             "01 0xD  ----- ----- ---- ---- ---- ----",
382 
  EF(l_cust2), 0, it_unknown },
383 
{ "l.cust3",   "",             "01 0xE  ----- ----- ---- ---- ---- ----",
384 
  EF(l_cust3), 0, it_unknown },
385 
{ "l.cust4",   "",             "01 0xF  ----- ----- ---- ---- ---- ----",
386 
  EF(l_cust4), 0, it_unknown },
387 
 
388 
{ "l.ld",      "rD,I(rA)",     "10 0x0  DDDDD AAAAA IIII IIII IIII IIII", EFI,
389 
  0, it_load },
390 
{ "l.lwz",     "rD,I(rA)",     "10 0x1  DDDDD AAAAA IIII IIII IIII IIII",
391 
  EF(l_lwz), 0, it_load },
392 
{ "l.lws",     "rD,I(rA)",     "10 0x2  DDDDD AAAAA IIII IIII IIII IIII", EFI,
393 
  0, it_load },
394 
{ "l.lbz",     "rD,I(rA)",     "10 0x3  DDDDD AAAAA IIII IIII IIII IIII",
395 
  EF(l_lbz), 0, it_load },
396 
{ "l.lbs",     "rD,I(rA)",     "10 0x4  DDDDD AAAAA IIII IIII IIII IIII",
397 
  EF(l_lbs), 0, it_load },
398 
{ "l.lhz",     "rD,I(rA)",     "10 0x5  DDDDD AAAAA IIII IIII IIII IIII",
399 
  EF(l_lhz), 0, it_load },
400 
{ "l.lhs",     "rD,I(rA)",     "10 0x6  DDDDD AAAAA IIII IIII IIII IIII",
401 
  EF(l_lhs), 0, it_load },
402 
 
403 
{ "l.addi",    "rD,rA,I",      "10 0x7  DDDDD AAAAA IIII IIII IIII IIII",
404 
  EF(l_add), OR32_W_FLAG, it_arith },
405 
{ "l.addic",   "rD,rA,I",      "10 0x8  DDDDD AAAAA IIII IIII IIII IIII", EFI,
406 
  0, it_arith },
407 
{ "l.andi",    "rD,rA,K",      "10 0x9  DDDDD AAAAA KKKK KKKK KKKK KKKK",
408 
  EF(l_and), OR32_W_FLAG, it_arith },
409 
{ "l.ori",     "rD,rA,K",      "10 0xA  DDDDD AAAAA KKKK KKKK KKKK KKKK",
410 
  EF(l_or), 0, it_arith },
411 
{ "l.xori",    "rD,rA,I",      "10 0xB  DDDDD AAAAA IIII IIII IIII IIII",
412 
  EF(l_xor), 0, it_arith },
413 
{ "l.muli",    "rD,rA,I",      "10 0xC  DDDDD AAAAA IIII IIII IIII IIII",
414 
  EF(l_mul), 0, it_arith },
415 
{ "l.mfspr",   "rD,rA,K",      "10 0xD  DDDDD AAAAA KKKK KKKK KKKK KKKK",
416 
  EF(l_mfspr), 0, it_move },
417 
{ "l.slli",    "rD,rA,L",      "10 0xE  DDDDD AAAAA ---- ---- 00LL LLLL",
418 
  EF(l_sll), 0, it_shift },
419 
{ "l.srli",    "rD,rA,L",      "10 0xE  DDDDD AAAAA ---- ---- 01LL LLLL",
420 
  EF(l_srl), 0, it_shift },
421 
{ "l.srai",    "rD,rA,L",      "10 0xE  DDDDD AAAAA ---- ---- 10LL LLLL",
422 
  EF(l_sra), 0, it_shift },
423 
{ "l.rori",    "rD,rA,L",      "10 0xE  DDDDD AAAAA ---- ---- 11LL LLLL", EFI,
424 
  0, it_shift },
425 
 
426 
{ "l.sfeqi",   "rA,I",         "10 0xF  00000 AAAAA IIII IIII IIII IIII",
427 
  EF(l_sfeq), OR32_W_FLAG, it_compare },
428 
{ "l.sfnei",   "rA,I",         "10 0xF  00001 AAAAA IIII IIII IIII IIII",
429 
  EF(l_sfne), OR32_W_FLAG, it_compare },
430 
{ "l.sfgtui",  "rA,I",         "10 0xF  00010 AAAAA IIII IIII IIII IIII",
431 
  EF(l_sfgtu), OR32_W_FLAG, it_compare },
432 
{ "l.sfgeui",  "rA,I",         "10 0xF  00011 AAAAA IIII IIII IIII IIII",
433 
  EF(l_sfgeu), OR32_W_FLAG, it_compare },
434 
{ "l.sfltui",  "rA,I",         "10 0xF  00100 AAAAA IIII IIII IIII IIII",
435 
  EF(l_sfltu), OR32_W_FLAG, it_compare },
436 
{ "l.sfleui",  "rA,I",         "10 0xF  00101 AAAAA IIII IIII IIII IIII",
437 
  EF(l_sfleu), OR32_W_FLAG, it_compare },
438 
{ "l.sfgtsi",  "rA,I",         "10 0xF  01010 AAAAA IIII IIII IIII IIII",
439 
  EF(l_sfgts), OR32_W_FLAG, it_compare },
440 
{ "l.sfgesi",  "rA,I",         "10 0xF  01011 AAAAA IIII IIII IIII IIII",
441 
  EF(l_sfges), OR32_W_FLAG, it_compare },
442 
{ "l.sfltsi",  "rA,I",         "10 0xF  01100 AAAAA IIII IIII IIII IIII",
443 
  EF(l_sflts), OR32_W_FLAG, it_compare },
444 
{ "l.sflesi",  "rA,I",         "10 0xF  01101 AAAAA IIII IIII IIII IIII",
445 
  EF(l_sfles), OR32_W_FLAG, it_compare },
446 
 
447 
{ "l.mtspr",   "rA,rB,K",      "11 0x0  KKKKK AAAAA BBBB BKKK KKKK KKKK",
448 
  EF(l_mtspr), 0, it_move },
449 
{ "l.mac",     "rA,rB",        "11 0x1  ----- AAAAA BBBB B--- ---- 0x1",
450 
  EF(l_mac), 0, it_mac },
451 
{ "l.msb",     "rA,rB",        "11 0x1  ----- AAAAA BBBB B--- ---- 0x2",
452 
  EF(l_msb), 0, it_mac },
453 
 
454 
{ "lf.add.s",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x0 0x0",
455 
  EF(lf_add_s), 0, it_float },
456 
{ "lf.sub.s",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x0 0x1",
457 
  EF(lf_sub_s), 0, it_float },
458 
{ "lf.mul.s",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x0 0x2",
459 
  EF(lf_mul_s), 0, it_float },
460 
{ "lf.div.s",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x0 0x3",
461 
  EF(lf_div_s), 0, it_float },
462 
{ "lf.itof.s",  "rD,rA",       "11 0x2  DDDDD AAAAA 0000 0--- 0x0 0x4",
463 
  EF(lf_itof_s), 0, it_float },
464 
{ "lf.ftoi.s",  "rD,rA",       "11 0x2  DDDDD AAAAA 0000 0--- 0x0 0x5",
465 
  EF(lf_ftoi_s), 0, it_float },
466 
{ "lf.rem.s",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x0 0x6",
467 
  EF(lf_rem_s), 0, it_float },
468 
{ "lf.madd.s",  "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x0 0x7",
469 
  EF(lf_madd_s), 0, it_float },
470 
{ "lf.sfeq.s",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x0 0x8",
471 
  EF(lf_sfeq_s), 0, it_float },
472 
{ "lf.sfne.s",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x0 0x9",
473 
  EF(lf_sfne_s), 0, it_float },
474 
{ "lf.sfgt.s",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x0 0xA",
475 
  EF(lf_sfgt_s), 0, it_float },
476 
{ "lf.sfge.s",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x0 0xB",
477 
  EF(lf_sfge_s), 0, it_float },
478 
{ "lf.sflt.s",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x0 0xC",
479 
  EF(lf_sflt_s), 0, it_float },
480 
{ "lf.sfle.s",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x0 0xD",
481 
  EF(lf_sfle_s), 0, it_float },
482 
{ "lf.cust1.s", "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0xD ----", EFI,
483 
  0, it_float },
484 
 
485 
{ "lf.add.d",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0,
486 
  it_float },
487 
{ "lf.sub.d",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0,
488 
  it_float },
489 
{ "lf.mul.d",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0,
490 
  it_float },
491 
{ "lf.div.d",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0,
492 
  it_float },
493 
{ "lf.itof.d",  "rD,rA",       "11 0x2  DDDDD AAAAA 0000 0--- 0x1 0x4", EFI, 0,
494 
  it_float },
495 
{ "lf.ftoi.d",  "rD,rA",       "11 0x2  DDDDD AAAAA 0000 0--- 0x1 0x5", EFI, 0,
496 
  it_float },
497 
{ "lf.rem.d",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0,
498 
  it_float },
499 
{ "lf.madd.d",  "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0,
500 
  it_float },
501 
{ "lf.sfeq.d",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0,
502 
  it_float },
503 
{ "lf.sfne.d",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0,
504 
  it_float },
505 
{ "lf.sfgt.d",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0,
506 
  it_float },
507 
{ "lf.sfge.d",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0,
508 
  it_float },
509 
{ "lf.sflt.d",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0,
510 
  it_float },
511 
{ "lf.sfle.d",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0,
512 
  it_float },
513 
{ "lf.cust1.d", "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0xE ----", EFI, 0,
514 
  it_float },
515 
 
516 
{ "l.sd",      "I(rD),rB",     "11 0x4  IIIII DDDDD BBBB BIII IIII IIII", EFI,
517 
  0, it_store },
518 
{ "l.sw",      "I(rD),rB",     "11 0x5  IIIII DDDDD BBBB BIII IIII IIII",
519 
  EF(l_sw), 0, it_store },
520 
{ "l.sb",      "I(rD),rB",     "11 0x6  IIIII DDDDD BBBB BIII IIII IIII",
521 
  EF(l_sb), 0, it_store },
522 
{ "l.sh",      "I(rD),rB",     "11 0x7  IIIII DDDDD BBBB BIII IIII IIII",
523 
  EF(l_sh), 0, it_store },
524 
 
525 
{ "l.add",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x0",
526 
  EF(l_add), OR32_W_FLAG, it_arith },
527 
{ "l.addc",    "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x1",
528 
  EF(l_addc), OR32_W_FLAG, it_arith },
529 
{ "l.sub",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x2",
530 
  EF(l_sub), 0, it_arith },
531 
{ "l.and",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x3",
532 
  EF(l_and), OR32_W_FLAG, it_arith },
533 
{ "l.or",      "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x4",
534 
  EF(l_or), 0, it_arith },
535 
{ "l.xor",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x5",
536 
  EF(l_xor), 0, it_arith },
537 
{ "l.mul",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-11 ---- 0x6",
538 
  EF(l_mul), 0, it_arith },
539 
 
540 
{ "l.sll",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 00-- 0x8",
541 
  EF(l_sll), 0, it_shift },
542 
{ "l.srl",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 01-- 0x8",
543 
  EF(l_srl), 0, it_shift },
544 
{ "l.sra",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 10-- 0x8",
545 
  EF(l_sra), 0, it_shift },
546 
{ "l.ror",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 11-- 0x8", EFI,
547 
  0, it_shift },
548 
{ "l.div",     "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-11 ---- 0x9",
549 
  EF(l_div), 0, it_arith },
550 
{ "l.divu",    "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-11 ---- 0xA",
551 
  EF(l_divu), 0, it_arith },
552 
{ "l.mulu",    "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-11 ---- 0xB", EFI,
553 
  0, it_arith },
554 
{ "l.extbs",   "rD,rA",     "11 0x8  DDDDD AAAAA ---- --00 01-- 0xC",
555 
  EF(l_extbs), 0, it_move },
556 
{ "l.exths",   "rD,rA",     "11 0x8  DDDDD AAAAA ---- --00 00-- 0xC",
557 
  EF(l_exths), 0, it_move },
558 
{ "l.extws",   "rD,rA",     "11 0x8  DDDDD AAAAA ---- --00 00-- 0xD",
559 
  EF(l_extws), 0, it_move },
560 
{ "l.extbz",   "rD,rA",     "11 0x8  DDDDD AAAAA ---- --00 11-- 0xC",
561 
  EF(l_extbz), 0, it_move },
562 
{ "l.exthz",   "rD,rA",     "11 0x8  DDDDD AAAAA ---- --00 10-- 0xC",
563 
  EF(l_exthz), 0, it_move },
564 
{ "l.extwz",   "rD,rA",     "11 0x8  DDDDD AAAAA ---- --00 01-- 0xD",
565 
  EF(l_extwz), 0, it_move },
566 
{ "l.cmov",    "rD,rA,rB",     "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0xE",
567 
  EF(l_cmov), OR32_R_FLAG, it_move },
568 
{ "l.ff1",     "rD,rA",     "11 0x8  DDDDD AAAAA ---- --00 ---- 0xF",
569 
  EF(l_ff1), 0, it_arith },
570 
{ "l.fl1",     "rD,rA",     "11 0x8  DDDDD AAAAA ---- --01 ---- 0xF", EFI, 0,
571 
  it_arith },
572 
 
573 
{ "l.sfeq",    "rA,rB",        "11 0x9  00000 AAAAA BBBB B--- ---- ----",
574 
  EF(l_sfeq), OR32_W_FLAG, it_compare },
575 
{ "l.sfne",    "rA,rB",        "11 0x9  00001 AAAAA BBBB B--- ---- ----",
576 
  EF(l_sfne), OR32_W_FLAG, it_compare },
577 
{ "l.sfgtu",   "rA,rB",        "11 0x9  00010 AAAAA BBBB B--- ---- ----",
578 
  EF(l_sfgtu), OR32_W_FLAG, it_compare },
579 
{ "l.sfgeu",   "rA,rB",        "11 0x9  00011 AAAAA BBBB B--- ---- ----",
580 
  EF(l_sfgeu), OR32_W_FLAG, it_compare },
581 
{ "l.sfltu",   "rA,rB",        "11 0x9  00100 AAAAA BBBB B--- ---- ----",
582 
  EF(l_sfltu), OR32_W_FLAG, it_compare },
583 
{ "l.sfleu",   "rA,rB",        "11 0x9  00101 AAAAA BBBB B--- ---- ----",
584 
  EF(l_sfleu), OR32_W_FLAG, it_compare },
585 
{ "l.sfgts",   "rA,rB",        "11 0x9  01010 AAAAA BBBB B--- ---- ----",
586 
  EF(l_sfgts), OR32_W_FLAG, it_compare },
587 
{ "l.sfges",   "rA,rB",        "11 0x9  01011 AAAAA BBBB B--- ---- ----",
588 
  EF(l_sfges), OR32_W_FLAG, it_compare },
589 
{ "l.sflts",   "rA,rB",        "11 0x9  01100 AAAAA BBBB B--- ---- ----",
590 
  EF(l_sflts), OR32_W_FLAG, it_compare },
591 
{ "l.sfles",   "rA,rB",        "11 0x9  01101 AAAAA BBBB B--- ---- ----",
592 
  EF(l_sfles), OR32_W_FLAG, it_compare },
593 
 
594 
{ "l.cust5",   "rD,rA,rB,L,K", "11 0xC  DDDDD AAAAA BBBB BLLL LLLK KKKK", EFI,
595 
  0, it_unknown },
596 
{ "l.cust6",   "",             "11 0xD  ----- ----- ---- ---- ---- ----", EFI,
597 
  0, it_unknown },
598 
{ "l.cust7",   "",             "11 0xE  ----- ----- ---- ---- ---- ----", EFI,
599 
  0, it_unknown },
600 
{ "l.cust8",   "",             "11 0xF  ----- ----- ---- ---- ---- ----", EFI,
601 
  0, it_unknown },
602 
 
603 
/* This section should not be defined in or1ksim, since it contains duplicates,
604 
   which would cause machine builder to complain.  */
605 
#ifdef HAS_CUST
606 
{ "l.cust5_1",   "rD",         "11 0xC  DDDDD ----- ---- ---- ---- ----", EFI,
607 
  0, it_unknown },
608 
{ "l.cust5_2",   "rD,rA"   ,   "11 0xC  DDDDD AAAAA ---- ---- ---- ----", EFI,
609 
  0, it_unknown },
610 
{ "l.cust5_3",   "rD,rA,rB",   "11 0xC  DDDDD AAAAA BBBB B--- ---- ----", EFI,
611 
  0, it_unknown },
612 
 
613 
{ "l.cust6_1",   "rD",         "11 0xD  DDDDD ----- ---- ---- ---- ----", EFI,
614 
  0, it_unknown },
615 
{ "l.cust6_2",   "rD,rA"   ,   "11 0xD  DDDDD AAAAA ---- ---- ---- ----", EFI,
616 
  0, it_unknown },
617 
{ "l.cust6_3",   "rD,rA,rB",   "11 0xD  DDDDD AAAAA BBBB B--- ---- ----", EFI,
618 
  0, it_unknown },
619 
 
620 
{ "l.cust7_1",   "rD",         "11 0xE  DDDDD ----- ---- ---- ---- ----", EFI,
621 
  0, it_unknown },
622 
{ "l.cust7_2",   "rD,rA"   ,   "11 0xE  DDDDD AAAAA ---- ---- ---- ----", EFI,
623 
  0, it_unknown },
624 
{ "l.cust7_3",   "rD,rA,rB",   "11 0xE  DDDDD AAAAA BBBB B--- ---- ----", EFI,
625 
  0, it_unknown },
626 
 
627 
{ "l.cust8_1",   "rD",         "11 0xF  DDDDD ----- ---- ---- ---- ----", EFI,
628 
  0, it_unknown },
629 
{ "l.cust8_2",   "rD,rA"   ,   "11 0xF  DDDDD AAAAA ---- ---- ---- ----", EFI,
630 
  0, it_unknown },
631 
{ "l.cust8_3",   "rD,rA,rB",   "11 0xF  DDDDD AAAAA BBBB B--- ---- ----", EFI,
632 
  0, it_unknown },
633 
#endif
634 
 
635 
{ "", "", "", EFI, 0, 0 }  /* Dummy entry, not included in num_opcodes.  This
636 
                            * lets code examine entry i+1 without checking
637 
                            * if we've run off the end of the table.  */
638 
};
639 
 
640 
#undef EFI
641 
#undef EFN
642 
#undef EF
643 
 
644 
/* **INDENT-ON** */
645 
 
646 
/* Define dummy, if debug is not defined.  */
647 
#ifndef HAS_DEBUG
648 
#define debug(l, fmt...) ;
649 
#endif
650 
 
651 
CONST int num_opcodes = ((sizeof(or32_opcodes)) / (sizeof(struct or32_opcode))) - 1;
652 
 
653 
/* Calculates instruction length in bytes. Always 4 for OR32. */
654 
int
655 
insn_len(int insn_index)
656 
{
657 
  insn_index = 0; /* Just to get rid that warning.  */
658 
  return 4;
659 
}
660 
 
661 
/* Is individual insn's operand signed or unsigned? */
662 
int
663 
letter_signed(char l)
664 
{
665 
  CONST struct or32_letter *pletter;
666 
 
667 
  for(pletter = or32_letters; pletter->letter != '\0'; pletter++)
668 
    if (pletter->letter == l)
669 
      return pletter->sign;
670 
 
671 
  printf("letter_signed(%c): Unknown letter.\n", l);
672 
  return 0;
673 
}
674 
 
675 
/* Simple cache for letter ranges */
676 
static int range_cache[256] = {0};
677 
 
678 
/* Number of letters in the individual lettered operand. */
679 
int
680 
letter_range(char l)
681 
{
682 
  CONST struct or32_opcode *pinsn;
683 
  char *enc;
684 
  int range = 0;
685 
 
686 
  /* Is value cached? */
687 
  if ((range = range_cache[(unsigned char)l])) return range;
688 
 
689 
  for(pinsn = or32_opcodes; strlen(pinsn->name); pinsn++)
690 
    {
691 
      if (strchr(pinsn->encoding,l))
692 
        {
693 
          for (enc = pinsn->encoding; *enc != '\0'; enc++)
694 
            if ((*enc == '0') && (*(enc+1) == 'x'))
695 
              enc += 2;
696 
            else if (*enc == l)
697 
              range++;
698 
          return range_cache[(unsigned char)l] = range;
699 
        }
700 
    }
701 
 
702 
  printf("\nABORT: letter_range(%c): Never used letter.\n", l);
703 
  exit(1);
704 
}
705 
 
706 
/* MM: Returns index of given instruction name.  */
707 
int
708 
insn_index (char *insn)
709 
{
710 
  int i, found = -1;
711 
  for (i = 0; i < num_opcodes; i++)
712 
    if (!strcmp (or32_opcodes[i].name, insn))
713 
      {
714 
        found = i;
715 
        break;
716 
      }
717 
  return found;
718 
}
719 
 
720 
/* Returns name of the specified instruction index */
721 
CONST char *
722 
insn_name(int index)
723 
{
724 
  if (index >= 0 && index < num_opcodes)
725 
    return or32_opcodes[index].name;
726 
  else
727 
    return "???";
728 
}
729 
 
730 
#if defined(HAS_EXECUTION) && SIMPLE_EXECUTION
731 
void
732 
l_none(struct iqueue_entry *current)
733 
{
734 
}
735 
#elif defined(HAS_EXECUTION) && DYNAMIC_EXECUTION
736 
void
737 
l_none(struct op_queue *opq, int *param_t, orreg_t *param, int delay_slot)
738 
{
739 
}
740 
#else
741 
void
742 
l_none()
743 
{
744 
}
745 
#endif
746 
 
747 
/*** Finite automata for instruction decoding building code ***/
748 
 
749 
/* Find symbols in encoding.  */
750 
unsigned long
751 
insn_extract(char param_ch, char *enc_initial)
752 
{
753 
  char *enc;
754 
  unsigned long ret = 0;
755 
  unsigned opc_pos = 32;
756 
  for (enc = enc_initial; *enc != '\0'; )
757 
    if ((*enc == '0') && (*(enc+1) == 'x'))
758 
      {
759 
        unsigned long tmp = strtol(enc+2, NULL, 16);
760 
        opc_pos -= 4;
761 
        if (param_ch == '0' || param_ch == '1')
762 
          {
763 
            if (param_ch == '0')
764 
              tmp = 15 - tmp;
765 
            ret |= tmp << opc_pos;
766 
          }
767 
        enc += 3;
768 
      }
769 
    else
770 
      {
771 
        if (*enc == '0' || *enc == '1' || *enc == '-' || isalpha(*enc) )
772 
          {
773 
            opc_pos--;
774 
            if (param_ch == *enc)
775 
              ret |= 1 << opc_pos;
776 
          }
777 
        enc++;
778 
      }
779 
  return ret;
780 
}
781 
 
782 
#define MAX_AUTOMATA_SIZE (1200)
783 
#define MAX_OP_TABLE_SIZE (1200)
784 
#define MAX_LEN           (8)
785 
 
786 
#ifndef MIN
787 
# define MIN(x,y)          ((x) < (y) ? (x) : (y))
788 
#endif
789 
 
790 
unsigned long *automata;
791 
int nuncovered;
792 
int curpass = 0;
793 
 
794 
/* MM: Struct that holds runtime build information about instructions.  */
795 
struct temp_insn_struct *ti;
796 
 
797 
struct insn_op_struct *op_data, **op_start;
798 
 
799 
/* Recursive utility function used to find best match and to build automata.  */
800 
 
801 
static unsigned long *
802 
cover_insn (unsigned long *cur, int pass, unsigned int mask)
803 
{
804 
  int best_first = 0, best_len = 0, i, last_match = -1, ninstr = 0;
805 
  unsigned long cur_mask = mask;
806 
  unsigned long *next;
807 
 
808 
  for (i = 0; i < num_opcodes; i++)
809 
    if (ti[i].in_pass == pass)
810 
      {
811 
        cur_mask &= ti[i].insn_mask;
812 
        ninstr++;
813 
        last_match = i;
814 
      }
815 
 
816 
  debug(8, "%08X %08X\n", mask, cur_mask);
817 
  if (ninstr == 0)
818 
    return 0;
819 
  if (ninstr == 1)
820 
    {
821 
      /* Leaf holds instruction index. */
822 
      debug(8, "%i>I%i %s\n", cur - automata, last_match, or32_opcodes[last_match].name);
823 
      *cur = LEAF_FLAG | last_match;
824 
      cur++;
825 
      nuncovered--;
826 
    } else {
827 
      /* Find longest match.  */
828 
      for (i = 0; i < 32; i++)
829 
        {
830 
          int len;
831 
          for (len = best_len + 1; len < MIN(MAX_LEN, 33 - i); len++)
832 
            {
833 
              unsigned long m = (1UL << ((unsigned long)len)) - 1;
834 
              debug(9, " (%i(%08X & %08X>>%i = %08X, %08X)",len,m, cur_mask, i, (cur_mask >> (unsigned)i), (cur_mask >> (unsigned)i) & m);
835 
              if ((m & (cur_mask >> (unsigned)i)) == m)
836 
                {
837 
                  best_len = len;
838 
                  best_first = i;
839 
                  debug(9, "!");
840 
                }
841 
              else
842 
                break;
843 
            }
844 
        }
845 
      debug(9, "\n");
846 
      if (!best_len)
847 
        {
848 
          fprintf (stderr, "%i instructions match mask 0x%08X:\n", ninstr, mask);
849 
          for (i = 0; i < num_opcodes; i++)
850 
            if (ti[i].in_pass == pass)
851 
              fprintf (stderr, "%s ", or32_opcodes[i].name);
852 
 
853 
          fprintf (stderr, "\n");
854 
          exit (1);
855 
        }
856 
      debug(8, "%i> #### %i << %i (%i) ####\n", cur - automata, best_len, best_first, ninstr);
857 
      *cur = best_first;
858 
      cur++;
859 
      *cur = (1 << best_len) - 1;
860 
      cur++;
861 
      next = cur;
862 
      /* Allocate space for pointers.  */
863 
      cur += 1 << best_len;
864 
      cur_mask = (1 << (unsigned long)best_len) - 1;
865 
 
866 
      for (i = 0; i < (1 << (unsigned long)best_len); i++)
867 
        {
868 
          int j;
869 
          unsigned long *c;
870 
          curpass++;
871 
          for (j = 0; j < num_opcodes; j++)
872 
            if (ti[j].in_pass == pass
873 
                && ((ti[j].insn >> best_first) & cur_mask) == (unsigned long) i
874 
                && ((ti[j].insn_mask >> best_first) & cur_mask) == cur_mask)
875 
              ti[j].in_pass = curpass;
876 
 
877 
          debug(9, "%08X %08X %i\n", mask, cur_mask, best_first);
878 
          c = cover_insn (cur, curpass, mask & (~(cur_mask << best_first)));
879 
          if (c)
880 
            {
881 
              debug(8, "%i> #%X -> %u\n", next - automata, i, cur - automata);
882 
              *next = cur - automata;
883 
              cur = c;
884 
            }
885 
          else
886 
            {
887 
              debug(8, "%i> N/A\n", next - automata);
888 
              *next = 0;
889 
            }
890 
          next++;
891 
        }
892 
    }
893 
  return cur;
894 
}
895 
 
896 
/* Returns number of nonzero bits. */
897 
static int
898 
num_ones (unsigned long value)
899 
{
900 
  int c = 0;
901 
  while (value)
902 
    {
903 
      if (value & 1)
904 
        c++;
905 
      value >>= 1;
906 
    }
907 
  return c;
908 
}
909 
 
910 
/* Utility function, which converts parameters from or32_opcode format to more binary form.
911 
   Parameters are stored in ti struct.  */
912 
 
913 
static struct insn_op_struct *
914 
parse_params (CONST struct or32_opcode *opcode, struct insn_op_struct *cur)
915 
{
916 
  char *args = opcode->args;
917 
  int i, type;
918 
  int num_cur_op = 0;;
919 
 
920 
  i = 0;
921 
  type = 0;
922 
  /* In case we don't have any parameters, we add dummy read from r0.  */
923 
  if (!(*args)) {
924 
    cur->type = OPTYPE_REG | OPTYPE_OP | OPTYPE_LAST;
925 
    cur->data = 0;
926 
    debug(9, "#%08X %08X\n", cur->type, cur->data);
927 
    cur++;
928 
    return cur;
929 
  }
930 
 
931 
  while (*args != '\0')
932 
    {
933 
      if (*args == 'r')
934 
        {
935 
          args++;
936 
          type |= OPTYPE_REG;
937 
          if(*args == 'D')
938 
            type |= OPTYPE_DST;
939 
        }
940 
      else if (isalpha (*args))
941 
        {
942 
          unsigned long arg;
943 
          arg = insn_extract(*args, opcode->encoding);
944 
          debug(9, "%s : %08X ------\n", opcode->name, arg);
945 
          if (letter_signed (*args))
946 
            {
947 
              type |= OPTYPE_SIG;
948 
              type |= ((num_ones (arg) - 1) << OPTYPE_SBIT_SHR) & OPTYPE_SBIT;
949 
            }
950 
 
951 
          num_cur_op = 0;
952 
          /* Split argument to sequences of consecutive ones.  */
953 
          while (arg)
954 
            {
955 
              int shr = 0;
956 
              unsigned long tmp = arg, mask = 0;
957 
              while ((tmp & 1) == 0)
958 
                {
959 
                  shr++;
960 
                  tmp >>= 1;
961 
                }
962 
              while (tmp & 1)
963 
                {
964 
                  mask++;
965 
                  tmp >>= 1;
966 
                }
967 
              cur->type = type | shr;
968 
              cur->data = mask;
969 
              arg &= ~(((1 << mask) - 1) << shr);
970 
              debug(6, "|%08X %08X\n", cur->type, cur->data);
971 
              cur++;
972 
              num_cur_op++;
973 
            }
974 
          args++;
975 
        }
976 
      else if (*args == '(')
977 
        {
978 
          /* Next param is displacement.  Later we will treat them as one operand.  */
979 
          /* Set the OPTYPE_DIS flag on all insn_op_structs that belong to this
980 
           * operand */
981 
          while(num_cur_op > 0) {
982 
            cur[-num_cur_op].type |= type | OPTYPE_DIS;
983 
            num_cur_op--;
984 
          }
985 
          cur[-1].type |= OPTYPE_OP;
986 
          debug(9, ">%08X %08X\n", cur->type, cur->data);
987 
          type = 0;
988 
          i++;
989 
          args++;
990 
        }
991 
      else if (*args == OPERAND_DELIM)
992 
        {
993 
          cur--;
994 
          cur->type = type | cur->type | OPTYPE_OP;
995 
          debug(9, ">%08X %08X\n", cur->type, cur->data);
996 
          cur++;
997 
          type = 0;
998 
          i++;
999 
          args++;
1000 
        }
1001 
      else if (*args == '0')
1002 
        {
1003 
          cur->type = type;
1004 
          cur->data = 0;
1005 
          debug(9, ">%08X %08X\n", cur->type, cur->data);
1006 
          cur++;
1007 
          type = 0;
1008 
          i++;
1009 
          args++;
1010 
        }
1011 
      else if (*args == ')')
1012 
        args++;
1013 
      else
1014 
        {
1015 
          fprintf (stderr, "%s : parse error in args.\n", opcode->name);
1016 
          exit (1);
1017 
        }
1018 
    }
1019 
  cur--;
1020 
  cur->type = type | cur->type | OPTYPE_OP | OPTYPE_LAST;
1021 
  debug(9, "#%08X %08X\n", cur->type, cur->data);
1022 
  cur++;
1023 
  return cur;
1024 
}
1025 
 
1026 
/* Constructs new automata based on or32_opcodes array.  */
1027 
 
1028 
void
1029 
build_automata()
1030 
{
1031 
  int i;
1032 
  unsigned long *end;
1033 
  struct insn_op_struct *cur;
1034 
 
1035 
  automata = (unsigned long *) malloc (MAX_AUTOMATA_SIZE * sizeof (unsigned long));
1036 
  ti = (struct temp_insn_struct *) malloc (sizeof (struct temp_insn_struct) * num_opcodes);
1037 
 
1038 
  nuncovered = num_opcodes;
1039 
 
1040 
#ifdef HAS_EXECUTION
1041 
  printf("Building automata... ");
1042 
#endif
1043 
 
1044 
  /* Build temporary information about instructions.  */
1045 
  for (i = 0; i < num_opcodes; i++)
1046 
    {
1047 
      unsigned long ones, zeros;
1048 
      char *encoding = or32_opcodes[i].encoding;
1049 
      ones  = insn_extract('1', encoding);
1050 
      zeros = insn_extract('0', encoding);
1051 
      ti[i].insn_mask = ones | zeros;
1052 
      ti[i].insn = ones;
1053 
      ti[i].in_pass = curpass = 0;
1054 
      /*debug(9, "%s: %s %08X %08X\n", or32_opcodes[i].name,
1055 
        or32_opcodes[i].encoding, ti[i].insn_mask, ti[i].insn);*/
1056 
    }
1057 
 
1058 
  /* Until all are covered search for best criteria to separate them.  */
1059 
  end = cover_insn (automata, curpass, 0xFFFFFFFF);
1060 
  if (end - automata > MAX_AUTOMATA_SIZE)
1061 
    {
1062 
      fprintf (stderr, "Automata too large. Increase MAX_AUTOMATA_SIZE.");
1063 
      exit (1);
1064 
    }
1065 
#ifdef HAS_EXECUTION
1066 
  printf("done, num uncovered: %i/%i.\n", nuncovered, num_opcodes);
1067 
#endif
1068 
 
1069 
#ifdef HAS_EXECUTION
1070 
  printf("Parsing operands data... ");
1071 
#endif
1072 
  op_data = (struct insn_op_struct *) malloc (MAX_OP_TABLE_SIZE * sizeof (struct insn_op_struct));
1073 
  op_start = (struct insn_op_struct **) malloc (num_opcodes * sizeof (struct insn_op_struct *));
1074 
  cur = op_data;
1075 
  for (i = 0; i < num_opcodes; i++)
1076 
    {
1077 
      op_start[i] = cur;
1078 
      cur = parse_params (&or32_opcodes[i], cur);
1079 
      if (cur - op_data > MAX_OP_TABLE_SIZE)
1080 
        {
1081 
          fprintf (stderr, "Operands table too small, increase MAX_OP_TABLE_SIZE.\n");
1082 
          exit (1);
1083 
        }
1084 
    }
1085 
#ifdef HAS_EXECUTION
1086 
  printf("done.\n");
1087 
#endif
1088 
}
1089 
 
1090 
void destruct_automata ()
1091 
{
1092 
  free (ti);
1093 
  free (automata);
1094 
  free (op_data);
1095 
  free (op_start);
1096 
}
1097 
 
1098 
/* Decodes instruction and returns instruction index.  */
1099 
int insn_decode (unsigned int insn)
1100 
{
1101 
  unsigned long *a = automata;
1102 
  int i;
1103 
  while (!(*a & LEAF_FLAG))
1104 
    {
1105 
      unsigned int first = *a;
1106 
      //debug(9, "%i ", a - automata);
1107 
      a++;
1108 
      i = (insn >> first) & *a;
1109 
      a++;
1110 
      if (!*(a + i))
1111 
        { /* Invalid instruction found?  */
1112 
          //debug(9, "XXX\n", i);
1113 
          return -1;
1114 
        }
1115 
      a = automata + *(a + i);
1116 
    }
1117 
  i = *a & ~LEAF_FLAG;
1118 
  //debug(9, "%i\n", i);
1119 
  /* Final check - do we have direct match?
1120 
     (based on or32_opcodes this should be the only possibility,
1121 
     but in case of invalid/missing instruction we must perform a check)  */
1122 
  if ((ti[i].insn_mask & insn) == ti[i].insn)
1123 
    return i;
1124 
  else
1125 
    return -1;
1126 
}
1127 
 
1128 
static char disassembled_str[50];
1129 
char *disassembled = &disassembled_str[0];
1130 
 
1131 
/* Automagically does zero- or sign- extension and also finds correct
1132 
   sign bit position if sign extension is correct extension. Which extension
1133 
   is proper is figured out from letter description. */
1134 
 
1135 
unsigned long
1136 
extend_imm(unsigned long imm, char l)
1137 
{
1138 
  unsigned long mask;
1139 
  int letter_bits;
1140 
 
1141 
  /* First truncate all bits above valid range for this letter
1142 
     in case it is zero extend. */
1143 
  letter_bits = letter_range(l);
1144 
  mask = (1 << letter_bits) - 1;
1145 
  imm &= mask;
1146 
 
1147 
  /* Do sign extend if this is the right one. */
1148 
  if (letter_signed(l) && (imm >> (letter_bits - 1)))
1149 
    imm |= (~mask);
1150 
 
1151 
  return imm;
1152 
}
1153 
 
1154 
static unsigned long
1155 
or32_extract(char param_ch, char *enc_initial, unsigned long insn)
1156 
{
1157 
  char *enc;
1158 
  unsigned long ret = 0;
1159 
  int opc_pos = 0;
1160 
  int param_pos = 0;
1161 
 
1162 
  for (enc = enc_initial; *enc != '\0'; enc++)
1163 
    if (*enc == param_ch)
1164 
      {
1165 
        if (enc - 2 >= enc_initial && (*(enc - 2) == '0') && (*(enc - 1) == 'x'))
1166 
          continue;
1167 
        else
1168 
          param_pos++;
1169 
      }
1170 
 
1171 
#if DEBUG
1172 
  printf("or32_extract: %x ", param_pos);
1173 
#endif
1174 
  opc_pos = 32;
1175 
  for (enc = enc_initial; *enc != '\0'; )
1176 
    if ((*enc == '0') && (*(enc+1) == 'x'))
1177 
      {
1178 
        opc_pos -= 4;
1179 
        if ((param_ch == '0') || (param_ch == '1'))
1180 
          {
1181 
            unsigned long tmp = strtol(enc, NULL, 16);
1182 
#if DEBUG
1183 
            printf(" enc=%s, tmp=%x ", enc, tmp);
1184 
#endif
1185 
            if (param_ch == '0')
1186 
              tmp = 15 - tmp;
1187 
            ret |= tmp << opc_pos;
1188 
          }
1189 
        enc += 3;
1190 
      }
1191 
    else if ((*enc == '0') || (*enc == '1'))
1192 
      {
1193 
        opc_pos--;
1194 
        if (param_ch == *enc)
1195 
          ret |= 1 << opc_pos;
1196 
        enc++;
1197 
      }
1198 
    else if (*enc == param_ch)
1199 
      {
1200 
        opc_pos--;
1201 
        param_pos--;
1202 
#if DEBUG
1203 
        printf("\n  ret=%x opc_pos=%x, param_pos=%x\n", ret, opc_pos, param_pos);
1204 
#endif
1205 
        if (islower(param_ch))
1206 
          ret -= ((insn >> opc_pos) & 0x1) << param_pos;
1207 
        else
1208 
          ret += ((insn >> opc_pos) & 0x1) << param_pos;
1209 
        enc++;
1210 
      }
1211 
    else if (isalpha(*enc))
1212 
      {
1213 
        opc_pos--;
1214 
        enc++;
1215 
      }
1216 
    else if (*enc == '-')
1217 
      {
1218 
        opc_pos--;
1219 
        enc++;
1220 
      }
1221 
    else
1222 
      enc++;
1223 
 
1224 
#if DEBUG
1225 
  printf ("ret=%x\n", ret);
1226 
#endif
1227 
  return ret;
1228 
}
1229 
 
1230 
/* Print register. Used only by print_insn. */
1231 
 
1232 
static char *
1233 
or32_print_register (char *dest, char param_ch, char *encoding, unsigned long insn)
1234 
{
1235 
  int regnum = or32_extract(param_ch, encoding, insn);
1236 
 
1237 
  sprintf (dest, "r%d", regnum);
1238 
  while (*dest) dest++;
1239 
  return dest;
1240 
}
1241 
 
1242 
/* Print immediate. Used only by print_insn. */
1243 
 
1244 
static char *
1245 
or32_print_immediate (char *dest, char param_ch, char *encoding, unsigned long insn)
1246 
{
1247 
  int imm = or32_extract (param_ch, encoding, insn);
1248 
 
1249 
  imm = extend_imm(imm, param_ch);
1250 
 
1251 
  if (letter_signed(param_ch))
1252 
    {
1253 
      if (imm < 0)
1254 
        sprintf (dest, "%d", imm);
1255 
      else
1256 
        sprintf (dest, "0x%x", imm);
1257 
    }
1258 
  else
1259 
    sprintf (dest, "%#x", imm);
1260 
  while (*dest) dest++;
1261 
  return dest;
1262 
}
1263 
 
1264 
/* Disassemble one instruction from insn to disassemble.
1265 
   Return the size of the instruction.  */
1266 
 
1267 
int
1268 
disassemble_insn (insn)
1269 
     unsigned long insn;
1270 
{
1271 
  return disassemble_index (insn, insn_decode (insn));
1272 
}
1273 
 
1274 
/* Disassemble one instruction from insn index.
1275 
   Return the size of the instruction.  */
1276 
 
1277 
int
1278 
disassemble_index (insn, index)
1279 
     unsigned long insn;
1280 
     int index;
1281 
{
1282 
  char *dest = disassembled;
1283 
  if (index >= 0)
1284 
    {
1285 
      struct or32_opcode const *opcode = &or32_opcodes[index];
1286 
      char *s;
1287 
 
1288 
      strcpy (dest, opcode->name);
1289 
      while (*dest) dest++;
1290 
      *dest++ = ' ';
1291 
      *dest = 0;
1292 
 
1293 
      for (s = opcode->args; *s != '\0'; ++s)
1294 
        {
1295 
          switch (*s)
1296 
            {
1297 
            case '\0':
1298 
              return insn_len (insn);
1299 
 
1300 
            case 'r':
1301 
              dest = or32_print_register(dest, *++s, opcode->encoding, insn);
1302 
              break;
1303 
 
1304 
            default:
1305 
              if (strchr (opcode->encoding, *s))
1306 
                dest = or32_print_immediate (dest, *s, opcode->encoding, insn);
1307 
              else {
1308 
                *dest++ = *s;
1309 
                *dest = 0;
1310 
              }
1311 
            }
1312 
        }
1313 
    }
1314 
  else
1315 
    {
1316 
      /* This used to be %8x for binutils.  */
1317 
      sprintf(dest, ".word 0x%08lx", insn);
1318 
      while (*dest) dest++;
1319 
    }
1320 
  return insn_len (insn);
1321 
}

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