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<HTML
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>Default Interrupt Handling</TITLE
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HREF="ecos-ref.html"><LINK
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REL="UP"
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TITLE="Exception Handling"
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>eCos Reference Manual</TH
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WIDTH="80%"
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ALIGN="center"
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VALIGN="bottom"
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>Chapter 10. Exception Handling</TD
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><TD
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WIDTH="10%"
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ALIGN="right"
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VALIGN="bottom"
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WIDTH="100%"></DIV
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CLASS="SECTION"
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><H1
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CLASS="SECTION"
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><A
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NAME="HAL-DEFAULT-INTERRUPT-HANDLING">Default Interrupt Handling</H1
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><P
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>Most asynchronous external interrupt vectors will point to a default
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interrupt VSR which decodes the actual interrupt being delivered from
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the interrupt controller and invokes the appropriate ISR.</P
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><P
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>The default interrupt VSR has a number of responsibilities if it is
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going to interact with the Kernel cleanly and allow interrupts to
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cause thread preemption.</P
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><P
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>To support this VSR an ISR vector table is needed. For each valid
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vector three pointers need to be stored: the ISR, its data pointer and
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an opaque (to the HAL) interrupt object pointer needed by the
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kernel. It is implementation defined whether these are stored in a
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single table of triples, or in three separate tables.</P
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><P
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>The VSR follows the following approximate plan:</P
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><P
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></P
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><OL
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TYPE="1"
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><LI
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><P
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> Save the CPU state. In non-debug configurations, it may be
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possible to get away with saving less than the entire machine
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state. The option
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<TT
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CLASS="LITERAL"
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>CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT</TT
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>
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is supported in some targets to do this.
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</P
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></LI
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><LI
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><P
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> Increment the kernel scheduler lock. This is a static member of
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the Cyg_Scheduler class, however it has also been aliased to
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<TT
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CLASS="LITERAL"
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>cyg_scheduler_sched_lock</TT
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> so that it can be
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accessed from assembly code.
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</P
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></LI
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><LI
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><P
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> (Optional) Switch to an interrupt stack if not already running on
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it. This allows nested interrupts to be delivered without needing
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every thread to have a stack large enough to take the maximum
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possible nesting. It is implementation defined how to detect
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whether this is a nested interrupt but there are two basic
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techniques. The first is to inspect the stack pointer and switch
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only if it is not currently within the interrupt stack range; the
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second is to maintain a counter of the interrupt nesting level and
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switch only if it is zero. The option
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<TT
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CLASS="LITERAL"
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>CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK</TT
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>
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controls whether this happens.
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</P
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></LI
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><LI
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><P
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> Decode the actual external interrupt being delivered from
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the interrupt controller. This will yield the ISR vector
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number. The code to do this usually needs to come from the
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variant or platform HAL, so is usually present in the form of a
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macro or procedure callout.
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</P
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></LI
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><LI
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><P
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> (Optional) Re-enable interrupts to permit nesting. At this point
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we can potentially allow higher priority interrupts to occur. It
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depends on the interrupt architecture of the CPU and platform
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whether more interrupts will occur at this point, or whether they
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will only be delivered after the current interrupt has been
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acknowledged (by a call to
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<TT
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CLASS="FUNCTION"
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>HAL_INTERRUPT_ACKNOWLEDGE()</TT
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> in the ISR).
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</P
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></LI
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><LI
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><P
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> Using the ISR vector number as an index, retrieve the
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ISR pointer and its data pointer from the ISR vector table.
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</P
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></LI
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><LI
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><P
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> Construct a C call stack frame. This may involve making stack
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space for call frames, and arguments, and initializing the back
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pointers to halt a GDB backtrace operation.
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</P
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></LI
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><LI
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><P
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> Call the ISR, passing the vector number and data pointer. The
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vector number and a pointer to the saved state should be preserved
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across this call, preferably by storing them in registers that are
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defined to be callee-saved by the calling conventions.
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</P
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></LI
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><LI
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><P
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> If this is an un-nested interrupt and a separate interrupt
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stack is being used, switch back to the interrupted thread's
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own stack.
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</P
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></LI
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><LI
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><P
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> Use the saved ISR vector number to get the interrupt object
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pointer from the ISR vector table.
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</P
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></LI
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><LI
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><P
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> Call <TT
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CLASS="FUNCTION"
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>interrupt_end()</TT
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> passing it the return
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value from the ISR, the interrupt object pointer and a pointer to
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the saved CPU state. This function is implemented by the Kernel
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and is responsible for finishing off the interrupt
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handling. Specifically, it may post a DSR depending on the ISR
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return value, and will decrement the scheduler lock. If the lock
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is zeroed by this operation then any posted DSRs may be called and
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may in turn result in a thread context switch.
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</P
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></LI
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><LI
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><P
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> The return from <TT
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CLASS="FUNCTION"
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>interrupt_end()</TT
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> may occur
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some time after the call. Many other threads may have executed in
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the meantime. So here all we may do is restore the machine state
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and resume execution of the interrupted thread. Depending on the
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architecture, it may be necessary to disable interrupts again for
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part of this.
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</P
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></LI
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></OL
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><P
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>The detailed order of these steps may vary slightly depending on the
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architecture, in particular where interrupts are enabled and disabled.</P
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WIDTH="33%"
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>Default Synchronous Exception Handling</TD
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