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[/] [or1k_old/] [trunk/] [gdb-5.3/] [sim/] [v850/] [simops.c] - Blame information for rev 1782

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Line No. Rev Author Line
1 1181 sfurman 
#include "sim-main.h"
2 
#include "v850_sim.h"
3 
#include "simops.h"
4 
 
5 
#ifdef HAVE_UTIME_H
6 
#include <utime.h>
7 
#endif
8 
 
9 
#ifdef HAVE_TIME_H
10 
#include <time.h>
11 
#endif
12 
 
13 
#ifdef HAVE_UNISTD_H
14 
#include <unistd.h>
15 
#endif
16 
 
17 
#ifdef HAVE_STRING_H
18 
#include <string.h>
19 
#else
20 
#ifdef HAVE_STRINGS_H
21 
#include <strings.h>
22 
#endif
23 
#endif
24 
 
25 
#include "targ-vals.h"
26 
 
27 
#include "libiberty.h"
28 
 
29 
#include <errno.h>
30 
#if !defined(__GO32__) && !defined(_WIN32)
31 
#include <sys/stat.h>
32 
#include <sys/times.h>
33 
#include <sys/time.h>
34 
#endif
35 
 
36 
/* This is an array of the bit positions of registers r20 .. r31 in
37 
   that order in a prepare/dispose instruction.  */
38 
int type1_regs[12] = { 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 0, 21 };
39 
/* This is an array of the bit positions of registers r16 .. r31 in
40 
   that order in a push/pop instruction.  */
41 
int type2_regs[16] = { 3, 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
42 
/* This is an array of the bit positions of registers r1 .. r15 in
43 
   that order in a push/pop instruction.  */
44 
int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
45 
 
46 
#ifdef DEBUG
47 
#ifndef SIZE_INSTRUCTION
48 
#define SIZE_INSTRUCTION 18
49 
#endif
50 
 
51 
#ifndef SIZE_VALUES
52 
#define SIZE_VALUES 11
53 
#endif
54 
 
55 
 
56 
unsigned32 trace_values[3];
57 
int trace_num_values;
58 
unsigned32 trace_pc;
59 
const char *trace_name;
60 
int trace_module;
61 
 
62 
 
63 
void
64 
trace_input (name, type, size)
65 
     char *name;
66 
     enum op_types type;
67 
     int size;
68 
{
69 
 
70 
  if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
71 
    return;
72 
 
73 
  trace_pc = PC;
74 
  trace_name = name;
75 
  trace_module = TRACE_ALU_IDX;
76 
 
77 
  switch (type)
78 
    {
79 
    default:
80 
    case OP_UNKNOWN:
81 
    case OP_NONE:
82 
    case OP_TRAP:
83 
      trace_num_values = 0;
84 
      break;
85 
 
86 
    case OP_REG:
87 
    case OP_REG_REG_MOVE:
88 
      trace_values[0] = State.regs[OP[0]];
89 
      trace_num_values = 1;
90 
      break;
91 
 
92 
    case OP_BIT_CHANGE:
93 
    case OP_REG_REG:
94 
    case OP_REG_REG_CMP:
95 
      trace_values[0] = State.regs[OP[1]];
96 
      trace_values[1] = State.regs[OP[0]];
97 
      trace_num_values = 2;
98 
      break;
99 
 
100 
    case OP_IMM_REG:
101 
    case OP_IMM_REG_CMP:
102 
      trace_values[0] = SEXT5 (OP[0]);
103 
      trace_values[1] = OP[1];
104 
      trace_num_values = 2;
105 
      break;
106 
 
107 
    case OP_IMM_REG_MOVE:
108 
      trace_values[0] = SEXT5 (OP[0]);
109 
      trace_num_values = 1;
110 
      break;
111 
 
112 
    case OP_COND_BR:
113 
      trace_values[0] = State.pc;
114 
      trace_values[1] = SEXT9 (OP[0]);
115 
      trace_values[2] = PSW;
116 
      trace_num_values = 3;
117 
      break;
118 
 
119 
    case OP_LOAD16:
120 
      trace_values[0] = OP[1] * size;
121 
      trace_values[1] = State.regs[30];
122 
      trace_num_values = 2;
123 
      break;
124 
 
125 
    case OP_STORE16:
126 
      trace_values[0] = State.regs[OP[0]];
127 
      trace_values[1] = OP[1] * size;
128 
      trace_values[2] = State.regs[30];
129 
      trace_num_values = 3;
130 
      break;
131 
 
132 
    case OP_LOAD32:
133 
      trace_values[0] = EXTEND16 (OP[2]);
134 
      trace_values[1] = State.regs[OP[0]];
135 
      trace_num_values = 2;
136 
      break;
137 
 
138 
    case OP_STORE32:
139 
      trace_values[0] = State.regs[OP[1]];
140 
      trace_values[1] = EXTEND16 (OP[2]);
141 
      trace_values[2] = State.regs[OP[0]];
142 
      trace_num_values = 3;
143 
      break;
144 
 
145 
    case OP_JUMP:
146 
      trace_values[0] = SEXT22 (OP[0]);
147 
      trace_values[1] = State.pc;
148 
      trace_num_values = 2;
149 
      break;
150 
 
151 
    case OP_IMM_REG_REG:
152 
      trace_values[0] = EXTEND16 (OP[0]) << size;
153 
      trace_values[1] = State.regs[OP[1]];
154 
      trace_num_values = 2;
155 
      break;
156 
 
157 
    case OP_IMM16_REG_REG:
158 
      trace_values[0] = EXTEND16 (OP[2]) << size;
159 
      trace_values[1] = State.regs[OP[1]];
160 
      trace_num_values = 2;
161 
      break;
162 
 
163 
    case OP_UIMM_REG_REG:
164 
      trace_values[0] = (OP[0] & 0xffff) << size;
165 
      trace_values[1] = State.regs[OP[1]];
166 
      trace_num_values = 2;
167 
      break;
168 
 
169 
    case OP_UIMM16_REG_REG:
170 
      trace_values[0] = (OP[2]) << size;
171 
      trace_values[1] = State.regs[OP[1]];
172 
      trace_num_values = 2;
173 
      break;
174 
 
175 
    case OP_BIT:
176 
      trace_num_values = 0;
177 
      break;
178 
 
179 
    case OP_EX1:
180 
      trace_values[0] = PSW;
181 
      trace_num_values = 1;
182 
      break;
183 
 
184 
    case OP_EX2:
185 
      trace_num_values = 0;
186 
      break;
187 
 
188 
    case OP_LDSR:
189 
      trace_values[0] = State.regs[OP[0]];
190 
      trace_num_values = 1;
191 
      break;
192 
 
193 
    case OP_STSR:
194 
      trace_values[0] = State.sregs[OP[1]];
195 
      trace_num_values = 1;
196 
    }
197 
 
198 
}
199 
 
200 
void
201 
trace_result (int has_result, unsigned32 result)
202 
{
203 
  char buf[1000];
204 
  char *chp;
205 
 
206 
  buf[0] = '\0';
207 
  chp = buf;
208 
 
209 
  /* write out the values saved during the trace_input call */
210 
  {
211 
    int i;
212 
    for (i = 0; i < trace_num_values; i++)
213 
      {
214 
        sprintf (chp, "%*s0x%.8lx", SIZE_VALUES - 10, "",
215 
                 (long) trace_values[i]);
216 
        chp = strchr (chp, '\0');
217 
      }
218 
    while (i++ < 3)
219 
      {
220 
        sprintf (chp, "%*s", SIZE_VALUES, "");
221 
        chp = strchr (chp, '\0');
222 
      }
223 
  }
224 
 
225 
  /* append any result to the end of the buffer */
226 
  if (has_result)
227 
    sprintf (chp, " :: 0x%.8lx", (unsigned long)result);
228 
 
229 
  trace_generic (simulator, STATE_CPU (simulator, 0), trace_module, buf);
230 
}
231 
 
232 
void
233 
trace_output (result)
234 
     enum op_types result;
235 
{
236 
  if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
237 
    return;
238 
 
239 
  switch (result)
240 
    {
241 
    default:
242 
    case OP_UNKNOWN:
243 
    case OP_NONE:
244 
    case OP_TRAP:
245 
    case OP_REG:
246 
    case OP_REG_REG_CMP:
247 
    case OP_IMM_REG_CMP:
248 
    case OP_COND_BR:
249 
    case OP_STORE16:
250 
    case OP_STORE32:
251 
    case OP_BIT:
252 
    case OP_EX2:
253 
      trace_result (0, 0);
254 
      break;
255 
 
256 
    case OP_LOAD16:
257 
    case OP_STSR:
258 
      trace_result (1, State.regs[OP[0]]);
259 
      break;
260 
 
261 
    case OP_REG_REG:
262 
    case OP_REG_REG_MOVE:
263 
    case OP_IMM_REG:
264 
    case OP_IMM_REG_MOVE:
265 
    case OP_LOAD32:
266 
    case OP_EX1:
267 
      trace_result (1, State.regs[OP[1]]);
268 
      break;
269 
 
270 
    case OP_IMM_REG_REG:
271 
    case OP_UIMM_REG_REG:
272 
    case OP_IMM16_REG_REG:
273 
    case OP_UIMM16_REG_REG:
274 
      trace_result (1, State.regs[OP[1]]);
275 
      break;
276 
 
277 
    case OP_JUMP:
278 
      if (OP[1] != 0)
279 
        trace_result (1, State.regs[OP[1]]);
280 
      else
281 
        trace_result (0, 0);
282 
      break;
283 
 
284 
    case OP_LDSR:
285 
      trace_result (1, State.sregs[OP[1]]);
286 
      break;
287 
    }
288 
}
289 
#endif
290 
 
291 
 
292 
/* Returns 1 if the specific condition is met, returns 0 otherwise.  */
293 
int
294 
condition_met (unsigned code)
295 
{
296 
  unsigned int psw = PSW;
297 
 
298 
  switch (code & 0xf)
299 
    {
300 
      case 0x0: return ((psw & PSW_OV) != 0);
301 
      case 0x1: return ((psw & PSW_CY) != 0);
302 
      case 0x2: return ((psw & PSW_Z) != 0);
303 
      case 0x3: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
304 
      case 0x4: return ((psw & PSW_S) != 0);
305 
    /*case 0x5: return 1;*/
306 
      case 0x6: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
307 
      case 0x7: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) != 0);
308 
      case 0x8: return ((psw & PSW_OV) == 0);
309 
      case 0x9: return ((psw & PSW_CY) == 0);
310 
      case 0xa: return ((psw & PSW_Z) == 0);
311 
      case 0xb: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
312 
      case 0xc: return ((psw & PSW_S) == 0);
313 
      case 0xd: return ((psw & PSW_SAT) != 0);
314 
      case 0xe: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
315 
      case 0xf: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) == 0);
316 
    }
317 
 
318 
  return 1;
319 
}
320 
 
321 
static unsigned long
322 
Add32 (unsigned long a1, unsigned long a2, int * carry)
323 
{
324 
  unsigned long result = (a1 + a2);
325 
 
326 
  * carry = (result < a1);
327 
 
328 
  return result;
329 
}
330 
 
331 
static void
332 
Multiply64 (boolean sign, unsigned long op0)
333 
{
334 
  unsigned long op1;
335 
  unsigned long lo;
336 
  unsigned long mid1;
337 
  unsigned long mid2;
338 
  unsigned long hi;
339 
  unsigned long RdLo;
340 
  unsigned long RdHi;
341 
  int           carry;
342 
 
343 
  op1 = State.regs[ OP[1] ];
344 
 
345 
  if (sign)
346 
    {
347 
      /* Compute sign of result and adjust operands if necessary.  */
348 
 
349 
      sign = (op0 ^ op1) & 0x80000000;
350 
 
351 
      if (((signed long) op0) < 0)
352 
        op0 = - op0;
353 
 
354 
      if (((signed long) op1) < 0)
355 
        op1 = - op1;
356 
    }
357 
 
358 
  /* We can split the 32x32 into four 16x16 operations. This ensures
359 
     that we do not lose precision on 32bit only hosts: */
360 
  lo   = ( (op0        & 0xFFFF) *  (op1        & 0xFFFF));
361 
  mid1 = ( (op0        & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
362 
  mid2 = (((op0 >> 16) & 0xFFFF) *  (op1        & 0xFFFF));
363 
  hi   = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
364 
 
365 
  /* We now need to add all of these results together, taking care
366 
     to propogate the carries from the additions: */
367 
  RdLo = Add32 (lo, (mid1 << 16), & carry);
368 
  RdHi = carry;
369 
  RdLo = Add32 (RdLo, (mid2 << 16), & carry);
370 
  RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi);
371 
 
372 
  if (sign)
373 
    {
374 
      /* Negate result if necessary.  */
375 
 
376 
      RdLo = ~ RdLo;
377 
      RdHi = ~ RdHi;
378 
      if (RdLo == 0xFFFFFFFF)
379 
        {
380 
          RdLo = 0;
381 
          RdHi += 1;
382 
        }
383 
      else
384 
        RdLo += 1;
385 
    }
386 
 
387 
  /* Don't store into register 0.  */
388 
  if (OP[1])
389 
    State.regs[ OP[1]       ] = RdLo;
390 
  if (OP[2] >> 11)
391 
    State.regs[ OP[2] >> 11 ] = RdHi;
392 
 
393 
  return;
394 
}
395 
 
396 
 
397 
/* Read a null terminated string from memory, return in a buffer */
398 
static char *
399 
fetch_str (sd, addr)
400 
     SIM_DESC sd;
401 
     address_word addr;
402 
{
403 
  char *buf;
404 
  int nr = 0;
405 
  while (sim_core_read_1 (STATE_CPU (sd, 0),
406 
                          PC, read_map, addr + nr) != 0)
407 
    nr++;
408 
  buf = NZALLOC (char, nr + 1);
409 
  sim_read (simulator, addr, buf, nr);
410 
  return buf;
411 
}
412 
 
413 
/* Read a null terminated argument vector from memory, return in a
414 
   buffer */
415 
static char **
416 
fetch_argv (sd, addr)
417 
     SIM_DESC sd;
418 
     address_word addr;
419 
{
420 
  int max_nr = 64;
421 
  int nr = 0;
422 
  char **buf = xmalloc (max_nr * sizeof (char*));
423 
  while (1)
424 
    {
425 
      unsigned32 a = sim_core_read_4 (STATE_CPU (sd, 0),
426 
                                      PC, read_map, addr + nr * 4);
427 
      if (a == 0) break;
428 
      buf[nr] = fetch_str (sd, a);
429 
      nr ++;
430 
      if (nr == max_nr - 1)
431 
        {
432 
          max_nr += 50;
433 
          buf = xrealloc (buf, max_nr * sizeof (char*));
434 
        }
435 
    }
436 
  buf[nr] = 0;
437 
  return buf;
438 
}
439 
 
440 
 
441 
/* sst.b */
442 
int
443 
OP_380 ()
444 
{
445 
  trace_input ("sst.b", OP_STORE16, 1);
446 
 
447 
  store_mem (State.regs[30] + (OP[3] & 0x7f), 1, State.regs[ OP[1] ]);
448 
 
449 
  trace_output (OP_STORE16);
450 
 
451 
  return 2;
452 
}
453 
 
454 
/* sst.h */
455 
int
456 
OP_480 ()
457 
{
458 
  trace_input ("sst.h", OP_STORE16, 2);
459 
 
460 
  store_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2, State.regs[ OP[1] ]);
461 
 
462 
  trace_output (OP_STORE16);
463 
 
464 
  return 2;
465 
}
466 
 
467 
/* sst.w */
468 
int
469 
OP_501 ()
470 
{
471 
  trace_input ("sst.w", OP_STORE16, 4);
472 
 
473 
  store_mem (State.regs[30] + ((OP[3] & 0x7e) << 1), 4, State.regs[ OP[1] ]);
474 
 
475 
  trace_output (OP_STORE16);
476 
 
477 
  return 2;
478 
}
479 
 
480 
/* ld.b */
481 
int
482 
OP_700 ()
483 
{
484 
  int adr;
485 
 
486 
  trace_input ("ld.b", OP_LOAD32, 1);
487 
 
488 
  adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
489 
 
490 
  State.regs[ OP[1] ] = EXTEND8 (load_mem (adr, 1));
491 
 
492 
  trace_output (OP_LOAD32);
493 
 
494 
  return 4;
495 
}
496 
 
497 
/* ld.h */
498 
int
499 
OP_720 ()
500 
{
501 
  int adr;
502 
 
503 
  trace_input ("ld.h", OP_LOAD32, 2);
504 
 
505 
  adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
506 
  adr &= ~0x1;
507 
 
508 
  State.regs[ OP[1] ] = EXTEND16 (load_mem (adr, 2));
509 
 
510 
  trace_output (OP_LOAD32);
511 
 
512 
  return 4;
513 
}
514 
 
515 
/* ld.w */
516 
int
517 
OP_10720 ()
518 
{
519 
  int adr;
520 
 
521 
  trace_input ("ld.w", OP_LOAD32, 4);
522 
 
523 
  adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
524 
  adr &= ~0x3;
525 
 
526 
  State.regs[ OP[1] ] = load_mem (adr, 4);
527 
 
528 
  trace_output (OP_LOAD32);
529 
 
530 
  return 4;
531 
}
532 
 
533 
/* st.b */
534 
int
535 
OP_740 ()
536 
{
537 
  trace_input ("st.b", OP_STORE32, 1);
538 
 
539 
  store_mem (State.regs[ OP[0] ] + EXTEND16 (OP[2]), 1, State.regs[ OP[1] ]);
540 
 
541 
  trace_output (OP_STORE32);
542 
 
543 
  return 4;
544 
}
545 
 
546 
/* st.h */
547 
int
548 
OP_760 ()
549 
{
550 
  int adr;
551 
 
552 
  trace_input ("st.h", OP_STORE32, 2);
553 
 
554 
  adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
555 
  adr &= ~1;
556 
 
557 
  store_mem (adr, 2, State.regs[ OP[1] ]);
558 
 
559 
  trace_output (OP_STORE32);
560 
 
561 
  return 4;
562 
}
563 
 
564 
/* st.w */
565 
int
566 
OP_10760 ()
567 
{
568 
  int adr;
569 
 
570 
  trace_input ("st.w", OP_STORE32, 4);
571 
 
572 
  adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
573 
  adr &= ~3;
574 
 
575 
  store_mem (adr, 4, State.regs[ OP[1] ]);
576 
 
577 
  trace_output (OP_STORE32);
578 
 
579 
  return 4;
580 
}
581 
 
582 
/* add reg, reg */
583 
int
584 
OP_1C0 ()
585 
{
586 
  unsigned int op0, op1, result, z, s, cy, ov;
587 
 
588 
  trace_input ("add", OP_REG_REG, 0);
589 
 
590 
  /* Compute the result.  */
591 
 
592 
  op0 = State.regs[ OP[0] ];
593 
  op1 = State.regs[ OP[1] ];
594 
 
595 
  result = op0 + op1;
596 
 
597 
  /* Compute the condition codes.  */
598 
  z = (result == 0);
599 
  s = (result & 0x80000000);
600 
  cy = (result < op0 || result < op1);
601 
  ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
602 
        && (op0 & 0x80000000) != (result & 0x80000000));
603 
 
604 
  /* Store the result and condition codes.  */
605 
  State.regs[OP[1]] = result;
606 
  PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
607 
  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
608 
                     | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
609 
  trace_output (OP_REG_REG);
610 
 
611 
  return 2;
612 
}
613 
 
614 
/* add sign_extend(imm5), reg */
615 
int
616 
OP_240 ()
617 
{
618 
  unsigned int op0, op1, result, z, s, cy, ov;
619 
  int temp;
620 
 
621 
  trace_input ("add", OP_IMM_REG, 0);
622 
 
623 
  /* Compute the result.  */
624 
  temp = SEXT5 (OP[0]);
625 
  op0 = temp;
626 
  op1 = State.regs[OP[1]];
627 
  result = op0 + op1;
628 
 
629 
  /* Compute the condition codes.  */
630 
  z = (result == 0);
631 
  s = (result & 0x80000000);
632 
  cy = (result < op0 || result < op1);
633 
  ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
634 
        && (op0 & 0x80000000) != (result & 0x80000000));
635 
 
636 
  /* Store the result and condition codes.  */
637 
  State.regs[OP[1]] = result;
638 
  PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
639 
  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
640 
                | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
641 
  trace_output (OP_IMM_REG);
642 
 
643 
  return 2;
644 
}
645 
 
646 
/* addi sign_extend(imm16), reg, reg */
647 
int
648 
OP_600 ()
649 
{
650 
  unsigned int op0, op1, result, z, s, cy, ov;
651 
 
652 
  trace_input ("addi", OP_IMM16_REG_REG, 0);
653 
 
654 
  /* Compute the result.  */
655 
 
656 
  op0 = EXTEND16 (OP[2]);
657 
  op1 = State.regs[ OP[0] ];
658 
  result = op0 + op1;
659 
 
660 
  /* Compute the condition codes.  */
661 
  z = (result == 0);
662 
  s = (result & 0x80000000);
663 
  cy = (result < op0 || result < op1);
664 
  ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
665 
        && (op0 & 0x80000000) != (result & 0x80000000));
666 
 
667 
  /* Store the result and condition codes.  */
668 
  State.regs[OP[1]] = result;
669 
  PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
670 
  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
671 
                | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
672 
  trace_output (OP_IMM16_REG_REG);
673 
 
674 
  return 4;
675 
}
676 
 
677 
/* sub reg1, reg2 */
678 
int
679 
OP_1A0 ()
680 
{
681 
  unsigned int op0, op1, result, z, s, cy, ov;
682 
 
683 
  trace_input ("sub", OP_REG_REG, 0);
684 
  /* Compute the result.  */
685 
  op0 = State.regs[ OP[0] ];
686 
  op1 = State.regs[ OP[1] ];
687 
  result = op1 - op0;
688 
 
689 
  /* Compute the condition codes.  */
690 
  z = (result == 0);
691 
  s = (result & 0x80000000);
692 
  cy = (op1 < op0);
693 
  ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
694 
        && (op1 & 0x80000000) != (result & 0x80000000));
695 
 
696 
  /* Store the result and condition codes.  */
697 
  State.regs[OP[1]] = result;
698 
  PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
699 
  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
700 
                | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
701 
  trace_output (OP_REG_REG);
702 
 
703 
  return 2;
704 
}
705 
 
706 
/* subr reg1, reg2 */
707 
int
708 
OP_180 ()
709 
{
710 
  unsigned int op0, op1, result, z, s, cy, ov;
711 
 
712 
  trace_input ("subr", OP_REG_REG, 0);
713 
  /* Compute the result.  */
714 
  op0 = State.regs[ OP[0] ];
715 
  op1 = State.regs[ OP[1] ];
716 
  result = op0 - op1;
717 
 
718 
  /* Compute the condition codes.  */
719 
  z = (result == 0);
720 
  s = (result & 0x80000000);
721 
  cy = (op0 < op1);
722 
  ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
723 
        && (op0 & 0x80000000) != (result & 0x80000000));
724 
 
725 
  /* Store the result and condition codes.  */
726 
  State.regs[OP[1]] = result;
727 
  PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
728 
  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
729 
                | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
730 
  trace_output (OP_REG_REG);
731 
 
732 
  return 2;
733 
}
734 
 
735 
/* sxh reg1 */
736 
int
737 
OP_E0 ()
738 
{
739 
  trace_input ("mulh", OP_REG_REG, 0);
740 
 
741 
  State.regs[ OP[1] ] = (EXTEND16 (State.regs[ OP[1] ]) * EXTEND16 (State.regs[ OP[0] ]));
742 
 
743 
  trace_output (OP_REG_REG);
744 
 
745 
  return 2;
746 
}
747 
 
748 
/* mulh sign_extend(imm5), reg2 */
749 
int
750 
OP_2E0 ()
751 
{
752 
  trace_input ("mulh", OP_IMM_REG, 0);
753 
 
754 
  State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[1] ]) * SEXT5 (OP[0]);
755 
 
756 
  trace_output (OP_IMM_REG);
757 
 
758 
  return 2;
759 
}
760 
 
761 
/* mulhi imm16, reg1, reg2 */
762 
int
763 
OP_6E0 ()
764 
{
765 
  trace_input ("mulhi", OP_IMM16_REG_REG, 0);
766 
 
767 
  State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[0] ]) * EXTEND16 (OP[2]);
768 
 
769 
  trace_output (OP_IMM16_REG_REG);
770 
 
771 
  return 4;
772 
}
773 
 
774 
/* divh reg1, reg2 */
775 
int
776 
OP_40 ()
777 
{
778 
  unsigned int op0, op1, result, ov, s, z;
779 
  int temp;
780 
 
781 
  trace_input ("divh", OP_REG_REG, 0);
782 
 
783 
  /* Compute the result.  */
784 
  temp = EXTEND16 (State.regs[ OP[0] ]);
785 
  op0 = temp;
786 
  op1 = State.regs[OP[1]];
787 
 
788 
  if (op0 == 0xffffffff && op1 == 0x80000000)
789 
    {
790 
      result = 0x80000000;
791 
      ov = 1;
792 
    }
793 
  else if (op0 != 0)
794 
    {
795 
      result = op1 / op0;
796 
      ov = 0;
797 
    }
798 
  else
799 
    {
800 
      result = 0x0;
801 
      ov = 1;
802 
    }
803 
 
804 
  /* Compute the condition codes.  */
805 
  z = (result == 0);
806 
  s = (result & 0x80000000);
807 
 
808 
  /* Store the result and condition codes.  */
809 
  State.regs[OP[1]] = result;
810 
  PSW &= ~(PSW_Z | PSW_S | PSW_OV);
811 
  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
812 
          | (ov ? PSW_OV : 0));
813 
  trace_output (OP_REG_REG);
814 
 
815 
  return 2;
816 
}
817 
 
818 
/* cmp reg, reg */
819 
int
820 
OP_1E0 ()
821 
{
822 
  unsigned int op0, op1, result, z, s, cy, ov;
823 
 
824 
  trace_input ("cmp", OP_REG_REG_CMP, 0);
825 
  /* Compute the result.  */
826 
  op0 = State.regs[ OP[0] ];
827 
  op1 = State.regs[ OP[1] ];
828 
  result = op1 - op0;
829 
 
830 
  /* Compute the condition codes.  */
831 
  z = (result == 0);
832 
  s = (result & 0x80000000);
833 
  cy = (op1 < op0);
834 
  ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
835 
        && (op1 & 0x80000000) != (result & 0x80000000));
836 
 
837 
  /* Set condition codes.  */
838 
  PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
839 
  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
840 
                | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
841 
  trace_output (OP_REG_REG_CMP);
842 
 
843 
  return 2;
844 
}
845 
 
846 
/* cmp sign_extend(imm5), reg */
847 
int
848 
OP_260 ()
849 
{
850 
  unsigned int op0, op1, result, z, s, cy, ov;
851 
  int temp;
852 
 
853 
  /* Compute the result.  */
854 
  trace_input ("cmp", OP_IMM_REG_CMP, 0);
855 
  temp = SEXT5 (OP[0]);
856 
  op0 = temp;
857 
  op1 = State.regs[OP[1]];
858 
  result = op1 - op0;
859 
 
860 
  /* Compute the condition codes.  */
861 
  z = (result == 0);
862 
  s = (result & 0x80000000);
863 
  cy = (op1 < op0);
864 
  ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
865 
        && (op1 & 0x80000000) != (result & 0x80000000));
866 
 
867 
  /* Set condition codes.  */
868 
  PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
869 
  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
870 
                | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
871 
  trace_output (OP_IMM_REG_CMP);
872 
 
873 
  return 2;
874 
}
875 
 
876 
/* setf cccc,reg2 */
877 
int
878 
OP_7E0 ()
879 
{
880 
  trace_input ("setf", OP_EX1, 0);
881 
 
882 
  State.regs[ OP[1] ] = condition_met (OP[0]);
883 
 
884 
  trace_output (OP_EX1);
885 
 
886 
  return 4;
887 
}
888 
 
889 
/* satadd reg,reg */
890 
int
891 
OP_C0 ()
892 
{
893 
  unsigned int op0, op1, result, z, s, cy, ov, sat;
894 
 
895 
  trace_input ("satadd", OP_REG_REG, 0);
896 
  /* Compute the result.  */
897 
  op0 = State.regs[ OP[0] ];
898 
  op1 = State.regs[ OP[1] ];
899 
  result = op0 + op1;
900 
 
901 
  /* Compute the condition codes.  */
902 
  z = (result == 0);
903 
  s = (result & 0x80000000);
904 
  cy = (result < op0 || result < op1);
905 
  ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
906 
        && (op0 & 0x80000000) != (result & 0x80000000));
907 
  sat = ov;
908 
 
909 
  /* Store the result and condition codes.  */
910 
  State.regs[OP[1]] = result;
911 
  PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
912 
  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
913 
          | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
914 
          | (sat ? PSW_SAT : 0));
915 
 
916 
  /* Handle saturated results.  */
917 
  if (sat && s)
918 
    State.regs[OP[1]] = 0x80000000;
919 
  else if (sat)
920 
    State.regs[OP[1]] = 0x7fffffff;
921 
  trace_output (OP_REG_REG);
922 
 
923 
  return 2;
924 
}
925 
 
926 
/* satadd sign_extend(imm5), reg */
927 
int
928 
OP_220 ()
929 
{
930 
  unsigned int op0, op1, result, z, s, cy, ov, sat;
931 
 
932 
  int temp;
933 
 
934 
  trace_input ("satadd", OP_IMM_REG, 0);
935 
 
936 
  /* Compute the result.  */
937 
  temp = SEXT5 (OP[0]);
938 
  op0 = temp;
939 
  op1 = State.regs[OP[1]];
940 
  result = op0 + op1;
941 
 
942 
  /* Compute the condition codes.  */
943 
  z = (result == 0);
944 
  s = (result & 0x80000000);
945 
  cy = (result < op0 || result < op1);
946 
  ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
947 
        && (op0 & 0x80000000) != (result & 0x80000000));
948 
  sat = ov;
949 
 
950 
  /* Store the result and condition codes.  */
951 
  State.regs[OP[1]] = result;
952 
  PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
953 
  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
954 
                | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
955 
                | (sat ? PSW_SAT : 0));
956 
 
957 
  /* Handle saturated results.  */
958 
  if (sat && s)
959 
    State.regs[OP[1]] = 0x80000000;
960 
  else if (sat)
961 
    State.regs[OP[1]] = 0x7fffffff;
962 
  trace_output (OP_IMM_REG);
963 
 
964 
  return 2;
965 
}
966 
 
967 
/* satsub reg1, reg2 */
968 
int
969 
OP_A0 ()
970 
{
971 
  unsigned int op0, op1, result, z, s, cy, ov, sat;
972 
 
973 
  trace_input ("satsub", OP_REG_REG, 0);
974 
 
975 
  /* Compute the result.  */
976 
  op0 = State.regs[ OP[0] ];
977 
  op1 = State.regs[ OP[1] ];
978 
  result = op1 - op0;
979 
 
980 
  /* Compute the condition codes.  */
981 
  z = (result == 0);
982 
  s = (result & 0x80000000);
983 
  cy = (op1 < op0);
984 
  ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
985 
        && (op1 & 0x80000000) != (result & 0x80000000));
986 
  sat = ov;
987 
 
988 
  /* Store the result and condition codes.  */
989 
  State.regs[OP[1]] = result;
990 
  PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
991 
  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
992 
          | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
993 
          | (sat ? PSW_SAT : 0));
994 
 
995 
  /* Handle saturated results.  */
996 
  if (sat && s)
997 
    State.regs[OP[1]] = 0x80000000;
998 
  else if (sat)
999 
    State.regs[OP[1]] = 0x7fffffff;
1000 
  trace_output (OP_REG_REG);
1001 
  return 2;
1002 
}
1003 
 
1004 
/* satsubi sign_extend(imm16), reg */
1005 
int
1006 
OP_660 ()
1007 
{
1008 
  unsigned int op0, op1, result, z, s, cy, ov, sat;
1009 
  int temp;
1010 
 
1011 
  trace_input ("satsubi", OP_IMM_REG, 0);
1012 
 
1013 
  /* Compute the result.  */
1014 
  temp = EXTEND16 (OP[2]);
1015 
  op0 = temp;
1016 
  op1 = State.regs[ OP[0] ];
1017 
  result = op1 - op0;
1018 
 
1019 
  /* Compute the condition codes.  */
1020 
  z = (result == 0);
1021 
  s = (result & 0x80000000);
1022 
  cy = (op1 < op0);
1023 
  ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1024 
        && (op1 & 0x80000000) != (result & 0x80000000));
1025 
  sat = ov;
1026 
 
1027 
  /* Store the result and condition codes.  */
1028 
  State.regs[OP[1]] = result;
1029 
  PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1030 
  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1031 
                | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1032 
                | (sat ? PSW_SAT : 0));
1033 
 
1034 
  /* Handle saturated results.  */
1035 
  if (sat && s)
1036 
    State.regs[OP[1]] = 0x80000000;
1037 
  else if (sat)
1038 
    State.regs[OP[1]] = 0x7fffffff;
1039 
  trace_output (OP_IMM_REG);
1040 
 
1041 
  return 4;
1042 
}
1043 
 
1044 
/* satsubr reg,reg */
1045 
int
1046 
OP_80 ()
1047 
{
1048 
  unsigned int op0, op1, result, z, s, cy, ov, sat;
1049 
 
1050 
  trace_input ("satsubr", OP_REG_REG, 0);
1051 
 
1052 
  /* Compute the result.  */
1053 
  op0 = State.regs[ OP[0] ];
1054 
  op1 = State.regs[ OP[1] ];
1055 
  result = op0 - op1;
1056 
 
1057 
  /* Compute the condition codes.  */
1058 
  z = (result == 0);
1059 
  s = (result & 0x80000000);
1060 
  cy = (result < op0);
1061 
  ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1062 
        && (op1 & 0x80000000) != (result & 0x80000000));
1063 
  sat = ov;
1064 
 
1065 
  /* Store the result and condition codes.  */
1066 
  State.regs[OP[1]] = result;
1067 
  PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1068 
  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1069 
          | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1070 
          | (sat ? PSW_SAT : 0));
1071 
 
1072 
  /* Handle saturated results.  */
1073 
  if (sat && s)
1074 
    State.regs[OP[1]] = 0x80000000;
1075 
  else if (sat)
1076 
    State.regs[OP[1]] = 0x7fffffff;
1077 
  trace_output (OP_REG_REG);
1078 
 
1079 
  return 2;
1080 
}
1081 
 
1082 
/* tst reg,reg */
1083 
int
1084 
OP_160 ()
1085 
{
1086 
  unsigned int op0, op1, result, z, s;
1087 
 
1088 
  trace_input ("tst", OP_REG_REG_CMP, 0);
1089 
 
1090 
  /* Compute the result.  */
1091 
  op0 = State.regs[ OP[0] ];
1092 
  op1 = State.regs[ OP[1] ];
1093 
  result = op0 & op1;
1094 
 
1095 
  /* Compute the condition codes.  */
1096 
  z = (result == 0);
1097 
  s = (result & 0x80000000);
1098 
 
1099 
  /* Store the condition codes.  */
1100 
  PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1101 
  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1102 
  trace_output (OP_REG_REG_CMP);
1103 
 
1104 
  return 2;
1105 
}
1106 
 
1107 
/* mov sign_extend(imm5), reg */
1108 
int
1109 
OP_200 ()
1110 
{
1111 
  int value = SEXT5 (OP[0]);
1112 
 
1113 
  trace_input ("mov", OP_IMM_REG_MOVE, 0);
1114 
 
1115 
  State.regs[ OP[1] ] = value;
1116 
 
1117 
  trace_output (OP_IMM_REG_MOVE);
1118 
 
1119 
  return 2;
1120 
}
1121 
 
1122 
/* movhi imm16, reg, reg */
1123 
int
1124 
OP_640 ()
1125 
{
1126 
  trace_input ("movhi", OP_UIMM16_REG_REG, 16);
1127 
 
1128 
  State.regs[ OP[1] ] = State.regs[ OP[0] ] + (OP[2] << 16);
1129 
 
1130 
  trace_output (OP_UIMM16_REG_REG);
1131 
 
1132 
  return 4;
1133 
}
1134 
 
1135 
/* sar zero_extend(imm5),reg1 */
1136 
int
1137 
OP_2A0 ()
1138 
{
1139 
  unsigned int op0, op1, result, z, s, cy;
1140 
 
1141 
  trace_input ("sar", OP_IMM_REG, 0);
1142 
  op0 = OP[0];
1143 
  op1 = State.regs[ OP[1] ];
1144 
  result = (signed)op1 >> op0;
1145 
 
1146 
  /* Compute the condition codes.  */
1147 
  z = (result == 0);
1148 
  s = (result & 0x80000000);
1149 
  cy = (op1 & (1 << (op0 - 1)));
1150 
 
1151 
  /* Store the result and condition codes.  */
1152 
  State.regs[ OP[1] ] = result;
1153 
  PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1154 
  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1155 
                | (cy ? PSW_CY : 0));
1156 
  trace_output (OP_IMM_REG);
1157 
 
1158 
  return 2;
1159 
}
1160 
 
1161 
/* sar reg1, reg2 */
1162 
int
1163 
OP_A007E0 ()
1164 
{
1165 
  unsigned int op0, op1, result, z, s, cy;
1166 
 
1167 
  trace_input ("sar", OP_REG_REG, 0);
1168 
 
1169 
  op0 = State.regs[ OP[0] ] & 0x1f;
1170 
  op1 = State.regs[ OP[1] ];
1171 
  result = (signed)op1 >> op0;
1172 
 
1173 
  /* Compute the condition codes.  */
1174 
  z = (result == 0);
1175 
  s = (result & 0x80000000);
1176 
  cy = (op1 & (1 << (op0 - 1)));
1177 
 
1178 
  /* Store the result and condition codes.  */
1179 
  State.regs[OP[1]] = result;
1180 
  PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1181 
  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1182 
                | (cy ? PSW_CY : 0));
1183 
  trace_output (OP_REG_REG);
1184 
 
1185 
  return 4;
1186 
}
1187 
 
1188 
/* shl zero_extend(imm5),reg1 */
1189 
int
1190 
OP_2C0 ()
1191 
{
1192 
  unsigned int op0, op1, result, z, s, cy;
1193 
 
1194 
  trace_input ("shl", OP_IMM_REG, 0);
1195 
  op0 = OP[0];
1196 
  op1 = State.regs[ OP[1] ];
1197 
  result = op1 << op0;
1198 
 
1199 
  /* Compute the condition codes.  */
1200 
  z = (result == 0);
1201 
  s = (result & 0x80000000);
1202 
  cy = (op1 & (1 << (32 - op0)));
1203 
 
1204 
  /* Store the result and condition codes.  */
1205 
  State.regs[OP[1]] = result;
1206 
  PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1207 
  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1208 
                | (cy ? PSW_CY : 0));
1209 
  trace_output (OP_IMM_REG);
1210 
 
1211 
  return 2;
1212 
}
1213 
 
1214 
/* shl reg1, reg2 */
1215 
int
1216 
OP_C007E0 ()
1217 
{
1218 
  unsigned int op0, op1, result, z, s, cy;
1219 
 
1220 
  trace_input ("shl", OP_REG_REG, 0);
1221 
  op0 = State.regs[ OP[0] ] & 0x1f;
1222 
  op1 = State.regs[ OP[1] ];
1223 
  result = op1 << op0;
1224 
 
1225 
  /* Compute the condition codes.  */
1226 
  z = (result == 0);
1227 
  s = (result & 0x80000000);
1228 
  cy = (op1 & (1 << (32 - op0)));
1229 
 
1230 
  /* Store the result and condition codes.  */
1231 
  State.regs[OP[1]] = result;
1232 
  PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1233 
  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1234 
                | (cy ? PSW_CY : 0));
1235 
  trace_output (OP_REG_REG);
1236 
 
1237 
  return 4;
1238 
}
1239 
 
1240 
/* shr zero_extend(imm5),reg1 */
1241 
int
1242 
OP_280 ()
1243 
{
1244 
  unsigned int op0, op1, result, z, s, cy;
1245 
 
1246 
  trace_input ("shr", OP_IMM_REG, 0);
1247 
  op0 = OP[0];
1248 
  op1 = State.regs[ OP[1] ];
1249 
  result = op1 >> op0;
1250 
 
1251 
  /* Compute the condition codes.  */
1252 
  z = (result == 0);
1253 
  s = (result & 0x80000000);
1254 
  cy = (op1 & (1 << (op0 - 1)));
1255 
 
1256 
  /* Store the result and condition codes.  */
1257 
  State.regs[OP[1]] = result;
1258 
  PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1259 
  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1260 
                | (cy ? PSW_CY : 0));
1261 
  trace_output (OP_IMM_REG);
1262 
 
1263 
  return 2;
1264 
}
1265 
 
1266 
/* shr reg1, reg2 */
1267 
int
1268 
OP_8007E0 ()
1269 
{
1270 
  unsigned int op0, op1, result, z, s, cy;
1271 
 
1272 
  trace_input ("shr", OP_REG_REG, 0);
1273 
  op0 = State.regs[ OP[0] ] & 0x1f;
1274 
  op1 = State.regs[ OP[1] ];
1275 
  result = op1 >> op0;
1276 
 
1277 
  /* Compute the condition codes.  */
1278 
  z = (result == 0);
1279 
  s = (result & 0x80000000);
1280 
  cy = (op1 & (1 << (op0 - 1)));
1281 
 
1282 
  /* Store the result and condition codes.  */
1283 
  State.regs[OP[1]] = result;
1284 
  PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1285 
  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1286 
                | (cy ? PSW_CY : 0));
1287 
  trace_output (OP_REG_REG);
1288 
 
1289 
  return 4;
1290 
}
1291 
 
1292 
/* or reg, reg */
1293 
int
1294 
OP_100 ()
1295 
{
1296 
  unsigned int op0, op1, result, z, s;
1297 
 
1298 
  trace_input ("or", OP_REG_REG, 0);
1299 
 
1300 
  /* Compute the result.  */
1301 
  op0 = State.regs[ OP[0] ];
1302 
  op1 = State.regs[ OP[1] ];
1303 
  result = op0 | op1;
1304 
 
1305 
  /* Compute the condition codes.  */
1306 
  z = (result == 0);
1307 
  s = (result & 0x80000000);
1308 
 
1309 
  /* Store the result and condition codes.  */
1310 
  State.regs[OP[1]] = result;
1311 
  PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1312 
  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1313 
  trace_output (OP_REG_REG);
1314 
 
1315 
  return 2;
1316 
}
1317 
 
1318 
/* ori zero_extend(imm16), reg, reg */
1319 
int
1320 
OP_680 ()
1321 
{
1322 
  unsigned int op0, op1, result, z, s;
1323 
 
1324 
  trace_input ("ori", OP_UIMM16_REG_REG, 0);
1325 
  op0 = OP[2];
1326 
  op1 = State.regs[ OP[0] ];
1327 
  result = op0 | op1;
1328 
 
1329 
  /* Compute the condition codes.  */
1330 
  z = (result == 0);
1331 
  s = (result & 0x80000000);
1332 
 
1333 
  /* Store the result and condition codes.  */
1334 
  State.regs[OP[1]] = result;
1335 
  PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1336 
  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1337 
  trace_output (OP_UIMM16_REG_REG);
1338 
 
1339 
  return 4;
1340 
}
1341 
 
1342 
/* and reg, reg */
1343 
int
1344 
OP_140 ()
1345 
{
1346 
  unsigned int op0, op1, result, z, s;
1347 
 
1348 
  trace_input ("and", OP_REG_REG, 0);
1349 
 
1350 
  /* Compute the result.  */
1351 
  op0 = State.regs[ OP[0] ];
1352 
  op1 = State.regs[ OP[1] ];
1353 
  result = op0 & op1;
1354 
 
1355 
  /* Compute the condition codes.  */
1356 
  z = (result == 0);
1357 
  s = (result & 0x80000000);
1358 
 
1359 
  /* Store the result and condition codes.  */
1360 
  State.regs[OP[1]] = result;
1361 
  PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1362 
  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1363 
  trace_output (OP_REG_REG);
1364 
 
1365 
  return 2;
1366 
}
1367 
 
1368 
/* andi zero_extend(imm16), reg, reg */
1369 
int
1370 
OP_6C0 ()
1371 
{
1372 
  unsigned int result, z;
1373 
 
1374 
  trace_input ("andi", OP_UIMM16_REG_REG, 0);
1375 
 
1376 
  result = OP[2] & State.regs[ OP[0] ];
1377 
 
1378 
  /* Compute the condition codes.  */
1379 
  z = (result == 0);
1380 
 
1381 
  /* Store the result and condition codes.  */
1382 
  State.regs[ OP[1] ] = result;
1383 
 
1384 
  PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1385 
  PSW |= (z ? PSW_Z : 0);
1386 
 
1387 
  trace_output (OP_UIMM16_REG_REG);
1388 
 
1389 
  return 4;
1390 
}
1391 
 
1392 
/* xor reg, reg */
1393 
int
1394 
OP_120 ()
1395 
{
1396 
  unsigned int op0, op1, result, z, s;
1397 
 
1398 
  trace_input ("xor", OP_REG_REG, 0);
1399 
 
1400 
  /* Compute the result.  */
1401 
  op0 = State.regs[ OP[0] ];
1402 
  op1 = State.regs[ OP[1] ];
1403 
  result = op0 ^ op1;
1404 
 
1405 
  /* Compute the condition codes.  */
1406 
  z = (result == 0);
1407 
  s = (result & 0x80000000);
1408 
 
1409 
  /* Store the result and condition codes.  */
1410 
  State.regs[OP[1]] = result;
1411 
  PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1412 
  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1413 
  trace_output (OP_REG_REG);
1414 
 
1415 
  return 2;
1416 
}
1417 
 
1418 
/* xori zero_extend(imm16), reg, reg */
1419 
int
1420 
OP_6A0 ()
1421 
{
1422 
  unsigned int op0, op1, result, z, s;
1423 
 
1424 
  trace_input ("xori", OP_UIMM16_REG_REG, 0);
1425 
  op0 = OP[2];
1426 
  op1 = State.regs[ OP[0] ];
1427 
  result = op0 ^ op1;
1428 
 
1429 
  /* Compute the condition codes.  */
1430 
  z = (result == 0);
1431 
  s = (result & 0x80000000);
1432 
 
1433 
  /* Store the result and condition codes.  */
1434 
  State.regs[OP[1]] = result;
1435 
  PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1436 
  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1437 
  trace_output (OP_UIMM16_REG_REG);
1438 
 
1439 
  return 4;
1440 
}
1441 
 
1442 
/* not reg1, reg2 */
1443 
int
1444 
OP_20 ()
1445 
{
1446 
  unsigned int op0, result, z, s;
1447 
 
1448 
  trace_input ("not", OP_REG_REG_MOVE, 0);
1449 
  /* Compute the result.  */
1450 
  op0 = State.regs[ OP[0] ];
1451 
  result = ~op0;
1452 
 
1453 
  /* Compute the condition codes.  */
1454 
  z = (result == 0);
1455 
  s = (result & 0x80000000);
1456 
 
1457 
  /* Store the result and condition codes.  */
1458 
  State.regs[OP[1]] = result;
1459 
  PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1460 
  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1461 
  trace_output (OP_REG_REG_MOVE);
1462 
 
1463 
  return 2;
1464 
}
1465 
 
1466 
/* set1 */
1467 
int
1468 
OP_7C0 ()
1469 
{
1470 
  unsigned int op0, op1, op2;
1471 
  int temp;
1472 
 
1473 
  trace_input ("set1", OP_BIT, 0);
1474 
  op0 = State.regs[ OP[0] ];
1475 
  op1 = OP[1] & 0x7;
1476 
  temp = EXTEND16 (OP[2]);
1477 
  op2 = temp;
1478 
  temp = load_mem (op0 + op2, 1);
1479 
  PSW &= ~PSW_Z;
1480 
  if ((temp & (1 << op1)) == 0)
1481 
    PSW |= PSW_Z;
1482 
  temp |= (1 << op1);
1483 
  store_mem (op0 + op2, 1, temp);
1484 
  trace_output (OP_BIT);
1485 
 
1486 
  return 4;
1487 
}
1488 
 
1489 
/* not1 */
1490 
int
1491 
OP_47C0 ()
1492 
{
1493 
  unsigned int op0, op1, op2;
1494 
  int temp;
1495 
 
1496 
  trace_input ("not1", OP_BIT, 0);
1497 
  op0 = State.regs[ OP[0] ];
1498 
  op1 = OP[1] & 0x7;
1499 
  temp = EXTEND16 (OP[2]);
1500 
  op2 = temp;
1501 
  temp = load_mem (op0 + op2, 1);
1502 
  PSW &= ~PSW_Z;
1503 
  if ((temp & (1 << op1)) == 0)
1504 
    PSW |= PSW_Z;
1505 
  temp ^= (1 << op1);
1506 
  store_mem (op0 + op2, 1, temp);
1507 
  trace_output (OP_BIT);
1508 
 
1509 
  return 4;
1510 
}
1511 
 
1512 
/* clr1 */
1513 
int
1514 
OP_87C0 ()
1515 
{
1516 
  unsigned int op0, op1, op2;
1517 
  int temp;
1518 
 
1519 
  trace_input ("clr1", OP_BIT, 0);
1520 
  op0 = State.regs[ OP[0] ];
1521 
  op1 = OP[1] & 0x7;
1522 
  temp = EXTEND16 (OP[2]);
1523 
  op2 = temp;
1524 
  temp = load_mem (op0 + op2, 1);
1525 
  PSW &= ~PSW_Z;
1526 
  if ((temp & (1 << op1)) == 0)
1527 
    PSW |= PSW_Z;
1528 
  temp &= ~(1 << op1);
1529 
  store_mem (op0 + op2, 1, temp);
1530 
  trace_output (OP_BIT);
1531 
 
1532 
  return 4;
1533 
}
1534 
 
1535 
/* tst1 */
1536 
int
1537 
OP_C7C0 ()
1538 
{
1539 
  unsigned int op0, op1, op2;
1540 
  int temp;
1541 
 
1542 
  trace_input ("tst1", OP_BIT, 0);
1543 
  op0 = State.regs[ OP[0] ];
1544 
  op1 = OP[1] & 0x7;
1545 
  temp = EXTEND16 (OP[2]);
1546 
  op2 = temp;
1547 
  temp = load_mem (op0 + op2, 1);
1548 
  PSW &= ~PSW_Z;
1549 
  if ((temp & (1 << op1)) == 0)
1550 
    PSW |= PSW_Z;
1551 
  trace_output (OP_BIT);
1552 
 
1553 
  return 4;
1554 
}
1555 
 
1556 
/* di */
1557 
int
1558 
OP_16007E0 ()
1559 
{
1560 
  trace_input ("di", OP_NONE, 0);
1561 
  PSW |= PSW_ID;
1562 
  trace_output (OP_NONE);
1563 
 
1564 
  return 4;
1565 
}
1566 
 
1567 
/* ei */
1568 
int
1569 
OP_16087E0 ()
1570 
{
1571 
  trace_input ("ei", OP_NONE, 0);
1572 
  PSW &= ~PSW_ID;
1573 
  trace_output (OP_NONE);
1574 
 
1575 
  return 4;
1576 
}
1577 
 
1578 
/* halt */
1579 
int
1580 
OP_12007E0 ()
1581 
{
1582 
  trace_input ("halt", OP_NONE, 0);
1583 
  /* FIXME this should put processor into a mode where NMI still handled */
1584 
  trace_output (OP_NONE);
1585 
  sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1586 
                   sim_stopped, SIM_SIGTRAP);
1587 
  return 0;
1588 
}
1589 
 
1590 
/* trap */
1591 
int
1592 
OP_10007E0 ()
1593 
{
1594 
  trace_input ("trap", OP_TRAP, 0);
1595 
  trace_output (OP_TRAP);
1596 
 
1597 
  /* Trap 31 is used for simulating OS I/O functions */
1598 
 
1599 
  if (OP[0] == 31)
1600 
    {
1601 
      int save_errno = errno;
1602 
      errno = 0;
1603 
 
1604 
/* Registers passed to trap 0 */
1605 
 
1606 
#define FUNC   State.regs[6]    /* function number, return value */
1607 
#define PARM1  State.regs[7]    /* optional parm 1 */
1608 
#define PARM2  State.regs[8]    /* optional parm 2 */
1609 
#define PARM3  State.regs[9]    /* optional parm 3 */
1610 
 
1611 
/* Registers set by trap 0 */
1612 
 
1613 
#define RETVAL State.regs[10]   /* return value */
1614 
#define RETERR State.regs[11]   /* return error code */
1615 
 
1616 
/* Turn a pointer in a register into a pointer into real memory. */
1617 
 
1618 
#define MEMPTR(x) (map (x))
1619 
 
1620 
      switch (FUNC)
1621 
        {
1622 
 
1623 
#ifdef HAVE_FORK
1624 
#ifdef TARGET_SYS_fork
1625 
        case TARGET_SYS_fork:
1626 
          RETVAL = fork ();
1627 
          break;
1628 
#endif
1629 
#endif
1630 
 
1631 
#ifdef HAVE_EXECVE
1632 
#ifdef TARGET_SYS_execv
1633 
        case TARGET_SYS_execve:
1634 
          {
1635 
            char *path = fetch_str (simulator, PARM1);
1636 
            char **argv = fetch_argv (simulator, PARM2);
1637 
            char **envp = fetch_argv (simulator, PARM3);
1638 
            RETVAL = execve (path, argv, envp);
1639 
            zfree (path);
1640 
            freeargv (argv);
1641 
            freeargv (envp);
1642 
            break;
1643 
          }
1644 
#endif
1645 
#endif
1646 
 
1647 
#if HAVE_EXECV
1648 
#ifdef TARGET_SYS_execv
1649 
        case TARGET_SYS_execv:
1650 
          {
1651 
            char *path = fetch_str (simulator, PARM1);
1652 
            char **argv = fetch_argv (simulator, PARM2);
1653 
            RETVAL = execv (path, argv);
1654 
            zfree (path);
1655 
            freeargv (argv);
1656 
            break;
1657 
          }
1658 
#endif
1659 
#endif
1660 
 
1661 
#if 0
1662 
#ifdef TARGET_SYS_pipe
1663 
        case TARGET_SYS_pipe:
1664 
          {
1665 
            reg_t buf;
1666 
            int host_fd[2];
1667 
 
1668 
            buf = PARM1;
1669 
            RETVAL = pipe (host_fd);
1670 
            SW (buf, host_fd[0]);
1671 
            buf += sizeof(uint16);
1672 
            SW (buf, host_fd[1]);
1673 
          }
1674 
          break;
1675 
#endif
1676 
#endif
1677 
 
1678 
#if 0
1679 
#ifdef TARGET_SYS_wait
1680 
        case TARGET_SYS_wait:
1681 
          {
1682 
            int status;
1683 
 
1684 
            RETVAL = wait (&status);
1685 
            SW (PARM1, status);
1686 
          }
1687 
          break;
1688 
#endif
1689 
#endif
1690 
 
1691 
#ifdef TARGET_SYS_read
1692 
        case TARGET_SYS_read:
1693 
          {
1694 
            char *buf = zalloc (PARM3);
1695 
            RETVAL = sim_io_read (simulator, PARM1, buf, PARM3);
1696 
            sim_write (simulator, PARM2, buf, PARM3);
1697 
            zfree (buf);
1698 
            break;
1699 
          }
1700 
#endif
1701 
 
1702 
#ifdef TARGET_SYS_write
1703 
        case TARGET_SYS_write:
1704 
          {
1705 
            char *buf = zalloc (PARM3);
1706 
            sim_read (simulator, PARM2, buf, PARM3);
1707 
            if (PARM1 == 1)
1708 
              RETVAL = sim_io_write_stdout (simulator, buf, PARM3);
1709 
            else
1710 
              RETVAL = sim_io_write (simulator, PARM1, buf, PARM3);
1711 
            zfree (buf);
1712 
            break;
1713 
          }
1714 
#endif
1715 
 
1716 
#ifdef TARGET_SYS_lseek
1717 
        case TARGET_SYS_lseek:
1718 
          RETVAL = sim_io_lseek (simulator, PARM1, PARM2, PARM3);
1719 
          break;
1720 
#endif
1721 
 
1722 
#ifdef TARGET_SYS_close
1723 
        case TARGET_SYS_close:
1724 
          RETVAL = sim_io_close (simulator, PARM1);
1725 
          break;
1726 
#endif
1727 
 
1728 
#ifdef TARGET_SYS_open
1729 
        case TARGET_SYS_open:
1730 
          {
1731 
            char *buf = fetch_str (simulator, PARM1);
1732 
            RETVAL = sim_io_open (simulator, buf, PARM2);
1733 
            zfree (buf);
1734 
            break;
1735 
          }
1736 
#endif
1737 
 
1738 
#ifdef TARGET_SYS_exit
1739 
        case TARGET_SYS_exit:
1740 
          if ((PARM1 & 0xffff0000) == 0xdead0000 && (PARM1 & 0xffff) != 0)
1741 
            /* get signal encoded by kill */
1742 
            sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1743 
                             sim_signalled, PARM1 & 0xffff);
1744 
          else if (PARM1 == 0xdead)
1745 
            /* old libraries */
1746 
            sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1747 
                             sim_stopped, SIM_SIGABRT);
1748 
          else
1749 
            /* PARM1 has exit status */
1750 
            sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1751 
                             sim_exited, PARM1);
1752 
          break;
1753 
#endif
1754 
 
1755 
#if !defined(__GO32__) && !defined(_WIN32)
1756 
#ifdef TARGET_SYS_stat
1757 
        case TARGET_SYS_stat:   /* added at hmsi */
1758 
          /* stat system call */
1759 
          {
1760 
            struct stat host_stat;
1761 
            reg_t buf;
1762 
            char *path = fetch_str (simulator, PARM1);
1763 
 
1764 
            RETVAL = stat (path, &host_stat);
1765 
 
1766 
            zfree (path);
1767 
            buf = PARM2;
1768 
 
1769 
            /* Just wild-assed guesses.  */
1770 
            store_mem (buf, 2, host_stat.st_dev);
1771 
            store_mem (buf + 2, 2, host_stat.st_ino);
1772 
            store_mem (buf + 4, 4, host_stat.st_mode);
1773 
            store_mem (buf + 8, 2, host_stat.st_nlink);
1774 
            store_mem (buf + 10, 2, host_stat.st_uid);
1775 
            store_mem (buf + 12, 2, host_stat.st_gid);
1776 
            store_mem (buf + 14, 2, host_stat.st_rdev);
1777 
            store_mem (buf + 16, 4, host_stat.st_size);
1778 
            store_mem (buf + 20, 4, host_stat.st_atime);
1779 
            store_mem (buf + 28, 4, host_stat.st_mtime);
1780 
            store_mem (buf + 36, 4, host_stat.st_ctime);
1781 
          }
1782 
          break;
1783 
#endif
1784 
#endif
1785 
 
1786 
#ifdef HAVE_CHOWN
1787 
#ifdef TARGET_SYS_chown
1788 
        case TARGET_SYS_chown:
1789 
          {
1790 
            char *path = fetch_str (simulator, PARM1);
1791 
            RETVAL = chown (path, PARM2, PARM3);
1792 
            zfree (path);
1793 
          }
1794 
          break;
1795 
#endif
1796 
#endif
1797 
 
1798 
#if HAVE_CHMOD
1799 
#ifdef TARGET_SYS_chmod
1800 
        case TARGET_SYS_chmod:
1801 
          {
1802 
            char *path = fetch_str (simulator, PARM1);
1803 
            RETVAL = chmod (path, PARM2);
1804 
            zfree (path);
1805 
          }
1806 
          break;
1807 
#endif
1808 
#endif
1809 
 
1810 
#ifdef TARGET_SYS_time
1811 
#if HAVE_TIME
1812 
        case TARGET_SYS_time:
1813 
          {
1814 
            time_t now;
1815 
            RETVAL = time (&now);
1816 
            store_mem (PARM1, 4, now);
1817 
          }
1818 
          break;
1819 
#endif
1820 
#endif
1821 
 
1822 
#if !defined(__GO32__) && !defined(_WIN32)
1823 
#ifdef TARGET_SYS_times
1824 
        case TARGET_SYS_times:
1825 
          {
1826 
            struct tms tms;
1827 
            RETVAL = times (&tms);
1828 
            store_mem (PARM1, 4, tms.tms_utime);
1829 
            store_mem (PARM1 + 4, 4, tms.tms_stime);
1830 
            store_mem (PARM1 + 8, 4, tms.tms_cutime);
1831 
            store_mem (PARM1 + 12, 4, tms.tms_cstime);
1832 
            break;
1833 
          }
1834 
#endif
1835 
#endif
1836 
 
1837 
#ifdef TARGET_SYS_gettimeofday
1838 
#if !defined(__GO32__) && !defined(_WIN32)
1839 
        case TARGET_SYS_gettimeofday:
1840 
          {
1841 
            struct timeval t;
1842 
            struct timezone tz;
1843 
            RETVAL = gettimeofday (&t, &tz);
1844 
            store_mem (PARM1, 4, t.tv_sec);
1845 
            store_mem (PARM1 + 4, 4, t.tv_usec);
1846 
            store_mem (PARM2, 4, tz.tz_minuteswest);
1847 
            store_mem (PARM2 + 4, 4, tz.tz_dsttime);
1848 
            break;
1849 
          }
1850 
#endif
1851 
#endif
1852 
 
1853 
#ifdef TARGET_SYS_utime
1854 
#if HAVE_UTIME
1855 
        case TARGET_SYS_utime:
1856 
          {
1857 
            /* Cast the second argument to void *, to avoid type mismatch
1858 
               if a prototype is present.  */
1859 
            sim_io_error (simulator, "Utime not supported");
1860 
            /* RETVAL = utime (path, (void *) MEMPTR (PARM2)); */
1861 
          }
1862 
          break;
1863 
#endif
1864 
#endif
1865 
 
1866 
        default:
1867 
          abort ();
1868 
        }
1869 
      RETERR = errno;
1870 
      errno = save_errno;
1871 
 
1872 
      return 4;
1873 
    }
1874 
  else
1875 
    {                           /* Trap 0 -> 30 */
1876 
      EIPC = PC + 4;
1877 
      EIPSW = PSW;
1878 
      /* Mask out EICC */
1879 
      ECR &= 0xffff0000;
1880 
      ECR |= 0x40 + OP[0];
1881 
      /* Flag that we are now doing exception processing.  */
1882 
      PSW |= PSW_EP | PSW_ID;
1883 
      PC = ((OP[0] < 0x10) ? 0x40 : 0x50) - 4;
1884 
 
1885 
      return 0;
1886 
    }
1887 
}
1888 
 
1889 
/* tst1 reg2, [reg1] */
1890 
int
1891 
OP_E607E0 (void)
1892 
{
1893 
  int temp;
1894 
 
1895 
  trace_input ("tst1", OP_BIT, 1);
1896 
 
1897 
  temp = load_mem (State.regs[ OP[0] ], 1);
1898 
 
1899 
  PSW &= ~PSW_Z;
1900 
  if ((temp & (1 << State.regs[ OP[1] & 0x7 ])) == 0)
1901 
    PSW |= PSW_Z;
1902 
 
1903 
  trace_output (OP_BIT);
1904 
 
1905 
  return 4;
1906 
}
1907 
 
1908 
/* mulu reg1, reg2, reg3 */
1909 
int
1910 
OP_22207E0 (void)
1911 
{
1912 
  trace_input ("mulu", OP_REG_REG_REG, 0);
1913 
 
1914 
  Multiply64 (false, State.regs[ OP[0] ]);
1915 
 
1916 
  trace_output (OP_REG_REG_REG);
1917 
 
1918 
  return 4;
1919 
}
1920 
 
1921 
#define BIT_CHANGE_OP( name, binop )            \
1922 
  unsigned int bit;                             \
1923 
  unsigned int temp;                            \
1924 
                                                \
1925 
  trace_input (name, OP_BIT_CHANGE, 0);          \
1926 
                                                \
1927 
  bit  = 1 << State.regs[ OP[1] & 0x7 ];        \
1928 
  temp = load_mem (State.regs[ OP[0] ], 1);      \
1929 
                                                \
1930 
  PSW &= ~PSW_Z;                                \
1931 
  if ((temp & bit) == 0)                 \
1932 
    PSW |= PSW_Z;                               \
1933 
  temp binop bit;                               \
1934 
                                                \
1935 
  store_mem (State.regs[ OP[0] ], 1, temp);      \
1936 
                                                \
1937 
  trace_output (OP_BIT_CHANGE);                 \
1938 
                                                \
1939 
  return 4;
1940 
 
1941 
/* clr1 reg2, [reg1] */
1942 
int
1943 
OP_E407E0 (void)
1944 
{
1945 
  BIT_CHANGE_OP ("clr1", &= ~ );
1946 
}
1947 
 
1948 
/* not1 reg2, [reg1] */
1949 
int
1950 
OP_E207E0 (void)
1951 
{
1952 
  BIT_CHANGE_OP ("not1", ^= );
1953 
}
1954 
 
1955 
/* set1 */
1956 
int
1957 
OP_E007E0 (void)
1958 
{
1959 
  BIT_CHANGE_OP ("set1", |= );
1960 
}
1961 
 
1962 
/* sasf */
1963 
int
1964 
OP_20007E0 (void)
1965 
{
1966 
  trace_input ("sasf", OP_EX1, 0);
1967 
 
1968 
  State.regs[ OP[1] ] = (State.regs[ OP[1] ] << 1) | condition_met (OP[0]);
1969 
 
1970 
  trace_output (OP_EX1);
1971 
 
1972 
  return 4;
1973 
}
1974 
 
1975 
/* This function is courtesy of Sugimoto at NEC, via Seow Tan
1976 
   (Soew_Tan@el.nec.com) */
1977 
void
1978 
divun
1979 
(
1980 
  unsigned int       N,
1981 
  unsigned long int  als,
1982 
  unsigned long int  sfi,
1983 
  unsigned32 /*unsigned long int*/ *  quotient_ptr,
1984 
  unsigned32 /*unsigned long int*/ *  remainder_ptr,
1985 
  boolean *          overflow_ptr
1986 
)
1987 
{
1988 
  unsigned long   ald = sfi >> (N - 1);
1989 
  unsigned long   alo = als;
1990 
  unsigned int    Q   = 1;
1991 
  unsigned int    C;
1992 
  unsigned int    S   = 0;
1993 
  unsigned int    i;
1994 
  unsigned int    R1  = 1;
1995 
  unsigned int    DBZ = (als == 0) ? 1 : 0;
1996 
  unsigned long   alt = Q ? ~als : als;
1997 
 
1998 
  /* 1st Loop */
1999 
  alo = ald + alt + Q;
2000 
  C   = (((alt >> 31) & (ald >> 31))
2001 
         | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2002 
  C   = C ^ Q;
2003 
  Q   = ~(C ^ S) & 1;
2004 
  R1  = (alo == 0) ? 0 : (R1 & Q);
2005 
  if ((S ^ (alo>>31)) && !C)
2006 
    {
2007 
      DBZ = 1;
2008 
    }
2009 
  S   = alo >> 31;
2010 
  sfi = (sfi << (32-N+1)) | Q;
2011 
  ald = (alo << 1) | (sfi >> 31);
2012 
 
2013 
  /* 2nd - N-1th Loop */
2014 
  for (i = 2; i < N; i++)
2015 
    {
2016 
      alt = Q ? ~als : als;
2017 
      alo = ald + alt + Q;
2018 
      C   = (((alt >> 31) & (ald >> 31))
2019 
             | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2020 
      C   = C ^ Q;
2021 
      Q   = ~(C ^ S) & 1;
2022 
      R1  = (alo == 0) ? 0 : (R1 & Q);
2023 
      if ((S ^ (alo>>31)) && !C && !DBZ)
2024 
        {
2025 
          DBZ = 1;
2026 
        }
2027 
      S   = alo >> 31;
2028 
      sfi = (sfi << 1) | Q;
2029 
      ald = (alo << 1) | (sfi >> 31);
2030 
    }
2031 
 
2032 
  /* Nth Loop */
2033 
  alt = Q ? ~als : als;
2034 
  alo = ald + alt + Q;
2035 
  C   = (((alt >> 31) & (ald >> 31))
2036 
         | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2037 
  C   = C ^ Q;
2038 
  Q   = ~(C ^ S) & 1;
2039 
  R1  = (alo == 0) ? 0 : (R1 & Q);
2040 
  if ((S ^ (alo>>31)) && !C)
2041 
    {
2042 
      DBZ = 1;
2043 
    }
2044 
 
2045 
  * quotient_ptr  = (sfi << 1) | Q;
2046 
  * remainder_ptr = Q ? alo : (alo + als);
2047 
  * overflow_ptr  = DBZ | R1;
2048 
}
2049 
 
2050 
/* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
2051 
void
2052 
divn
2053 
(
2054 
  unsigned int       N,
2055 
  unsigned long int  als,
2056 
  unsigned long int  sfi,
2057 
  signed32 /*signed long int*/ *  quotient_ptr,
2058 
  signed32 /*signed long int*/ *  remainder_ptr,
2059 
  boolean *          overflow_ptr
2060 
)
2061 
{
2062 
  unsigned long   ald = (signed long) sfi >> (N - 1);
2063 
  unsigned long   alo = als;
2064 
  unsigned int    SS  = als >> 31;
2065 
  unsigned int    SD  = sfi >> 31;
2066 
  unsigned int    R1  = 1;
2067 
  unsigned int    OV;
2068 
  unsigned int    DBZ = als == 0 ? 1 : 0;
2069 
  unsigned int    Q   = ~(SS ^ SD) & 1;
2070 
  unsigned int    C;
2071 
  unsigned int    S;
2072 
  unsigned int    i;
2073 
  unsigned long   alt = Q ? ~als : als;
2074 
 
2075 
 
2076 
  /* 1st Loop */
2077 
 
2078 
  alo = ald + alt + Q;
2079 
  C   = (((alt >> 31) & (ald >> 31))
2080 
         | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2081 
  Q   = C ^ SS;
2082 
  R1  = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2083 
  S   = alo >> 31;
2084 
  sfi = (sfi << (32-N+1)) | Q;
2085 
  ald = (alo << 1) | (sfi >> 31);
2086 
  if ((alo >> 31) ^ (ald >> 31))
2087 
    {
2088 
      DBZ = 1;
2089 
    }
2090 
 
2091 
  /* 2nd - N-1th Loop */
2092 
 
2093 
  for (i = 2; i < N; i++)
2094 
    {
2095 
      alt = Q ? ~als : als;
2096 
      alo = ald + alt + Q;
2097 
      C   = (((alt >> 31) & (ald >> 31))
2098 
             | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2099 
      Q   = C ^ SS;
2100 
      R1  = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2101 
      S   = alo >> 31;
2102 
      sfi = (sfi << 1) | Q;
2103 
      ald = (alo << 1) | (sfi >> 31);
2104 
      if ((alo >> 31) ^ (ald >> 31))
2105 
        {
2106 
          DBZ = 1;
2107 
        }
2108 
    }
2109 
 
2110 
  /* Nth Loop */
2111 
  alt = Q ? ~als : als;
2112 
  alo = ald + alt + Q;
2113 
  C   = (((alt >> 31) & (ald >> 31))
2114 
         | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2115 
  Q   = C ^ SS;
2116 
  R1  = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2117 
  sfi = (sfi << (32-N+1));
2118 
  ald = alo;
2119 
 
2120 
  /* End */
2121 
  if (alo != 0)
2122 
    {
2123 
      alt = Q ? ~als : als;
2124 
      alo = ald + alt + Q;
2125 
    }
2126 
  R1  = R1 & ((~alo >> 31) ^ SD);
2127 
  if ((alo != 0) && ((Q ^ (SS ^ SD)) ^ R1)) alo = ald;
2128 
  if (N != 32)
2129 
    ald = sfi = (long) ((sfi >> 1) | (SS ^ SD) << 31) >> (32-N-1) | Q;
2130 
  else
2131 
    ald = sfi = sfi | Q;
2132 
 
2133 
  OV = DBZ | ((alo == 0) ? 0 : R1);
2134 
 
2135 
  * remainder_ptr = alo;
2136 
 
2137 
  /* Adj */
2138 
  if (((alo != 0) && ((SS ^ SD) ^ R1))
2139 
      || ((alo == 0) && (SS ^ R1)))
2140 
    alo = ald + 1;
2141 
  else
2142 
    alo = ald;
2143 
 
2144 
  OV  = (DBZ | R1) ? OV : ((alo >> 31) & (~ald >> 31));
2145 
 
2146 
  * quotient_ptr  = alo;
2147 
  * overflow_ptr  = OV;
2148 
}
2149 
 
2150 
/* sdivun imm5, reg1, reg2, reg3 */
2151 
int
2152 
OP_1C207E0 (void)
2153 
{
2154 
  unsigned32 /*unsigned long int*/  quotient;
2155 
  unsigned32 /*unsigned long int*/  remainder;
2156 
  unsigned long int  divide_by;
2157 
  unsigned long int  divide_this;
2158 
  boolean            overflow = false;
2159 
  unsigned int       imm5;
2160 
 
2161 
  trace_input ("sdivun", OP_IMM_REG_REG_REG, 0);
2162 
 
2163 
  imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2164 
 
2165 
  divide_by   = State.regs[ OP[0] ];
2166 
  divide_this = State.regs[ OP[1] ] << imm5;
2167 
 
2168 
  divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2169 
 
2170 
  State.regs[ OP[1]       ] = quotient;
2171 
  State.regs[ OP[2] >> 11 ] = remainder;
2172 
 
2173 
  /* Set condition codes.  */
2174 
  PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2175 
 
2176 
  if (overflow)      PSW |= PSW_OV;
2177 
  if (quotient == 0) PSW |= PSW_Z;
2178 
  if (quotient & 0x80000000) PSW |= PSW_S;
2179 
 
2180 
  trace_output (OP_IMM_REG_REG_REG);
2181 
 
2182 
  return 4;
2183 
}
2184 
 
2185 
/* sdivn imm5, reg1, reg2, reg3 */
2186 
int
2187 
OP_1C007E0 (void)
2188 
{
2189 
  signed32 /*signed long int*/  quotient;
2190 
  signed32 /*signed long int*/  remainder;
2191 
  signed long int  divide_by;
2192 
  signed long int  divide_this;
2193 
  boolean          overflow = false;
2194 
  unsigned int     imm5;
2195 
 
2196 
  trace_input ("sdivn", OP_IMM_REG_REG_REG, 0);
2197 
 
2198 
  imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2199 
 
2200 
  divide_by   = State.regs[ OP[0] ];
2201 
  divide_this = State.regs[ OP[1] ] << imm5;
2202 
 
2203 
  divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2204 
 
2205 
  State.regs[ OP[1]       ] = quotient;
2206 
  State.regs[ OP[2] >> 11 ] = remainder;
2207 
 
2208 
  /* Set condition codes.  */
2209 
  PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2210 
 
2211 
  if (overflow)      PSW |= PSW_OV;
2212 
  if (quotient == 0) PSW |= PSW_Z;
2213 
  if (quotient <  0) PSW |= PSW_S;
2214 
 
2215 
  trace_output (OP_IMM_REG_REG_REG);
2216 
 
2217 
  return 4;
2218 
}
2219 
 
2220 
/* sdivhun imm5, reg1, reg2, reg3 */
2221 
int
2222 
OP_18207E0 (void)
2223 
{
2224 
  unsigned32 /*unsigned long int*/  quotient;
2225 
  unsigned32 /*unsigned long int*/  remainder;
2226 
  unsigned long int  divide_by;
2227 
  unsigned long int  divide_this;
2228 
  boolean            overflow = false;
2229 
  unsigned int       imm5;
2230 
 
2231 
  trace_input ("sdivhun", OP_IMM_REG_REG_REG, 0);
2232 
 
2233 
  imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2234 
 
2235 
  divide_by   = State.regs[ OP[0] ] & 0xffff;
2236 
  divide_this = State.regs[ OP[1] ] << imm5;
2237 
 
2238 
  divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2239 
 
2240 
  State.regs[ OP[1]       ] = quotient;
2241 
  State.regs[ OP[2] >> 11 ] = remainder;
2242 
 
2243 
  /* Set condition codes.  */
2244 
  PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2245 
 
2246 
  if (overflow)      PSW |= PSW_OV;
2247 
  if (quotient == 0) PSW |= PSW_Z;
2248 
  if (quotient & 0x80000000) PSW |= PSW_S;
2249 
 
2250 
  trace_output (OP_IMM_REG_REG_REG);
2251 
 
2252 
  return 4;
2253 
}
2254 
 
2255 
/* sdivhn imm5, reg1, reg2, reg3 */
2256 
int
2257 
OP_18007E0 (void)
2258 
{
2259 
  signed32 /*signed long int*/  quotient;
2260 
  signed32 /*signed long int*/  remainder;
2261 
  signed long int  divide_by;
2262 
  signed long int  divide_this;
2263 
  boolean          overflow = false;
2264 
  unsigned int     imm5;
2265 
 
2266 
  trace_input ("sdivhn", OP_IMM_REG_REG_REG, 0);
2267 
 
2268 
  imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2269 
 
2270 
  divide_by   = EXTEND16 (State.regs[ OP[0] ]);
2271 
  divide_this = State.regs[ OP[1] ] << imm5;
2272 
 
2273 
  divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2274 
 
2275 
  State.regs[ OP[1]       ] = quotient;
2276 
  State.regs[ OP[2] >> 11 ] = remainder;
2277 
 
2278 
  /* Set condition codes.  */
2279 
  PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2280 
 
2281 
  if (overflow)      PSW |= PSW_OV;
2282 
  if (quotient == 0) PSW |= PSW_Z;
2283 
  if (quotient <  0) PSW |= PSW_S;
2284 
 
2285 
  trace_output (OP_IMM_REG_REG_REG);
2286 
 
2287 
  return 4;
2288 
}
2289 
 
2290 
/* divu  reg1, reg2, reg3 */
2291 
int
2292 
OP_2C207E0 (void)
2293 
{
2294 
  unsigned long int quotient;
2295 
  unsigned long int remainder;
2296 
  unsigned long int divide_by;
2297 
  unsigned long int divide_this;
2298 
  boolean           overflow = false;
2299 
 
2300 
  trace_input ("divu", OP_REG_REG_REG, 0);
2301 
 
2302 
  /* Compute the result.  */
2303 
 
2304 
  divide_by   = State.regs[ OP[0] ];
2305 
  divide_this = State.regs[ OP[1] ];
2306 
 
2307 
  if (divide_by == 0)
2308 
    {
2309 
      overflow = true;
2310 
      divide_by  = 1;
2311 
    }
2312 
 
2313 
  State.regs[ OP[1]       ] = quotient  = divide_this / divide_by;
2314 
  State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2315 
 
2316 
  /* Set condition codes.  */
2317 
  PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2318 
 
2319 
  if (overflow)      PSW |= PSW_OV;
2320 
  if (quotient == 0) PSW |= PSW_Z;
2321 
  if (quotient & 0x80000000) PSW |= PSW_S;
2322 
 
2323 
  trace_output (OP_REG_REG_REG);
2324 
 
2325 
  return 4;
2326 
}
2327 
 
2328 
/* div  reg1, reg2, reg3 */
2329 
int
2330 
OP_2C007E0 (void)
2331 
{
2332 
  signed long int quotient;
2333 
  signed long int remainder;
2334 
  signed long int divide_by;
2335 
  signed long int divide_this;
2336 
  boolean         overflow = false;
2337 
 
2338 
  trace_input ("div", OP_REG_REG_REG, 0);
2339 
 
2340 
  /* Compute the result.  */
2341 
 
2342 
  divide_by   = State.regs[ OP[0] ];
2343 
  divide_this = State.regs[ OP[1] ];
2344 
 
2345 
  if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
2346 
    {
2347 
      overflow  = true;
2348 
      divide_by = 1;
2349 
    }
2350 
 
2351 
  State.regs[ OP[1]       ] = quotient  = divide_this / divide_by;
2352 
  State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2353 
 
2354 
  /* Set condition codes.  */
2355 
  PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2356 
 
2357 
  if (overflow)      PSW |= PSW_OV;
2358 
  if (quotient == 0) PSW |= PSW_Z;
2359 
  if (quotient <  0) PSW |= PSW_S;
2360 
 
2361 
  trace_output (OP_REG_REG_REG);
2362 
 
2363 
  return 4;
2364 
}
2365 
 
2366 
/* divhu  reg1, reg2, reg3 */
2367 
int
2368 
OP_28207E0 (void)
2369 
{
2370 
  unsigned long int quotient;
2371 
  unsigned long int remainder;
2372 
  unsigned long int divide_by;
2373 
  unsigned long int divide_this;
2374 
  boolean           overflow = false;
2375 
 
2376 
  trace_input ("divhu", OP_REG_REG_REG, 0);
2377 
 
2378 
  /* Compute the result.  */
2379 
 
2380 
  divide_by   = State.regs[ OP[0] ] & 0xffff;
2381 
  divide_this = State.regs[ OP[1] ];
2382 
 
2383 
  if (divide_by == 0)
2384 
    {
2385 
      overflow = true;
2386 
      divide_by  = 1;
2387 
    }
2388 
 
2389 
  State.regs[ OP[1]       ] = quotient  = divide_this / divide_by;
2390 
  State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2391 
 
2392 
  /* Set condition codes.  */
2393 
  PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2394 
 
2395 
  if (overflow)      PSW |= PSW_OV;
2396 
  if (quotient == 0) PSW |= PSW_Z;
2397 
  if (quotient & 0x80000000) PSW |= PSW_S;
2398 
 
2399 
  trace_output (OP_REG_REG_REG);
2400 
 
2401 
  return 4;
2402 
}
2403 
 
2404 
/* divh  reg1, reg2, reg3 */
2405 
int
2406 
OP_28007E0 (void)
2407 
{
2408 
  signed long int quotient;
2409 
  signed long int remainder;
2410 
  signed long int divide_by;
2411 
  signed long int divide_this;
2412 
  boolean         overflow = false;
2413 
 
2414 
  trace_input ("divh", OP_REG_REG_REG, 0);
2415 
 
2416 
  /* Compute the result.  */
2417 
 
2418 
  divide_by  = State.regs[ OP[0] ];
2419 
  divide_this = EXTEND16 (State.regs[ OP[1] ]);
2420 
 
2421 
  if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
2422 
    {
2423 
      overflow = true;
2424 
      divide_by  = 1;
2425 
    }
2426 
 
2427 
  State.regs[ OP[1]       ] = quotient  = divide_this / divide_by;
2428 
  State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2429 
 
2430 
  /* Set condition codes.  */
2431 
  PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2432 
 
2433 
  if (overflow)      PSW |= PSW_OV;
2434 
  if (quotient == 0) PSW |= PSW_Z;
2435 
  if (quotient <  0) PSW |= PSW_S;
2436 
 
2437 
  trace_output (OP_REG_REG_REG);
2438 
 
2439 
  return 4;
2440 
}
2441 
 
2442 
/* mulu imm9, reg2, reg3 */
2443 
int
2444 
OP_24207E0 (void)
2445 
{
2446 
  trace_input ("mulu", OP_IMM_REG_REG, 0);
2447 
 
2448 
  Multiply64 (false, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
2449 
 
2450 
  trace_output (OP_IMM_REG_REG);
2451 
 
2452 
  return 4;
2453 
}
2454 
 
2455 
/* mul imm9, reg2, reg3 */
2456 
int
2457 
OP_24007E0 (void)
2458 
{
2459 
  trace_input ("mul", OP_IMM_REG_REG, 0);
2460 
 
2461 
  Multiply64 (true, SEXT9 ((OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0)));
2462 
 
2463 
  trace_output (OP_IMM_REG_REG);
2464 
 
2465 
  return 4;
2466 
}
2467 
 
2468 
/* ld.hu */
2469 
int
2470 
OP_107E0 (void)
2471 
{
2472 
  int adr;
2473 
 
2474 
  trace_input ("ld.hu", OP_LOAD32, 2);
2475 
 
2476 
  adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
2477 
  adr &= ~0x1;
2478 
 
2479 
  State.regs[ OP[1] ] = load_mem (adr, 2);
2480 
 
2481 
  trace_output (OP_LOAD32);
2482 
 
2483 
  return 4;
2484 
}
2485 
 
2486 
 
2487 
/* ld.bu */
2488 
int
2489 
OP_10780 (void)
2490 
{
2491 
  int adr;
2492 
 
2493 
  trace_input ("ld.bu", OP_LOAD32, 1);
2494 
 
2495 
  adr = (State.regs[ OP[0] ]
2496 
         + (EXTEND16 (OP[2] & ~1) | ((OP[3] >> 5) & 1)));
2497 
 
2498 
  State.regs[ OP[1] ] = load_mem (adr, 1);
2499 
 
2500 
  trace_output (OP_LOAD32);
2501 
 
2502 
  return 4;
2503 
}
2504 
 
2505 
/* prepare list12, imm5, imm32 */
2506 
int
2507 
OP_1B0780 (void)
2508 
{
2509 
  int  i;
2510 
 
2511 
  trace_input ("prepare", OP_PUSHPOP1, 0);
2512 
 
2513 
  /* Store the registers with lower number registers being placed at higher addresses.  */
2514 
  for (i = 0; i < 12; i++)
2515 
    if ((OP[3] & (1 << type1_regs[ i ])))
2516 
      {
2517 
        SP -= 4;
2518 
        store_mem (SP, 4, State.regs[ 20 + i ]);
2519 
      }
2520 
 
2521 
  SP -= (OP[3] & 0x3e) << 1;
2522 
 
2523 
  EP = load_mem (PC + 4, 4);
2524 
 
2525 
  trace_output (OP_PUSHPOP1);
2526 
 
2527 
  return 8;
2528 
}
2529 
 
2530 
/* prepare list12, imm5, imm16-32 */
2531 
int
2532 
OP_130780 (void)
2533 
{
2534 
  int  i;
2535 
 
2536 
  trace_input ("prepare", OP_PUSHPOP1, 0);
2537 
 
2538 
  /* Store the registers with lower number registers being placed at higher addresses.  */
2539 
  for (i = 0; i < 12; i++)
2540 
    if ((OP[3] & (1 << type1_regs[ i ])))
2541 
      {
2542 
        SP -= 4;
2543 
        store_mem (SP, 4, State.regs[ 20 + i ]);
2544 
      }
2545 
 
2546 
  SP -= (OP[3] & 0x3e) << 1;
2547 
 
2548 
  EP = load_mem (PC + 4, 2) << 16;
2549 
 
2550 
  trace_output (OP_PUSHPOP1);
2551 
 
2552 
  return 6;
2553 
}
2554 
 
2555 
/* prepare list12, imm5, imm16 */
2556 
int
2557 
OP_B0780 (void)
2558 
{
2559 
  int  i;
2560 
 
2561 
  trace_input ("prepare", OP_PUSHPOP1, 0);
2562 
 
2563 
  /* Store the registers with lower number registers being placed at higher addresses.  */
2564 
  for (i = 0; i < 12; i++)
2565 
    if ((OP[3] & (1 << type1_regs[ i ])))
2566 
      {
2567 
        SP -= 4;
2568 
        store_mem (SP, 4, State.regs[ 20 + i ]);
2569 
      }
2570 
 
2571 
  SP -= (OP[3] & 0x3e) << 1;
2572 
 
2573 
  EP = EXTEND16 (load_mem (PC + 4, 2));
2574 
 
2575 
  trace_output (OP_PUSHPOP1);
2576 
 
2577 
  return 6;
2578 
}
2579 
 
2580 
/* prepare list12, imm5, sp */
2581 
int
2582 
OP_30780 (void)
2583 
{
2584 
  int  i;
2585 
 
2586 
  trace_input ("prepare", OP_PUSHPOP1, 0);
2587 
 
2588 
  /* Store the registers with lower number registers being placed at higher addresses.  */
2589 
  for (i = 0; i < 12; i++)
2590 
    if ((OP[3] & (1 << type1_regs[ i ])))
2591 
      {
2592 
        SP -= 4;
2593 
        store_mem (SP, 4, State.regs[ 20 + i ]);
2594 
      }
2595 
 
2596 
  SP -= (OP[3] & 0x3e) << 1;
2597 
 
2598 
  EP = SP;
2599 
 
2600 
  trace_output (OP_PUSHPOP1);
2601 
 
2602 
  return 4;
2603 
}
2604 
 
2605 
/* mul reg1, reg2, reg3 */
2606 
int
2607 
OP_22007E0 (void)
2608 
{
2609 
  trace_input ("mul", OP_REG_REG_REG, 0);
2610 
 
2611 
  Multiply64 (true, State.regs[ OP[0] ]);
2612 
 
2613 
  trace_output (OP_REG_REG_REG);
2614 
 
2615 
  return 4;
2616 
}
2617 
 
2618 
/* popmh list18 */
2619 
int
2620 
OP_307F0 (void)
2621 
{
2622 
  int i;
2623 
 
2624 
  trace_input ("popmh", OP_PUSHPOP2, 0);
2625 
 
2626 
  if (OP[3] & (1 << 19))
2627 
    {
2628 
      if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2629 
        {
2630 
          FEPSW = load_mem ( SP      & ~ 3, 4);
2631 
          FEPC  = load_mem ((SP + 4) & ~ 3, 4);
2632 
        }
2633 
      else
2634 
        {
2635 
          EIPSW = load_mem ( SP      & ~ 3, 4);
2636 
          EIPC  = load_mem ((SP + 4) & ~ 3, 4);
2637 
        }
2638 
 
2639 
      SP += 8;
2640 
    }
2641 
 
2642 
  /* Load the registers with lower number registers being retrieved from higher addresses.  */
2643 
  for (i = 16; i--;)
2644 
    if ((OP[3] & (1 << type2_regs[ i ])))
2645 
      {
2646 
        State.regs[ i + 16 ] = load_mem (SP & ~ 3, 4);
2647 
        SP += 4;
2648 
      }
2649 
 
2650 
  trace_output (OP_PUSHPOP2);
2651 
 
2652 
  return 4;
2653 
}
2654 
 
2655 
/* popml lsit18 */
2656 
int
2657 
OP_107F0 (void)
2658 
{
2659 
  int i;
2660 
 
2661 
  trace_input ("popml", OP_PUSHPOP3, 0);
2662 
 
2663 
  if (OP[3] & (1 << 19))
2664 
    {
2665 
      if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2666 
        {
2667 
          FEPSW = load_mem ( SP      & ~ 3, 4);
2668 
          FEPC =  load_mem ((SP + 4) & ~ 3, 4);
2669 
        }
2670 
      else
2671 
        {
2672 
          EIPSW = load_mem ( SP      & ~ 3, 4);
2673 
          EIPC  = load_mem ((SP + 4) & ~ 3, 4);
2674 
        }
2675 
 
2676 
      SP += 8;
2677 
    }
2678 
 
2679 
  if (OP[3] & (1 << 3))
2680 
    {
2681 
      PSW = load_mem (SP & ~ 3, 4);
2682 
      SP += 4;
2683 
    }
2684 
 
2685 
  /* Load the registers with lower number registers being retrieved from higher addresses.  */
2686 
  for (i = 15; i--;)
2687 
    if ((OP[3] & (1 << type3_regs[ i ])))
2688 
      {
2689 
        State.regs[ i + 1 ] = load_mem (SP & ~ 3, 4);
2690 
        SP += 4;
2691 
      }
2692 
 
2693 
  trace_output (OP_PUSHPOP2);
2694 
 
2695 
  return 4;
2696 
}
2697 
 
2698 
/* pushmh list18 */
2699 
int
2700 
OP_307E0 (void)
2701 
{
2702 
  int i;
2703 
 
2704 
  trace_input ("pushmh", OP_PUSHPOP2, 0);
2705 
 
2706 
  /* Store the registers with lower number registers being placed at higher addresses.  */
2707 
  for (i = 0; i < 16; i++)
2708 
    if ((OP[3] & (1 << type2_regs[ i ])))
2709 
      {
2710 
        SP -= 4;
2711 
        store_mem (SP & ~ 3, 4, State.regs[ i + 16 ]);
2712 
      }
2713 
 
2714 
  if (OP[3] & (1 << 19))
2715 
    {
2716 
      SP -= 8;
2717 
 
2718 
      if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2719 
        {
2720 
          store_mem ((SP + 4) & ~ 3, 4, FEPC);
2721 
          store_mem ( SP      & ~ 3, 4, FEPSW);
2722 
        }
2723 
      else
2724 
        {
2725 
          store_mem ((SP + 4) & ~ 3, 4, EIPC);
2726 
          store_mem ( SP      & ~ 3, 4, EIPSW);
2727 
        }
2728 
    }
2729 
 
2730 
  trace_output (OP_PUSHPOP2);
2731 
 
2732 
  return 4;
2733 
}
2734 
 

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