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// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/ILFLX_1M.v,v 1.1.1.1 2001-11-04 18:59:48 lampret Exp $

/*

FUNCTION        : FAST INPUT LATCH

*/

`timescale  100 ps / 10 ps

`celldefine

module ILFLX_1M (Q, D, G, GE, GF);

    parameter cds_action = "ignore";

    parameter INIT = 1'b0;

    output Q;

    reg    q_out;

    reg    o;

    input  D, G, GE, GF;

    tri0 GSR = glbl.GSR;

    buf B1 (Q, q_out);

        always @(D or GF)

            if (!GF)

                o = D;

        always @(GSR)

            if (GSR)

                assign q_out = INIT;

            else

                deassign q_out;

        always @(o or G or GE)

            if (!G && GE)

                q_out <= o;

    specify

        (D => Q) = (1, 1);

        (negedge G => (Q +: D)) = (1, 1);

        (posedge GE => (Q +: D)) = (1, 1);

    endspecify

endmodule

`endcelldefine