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// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/MUXF5_L.v,v 1.1.1.1 2001-11-04 18:59:49 lampret Exp $
 
/*
 
FUNCTION        : 2 to 1 Multiplexer for Carry Logic
 
*/
 
`timescale  100 ps / 10 ps
 
`celldefine
 
module MUXF5_L (LO, I0, I1, S);
 
    parameter cds_action = "ignore";
 
    output LO;
    reg    lo_out;
 
    input  I0, I1, S;
 
    buf B1 (LO, lo_out);
 
        always @(I0 or I1 or S) begin
            if (S)
                lo_out <= I1;
            else
                lo_out <= I0;
        end
 
    specify
        (I0 => LO) = (1, 1);
        (I1 => LO) = (1, 1);
        (S  => LO) = (1, 1);
    endspecify
 
endmodule
 
`endcelldefine

Line No.	Rev	Author	Line
1	266	lampret	`// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/MUXF5_L.v,v 1.1.1.1 2001-11-04 18:59:49 lampret Exp $`
2
3			`/*`
4
5			`FUNCTION : 2 to 1 Multiplexer for Carry Logic`
6
7			`*/`
8
9			`timescale 100 ps / 10 ps
10
11			`celldefine
12
13			`module MUXF5_L (LO, I0, I1, S);`
14
15			`parameter cds_action = "ignore";`
16
17			`output LO;`
18			`reg lo_out;`
19
20			`input I0, I1, S;`
21
22			`buf B1 (LO, lo_out);`
23
24			`always @(I0 or I1 or S) begin`
25			`if (S)`
26			`lo_out <= I1;`
27			`else`
28			`lo_out <= I0;`
29			`end`
30
31			`specify`
32			`(I0 => LO) = (1, 1);`
33			`(I1 => LO) = (1, 1);`
34			`(S => LO) = (1, 1);`
35			`endspecify`
36
37			`endmodule`
38
39			`endcelldefine

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[/] [or1k_old/] [trunk/] [mp3/] [lib/] [xilinx/] [unisims/] [MUXF5_L.v] - Blame information for rev 266