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[/] [or1k_old/] [trunk/] [mp3/] [sim/] [run/] [run_sim] - Blame information for rev 1782

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#!/bin/csh -f
 
#ncprep -f ../bin/nc.scr
#debussy -f ../bin/nc.scr
nLint -f ../bin/nc.scr
exit;
#verilog -f ../bin/nc.scr
# mv ncverilog.log ../log/ncverilog.log
 
ncvlog -f ncvlog.args
if ($status != 0) then
  exit
endif
 
# Run the NC-Verilog elaborator (build the design hierarchy)
ncelab -NOTIMINGCHECKS -f ncelab.args
if ($status != 0) then
  exit
endif
 
# Run the NC-Verilog simulator (simulate the design)
ncsim -f ncsim.args && \
mv flash.log ../log && \
mv executed.log ../log && \
mv sram.log ../log

Line No.	Rev	Author	Line
1	266	lampret	`#!/bin/csh -f`
2
3	507	lampret	`#ncprep -f ../bin/nc.scr`
4	266	lampret	`#debussy -f ../bin/nc.scr`
5	507	lampret	`nLint -f ../bin/nc.scr`
6			`exit;`
7	266	lampret	`#verilog -f ../bin/nc.scr`
8			`# mv ncverilog.log ../log/ncverilog.log`
9
10			`ncvlog -f ncvlog.args`
11			`if ($status != 0) then`
12			`exit`
13			`endif`
14
15			`# Run the NC-Verilog elaborator (build the design hierarchy)`
16	507	lampret	`ncelab -NOTIMINGCHECKS -f ncelab.args`
17	266	lampret	`if ($status != 0) then`
18			`exit`
19			`endif`
20
21			`# Run the NC-Verilog simulator (simulate the design)`
22			`ncsim -f ncsim.args && \`
23			`mv flash.log ../log && \`
24			`mv executed.log ../log && \`
25			`mv sram.log ../log`

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[/] [or1k_old/] [trunk/] [mp3/] [sim/] [run/] [run_sim] - Blame information for rev 1782