URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] [or1k_old/] [trunk/] [mp3/] [sw/] [int_test/] [int_test.cfg] - Blame information for rev 1765

Go to most recent revision | Details | Compare with Previous | View Log


section memory
  pattern = 0x00
  type = unknown /* Fastest */
 
  nmemories = 2
  device 0
    name = "RAM"
    ce = 0
    baseaddr = 0x40000000
    size = 0x00200000
    delayr = 1
    delayw = 2
  enddevice
 
  device 1
    name = "FLASH"
    ce = 1
    baseaddr = 0x00000000
    size = 0x00200000
    delayr = 10
    delayw = -1
  enddevice
end
 
section sim
  /* verbose = 1 */
  debug = 0
  profile = 0
  prof_fn = "sim.profile"
 
  history = 1
  exe_log = 0
  exe_log_fn = "executed.log"
  clkcycle = 4ns
end
 
section tick
  enabled = 1
  irq = 0
end

Line No.	Rev	Author	Line
1	592	lampret	`section memory`
2			`pattern = 0x00`
3			`type = unknown /* Fastest */`
4
5			`nmemories = 2`
6			`device 0`
7			`name = "RAM"`
8			`ce = 0`
9			`baseaddr = 0x40000000`
10			`size = 0x00200000`
11			`delayr = 1`
12			`delayw = 2`
13			`enddevice`
14
15			`device 1`
16			`name = "FLASH"`
17			`ce = 1`
18			`baseaddr = 0x00000000`
19			`size = 0x00200000`
20			`delayr = 10`
21			`delayw = -1`
22			`enddevice`
23			`end`
24
25			`section sim`
26			`/* verbose = 1 */`
27			`debug = 0`
28			`profile = 0`
29			`prof_fn = "sim.profile"`
30
31			`history = 1`
32			`exe_log = 0`
33			`exe_log_fn = "executed.log"`
34			`clkcycle = 4ns`
35			`end`
36
37			`section tick`
38			`enabled = 1`
39			`irq = 0`
40			`end`

Browse

Tools

Subversion Repositories or1k_old

[/] [or1k_old/] [trunk/] [mp3/] [sw/] [int_test/] [int_test.cfg] - Blame information for rev 1765