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[/] [or1k_old/] [trunk/] [mp3/] [sw/] [ints/] [handlers.S] - Blame information for rev 505

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Line No. Rev Author Line
1 505 lampret 
 
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#include "../support/spr_defs.h"
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        .extern _test
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        .extern _test
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        .global _main
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.global _main
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.global _buserr_except
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.global _dpf_except
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.global _ipf_except
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.global _lpint_except
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.global _align_except
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.global _illegal_except
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.global _hpint_except
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.global _dtlbmiss_except
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.global _itlbmiss_except
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.global _range_except
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.global _syscall_except
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.global _res1_except
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.global _trap_except
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.global _res2_except
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_buserr_except:
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_dpf_except:
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_ipf_except:
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_align_except:
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_illegal_except:
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_dtlbmiss_except:
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_itlbmiss_except:
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_range_except:
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_syscall_except:
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_res1_except:
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_trap_except:
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_res2_except:
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.org 0x0500
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_lpint_except:
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        l.nop
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        l.nop
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# clear TTMR[IP]
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        l.addi r4,r0,SPR_TTMR
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        l.movhi r5,hi(SPR_TTMR_RT | SPR_TTMR_IE)
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        l.addi r5,r5,233
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        l.mtspr r4,r5,0         # set TTMR
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# clear entire PICSR
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        l.movhi r4,hi(SPR_PICSR)
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        l.addi r4,r0,lo(SPR_PICSR)
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        l.addi r5,r0,0x0000
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        l.mtspr r4,r5,0         # set PICSR
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        l.nop
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        l.rfe
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        l.nop
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        l.nop
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.org 0x0800
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_hpint_except:
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        l.nop
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        l.nop
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# clear TTMR[IP]
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        l.addi r4,r0,SPR_TTMR
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        l.movhi r5,hi(SPR_TTMR_RT | SPR_TTMR_IE)
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        l.addi r5,r5,233
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        l.mtspr r4,r5,0         # set TTMR
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# clear entire PICSR
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        l.movhi r4,hi(SPR_PICSR)
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        l.addi r4,r0,lo(SPR_PICSR)
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        l.addi r5,r0,0x0000
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        l.mtspr r4,r5,0         # set PICSR
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        l.nop
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        l.rfe
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        l.nop
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        l.nop
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.org 0x2000
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_main:
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        l.nop
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        l.nop
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#
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# set tick to generate an interrupt every, let say 329 cycles
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#
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        l.addi r4,r0,SPR_TTMR
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        l.movhi r5,hi(SPR_TTMR_RT | SPR_TTMR_IE)
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        l.addi r5,r5,329
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        l.mtspr r4,r5,0         # set TTMR
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#
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# unmask all ints
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#
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        l.movhi r4,hi(SPR_PICMR)
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        l.addi r4,r0,lo(SPR_PICMR)
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        l.movhi r5,0xffff
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        l.addi r5,r5,0xffff
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        l.mtspr r4,r5,0         # set PICMR
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#
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# Enable exceptions and interrupts
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#
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        l.mfspr r5,r0,SPR_SR
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        l.ori r5,r5,SPR_SR_SUPV|SPR_SR_EXR|SPR_SR_EIR
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        l.mtspr r0,r5,SPR_SR    # set SR
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#
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# jump to main routine
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#
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        l.j _test
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        l.nop

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