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lampret |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// OR1200's definitions ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// Description ////
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//// Parameters of the OR1200 core ////
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//// ////
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//// To Do: ////
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//// - add parameters that are missing ////
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//// ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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1288 |
lampret |
// Revision 1.40 2004/05/09 19:49:04 lampret
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// Added some l.cust5 custom instructions as example
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//
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1284 |
lampret |
// Revision 1.39 2004/04/08 11:00:46 simont
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// Add support for 512B instruction cache.
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//
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53 |
1273 |
simont |
// Revision 1.38 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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//
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56 |
1267 |
lampret |
// Revision 1.35.4.6 2004/02/11 01:40:11 lampret
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// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
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1228 |
simons |
//
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59 |
1267 |
lampret |
// Revision 1.35.4.5 2004/01/15 06:46:38 markom
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// interface to debug changed; no more opselect; stb-ack protocol
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//
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// Revision 1.35.4.4 2004/01/11 22:45:46 andreje
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// Separate instruction and data QMEM decoders, QMEM acknowledge and byte-select added
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//
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// Revision 1.35.4.3 2003/12/17 13:43:38 simons
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// Exception prefix configuration changed.
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//
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// Revision 1.35.4.2 2003/12/05 00:05:03 lampret
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// Static exception prefix.
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//
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// Revision 1.35.4.1 2003/07/08 15:36:37 lampret
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// Added embedded memory QMEM.
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//
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1200 |
markom |
// Revision 1.35 2003/04/24 00:16:07 lampret
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// No functional changes. Added defines to disable implementation of multiplier/MAC
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//
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1159 |
lampret |
// Revision 1.34 2003/04/20 22:23:57 lampret
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// No functional change. Only added customization for exception vectors.
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//
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1155 |
lampret |
// Revision 1.33 2003/04/07 20:56:07 lampret
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// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description.
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//
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1139 |
lampret |
// Revision 1.32 2003/04/07 01:26:57 lampret
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// RFRAM defines comments updated. Altera LPM option added.
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//
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1132 |
lampret |
// Revision 1.31 2002/12/08 08:57:56 lampret
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// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
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//
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1104 |
lampret |
// Revision 1.30 2002/10/28 15:09:22 mohor
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// Previous check-in was done by mistake.
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//
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1078 |
mohor |
// Revision 1.29 2002/10/28 15:03:50 mohor
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93 |
1267 |
lampret |
// Signal scanb_sen renamed to scanb_en.
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1077 |
mohor |
//
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// Revision 1.28 2002/10/17 20:04:40 lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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//
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1063 |
lampret |
// Revision 1.27 2002/09/16 03:13:23 lampret
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// Removed obsolete comment.
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//
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1055 |
lampret |
// Revision 1.26 2002/09/08 05:52:16 lampret
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// Added optional l.div/l.divu insns. By default they are disabled.
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//
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1035 |
lampret |
// Revision 1.25 2002/09/07 19:16:10 lampret
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// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].
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//
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1033 |
lampret |
// Revision 1.24 2002/09/07 05:42:02 lampret
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// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
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//
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110 |
1032 |
lampret |
// Revision 1.23 2002/09/04 00:50:34 lampret
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// Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v.
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//
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113 |
1023 |
lampret |
// Revision 1.22 2002/09/03 22:28:21 lampret
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// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
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//
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116 |
1022 |
lampret |
// Revision 1.21 2002/08/22 02:18:55 lampret
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// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.
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//
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119 |
994 |
lampret |
// Revision 1.20 2002/08/18 21:59:45 lampret
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// Disable SB until it is tested
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//
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122 |
984 |
lampret |
// Revision 1.19 2002/08/18 19:53:08 lampret
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// Added store buffer.
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//
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125 |
977 |
lampret |
// Revision 1.18 2002/08/15 06:04:11 lampret
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// Fixed Xilinx trace buffer address. REported by Taylor Su.
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//
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128 |
962 |
lampret |
// Revision 1.17 2002/08/12 05:31:44 lampret
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// Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section.
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//
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131 |
944 |
lampret |
// Revision 1.16 2002/07/14 22:17:17 lampret
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// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
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//
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134 |
895 |
lampret |
// Revision 1.15 2002/06/08 16:20:21 lampret
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// Added defines for enabling generic FF based memory macro for register file.
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//
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137 |
870 |
lampret |
// Revision 1.14 2002/03/29 16:24:06 lampret
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// Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives
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//
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140 |
790 |
lampret |
// Revision 1.13 2002/03/29 15:16:55 lampret
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// Some of the warnings fixed.
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//
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143 |
788 |
lampret |
// Revision 1.12 2002/03/28 19:25:42 lampret
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// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.
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//
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146 |
778 |
lampret |
// Revision 1.11 2002/03/28 19:13:17 lampret
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// Updated defines.
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//
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149 |
776 |
lampret |
// Revision 1.10 2002/03/14 00:30:24 lampret
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// Added alternative for critical path in DU.
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//
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152 |
737 |
lampret |
// Revision 1.9 2002/03/11 01:26:26 lampret
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// Fixed async loop. Changed multiplier type for ASIC.
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//
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155 |
735 |
lampret |
// Revision 1.8 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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158 |
660 |
lampret |
// Revision 1.7 2002/02/01 19:56:54 lampret
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// Fixed combinational loops.
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//
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161 |
636 |
lampret |
// Revision 1.6 2002/01/19 14:10:22 lampret
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// Fixed OR1200_XILINX_RAM32X1D.
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//
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164 |
597 |
lampret |
// Revision 1.5 2002/01/18 07:56:00 lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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//
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167 |
589 |
lampret |
// Revision 1.4 2002/01/14 09:44:12 lampret
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// Default ASIC configuration does not sample WB inputs.
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//
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170 |
569 |
lampret |
// Revision 1.3 2002/01/08 00:51:08 lampret
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// Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be.
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//
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173 |
536 |
lampret |
// Revision 1.2 2002/01/03 21:23:03 lampret
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// Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target.
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//
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176 |
512 |
lampret |
// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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179 |
504 |
lampret |
// Revision 1.20 2001/12/04 05:02:36 lampret
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// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32
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//
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// Revision 1.19 2001/11/27 19:46:57 lampret
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// Now FPGA and ASIC target are separate.
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//
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// Revision 1.18 2001/11/23 21:42:31 simons
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// Program counter divided to PPC and NPC.
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//
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// Revision 1.17 2001/11/23 08:38:51 lampret
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// Changed DSR/DRR behavior and exception detection.
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//
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// Revision 1.16 2001/11/20 21:30:38 lampret
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// Added OR1200_REGISTERED_INPUTS.
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//
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// Revision 1.15 2001/11/19 14:29:48 simons
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// Cashes disabled.
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//
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// Revision 1.14 2001/11/13 10:02:21 lampret
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// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
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//
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// Revision 1.13 2001/11/12 01:45:40 lampret
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201 |
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// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
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//
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203 |
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// Revision 1.12 2001/11/10 03:43:57 lampret
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// Fixed exceptions.
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//
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// Revision 1.11 2001/11/02 18:57:14 lampret
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207 |
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// Modified virtual silicon instantiations.
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//
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209 |
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// Revision 1.10 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.9 2001/10/19 23:28:46 lampret
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// Fixed some synthesis warnings. Configured with caches and MMUs.
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//
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215 |
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// Revision 1.8 2001/10/14 13:12:09 lampret
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216 |
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// MP3 version.
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//
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218 |
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// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
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// no message
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220 |
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//
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221 |
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// Revision 1.3 2001/08/17 08:01:19 lampret
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222 |
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// IC enable/disable.
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223 |
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//
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224 |
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// Revision 1.2 2001/08/13 03:36:20 lampret
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225 |
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// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
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226 |
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//
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227 |
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// Revision 1.1 2001/08/09 13:39:33 lampret
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228 |
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// Major clean-up.
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//
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230 |
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// Revision 1.2 2001/07/22 03:31:54 lampret
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231 |
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// Fixed RAM's oen bug. Cache bypass under development.
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232 |
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//
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233 |
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// Revision 1.1 2001/07/20 00:46:03 lampret
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234 |
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// Development version of RTL. Libraries are missing.
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//
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236 |
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//
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237 |
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238 |
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//
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239 |
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// Dump VCD
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240 |
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//
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241 |
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//`define OR1200_VCD_DUMP
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242 |
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243 |
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//
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244 |
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// Generate debug messages during simulation
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245 |
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//
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246 |
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//`define OR1200_VERBOSE
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247 |
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248 |
1078 |
mohor |
// `define OR1200_ASIC
|
249 |
504 |
lampret |
////////////////////////////////////////////////////////
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250 |
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//
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251 |
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// Typical configuration for an ASIC
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252 |
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//
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253 |
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`ifdef OR1200_ASIC
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254 |
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255 |
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//
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256 |
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// Target ASIC memories
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257 |
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//
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258 |
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//`define OR1200_ARTISAN_SSP
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259 |
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//`define OR1200_ARTISAN_SDP
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260 |
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//`define OR1200_ARTISAN_STP
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261 |
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`define OR1200_VIRTUALSILICON_SSP
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262 |
1077 |
mohor |
//`define OR1200_VIRTUALSILICON_STP_T1
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263 |
778 |
lampret |
//`define OR1200_VIRTUALSILICON_STP_T2
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264 |
504 |
lampret |
|
265 |
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//
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266 |
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// Do not implement Data cache
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267 |
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//
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268 |
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//`define OR1200_NO_DC
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269 |
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270 |
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//
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271 |
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// Do not implement Insn cache
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272 |
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//
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273 |
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//`define OR1200_NO_IC
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274 |
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275 |
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//
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276 |
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// Do not implement Data MMU
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277 |
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//
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278 |
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//`define OR1200_NO_DMMU
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279 |
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280 |
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//
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281 |
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// Do not implement Insn MMU
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282 |
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//
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283 |
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//`define OR1200_NO_IMMU
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284 |
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|
285 |
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//
|
286 |
944 |
lampret |
// Select between ASIC optimized and generic multiplier
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287 |
504 |
lampret |
//
|
288 |
735 |
lampret |
//`define OR1200_ASIC_MULTP2_32X32
|
289 |
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`define OR1200_GENERIC_MULTP2_32X32
|
290 |
504 |
lampret |
|
291 |
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//
|
292 |
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// Size/type of insn/data cache if implemented
|
293 |
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//
|
294 |
1273 |
simont |
// `define OR1200_IC_1W_512B
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295 |
504 |
lampret |
// `define OR1200_IC_1W_4KB
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296 |
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`define OR1200_IC_1W_8KB
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297 |
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// `define OR1200_DC_1W_4KB
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298 |
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`define OR1200_DC_1W_8KB
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299 |
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300 |
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`else
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301 |
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302 |
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303 |
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/////////////////////////////////////////////////////////
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304 |
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//
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305 |
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// Typical configuration for an FPGA
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306 |
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//
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307 |
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308 |
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//
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309 |
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// Target FPGA memories
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310 |
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//
|
311 |
1132 |
lampret |
//`define OR1200_ALTERA_LPM
|
312 |
504 |
lampret |
`define OR1200_XILINX_RAMB4
|
313 |
776 |
lampret |
//`define OR1200_XILINX_RAM32X1D
|
314 |
895 |
lampret |
//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
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315 |
504 |
lampret |
|
316 |
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//
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317 |
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// Do not implement Data cache
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318 |
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//
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319 |
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//`define OR1200_NO_DC
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320 |
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321 |
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//
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322 |
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// Do not implement Insn cache
|
323 |
|
|
//
|
324 |
|
|
//`define OR1200_NO_IC
|
325 |
|
|
|
326 |
|
|
//
|
327 |
|
|
// Do not implement Data MMU
|
328 |
|
|
//
|
329 |
|
|
//`define OR1200_NO_DMMU
|
330 |
|
|
|
331 |
|
|
//
|
332 |
|
|
// Do not implement Insn MMU
|
333 |
|
|
//
|
334 |
|
|
//`define OR1200_NO_IMMU
|
335 |
|
|
|
336 |
|
|
//
|
337 |
944 |
lampret |
// Select between ASIC and generic multiplier
|
338 |
504 |
lampret |
//
|
339 |
944 |
lampret |
// (Generic seems to trigger a bug in the Cadence Ncsim simulator)
|
340 |
504 |
lampret |
//
|
341 |
|
|
//`define OR1200_ASIC_MULTP2_32X32
|
342 |
|
|
`define OR1200_GENERIC_MULTP2_32X32
|
343 |
|
|
|
344 |
|
|
//
|
345 |
|
|
// Size/type of insn/data cache if implemented
|
346 |
|
|
// (consider available FPGA memory resources)
|
347 |
|
|
//
|
348 |
1273 |
simont |
//`define OR1200_IC_1W_512B
|
349 |
504 |
lampret |
`define OR1200_IC_1W_4KB
|
350 |
|
|
//`define OR1200_IC_1W_8KB
|
351 |
|
|
`define OR1200_DC_1W_4KB
|
352 |
|
|
//`define OR1200_DC_1W_8KB
|
353 |
|
|
|
354 |
|
|
`endif
|
355 |
|
|
|
356 |
|
|
|
357 |
|
|
//////////////////////////////////////////////////////////
|
358 |
|
|
//
|
359 |
|
|
// Do not change below unless you know what you are doing
|
360 |
|
|
//
|
361 |
|
|
|
362 |
788 |
lampret |
//
|
363 |
1063 |
lampret |
// Enable RAM BIST
|
364 |
|
|
//
|
365 |
|
|
// At the moment this only works for Virtual Silicon
|
366 |
|
|
// single port RAMs. For other RAMs it has not effect.
|
367 |
|
|
// Special wrapper for VS RAMs needs to be provided
|
368 |
|
|
// with scan flops to facilitate bist scan.
|
369 |
|
|
//
|
370 |
1078 |
mohor |
//`define OR1200_BIST
|
371 |
1063 |
lampret |
|
372 |
|
|
//
|
373 |
944 |
lampret |
// Register OR1200 WISHBONE outputs
|
374 |
|
|
// (must be defined/enabled)
|
375 |
|
|
//
|
376 |
|
|
`define OR1200_REGISTERED_OUTPUTS
|
377 |
|
|
|
378 |
|
|
//
|
379 |
|
|
// Register OR1200 WISHBONE inputs
|
380 |
|
|
//
|
381 |
|
|
// (must be undefined/disabled)
|
382 |
|
|
//
|
383 |
|
|
//`define OR1200_REGISTERED_INPUTS
|
384 |
|
|
|
385 |
|
|
//
|
386 |
895 |
lampret |
// Disable bursts if they are not supported by the
|
387 |
|
|
// memory subsystem (only affect cache line fill)
|
388 |
|
|
//
|
389 |
|
|
//`define OR1200_NO_BURSTS
|
390 |
|
|
//
|
391 |
|
|
|
392 |
|
|
//
|
393 |
944 |
lampret |
// WISHBONE retry counter range
|
394 |
|
|
//
|
395 |
|
|
// 2^value range for retry counter. Retry counter
|
396 |
|
|
// is activated whenever *wb_rty_i is asserted and
|
397 |
|
|
// until retry counter expires, corresponding
|
398 |
|
|
// WISHBONE interface is deactivated.
|
399 |
|
|
//
|
400 |
|
|
// To disable retry counters and *wb_rty_i all together,
|
401 |
|
|
// undefine this macro.
|
402 |
|
|
//
|
403 |
|
|
//`define OR1200_WB_RETRY 7
|
404 |
|
|
|
405 |
|
|
//
|
406 |
1104 |
lampret |
// WISHBONE Consecutive Address Burst
|
407 |
|
|
//
|
408 |
|
|
// This was used prior to WISHBONE B3 specification
|
409 |
|
|
// to identify bursts. It is no longer needed but
|
410 |
|
|
// remains enabled for compatibility with old designs.
|
411 |
|
|
//
|
412 |
|
|
// To remove *wb_cab_o ports undefine this macro.
|
413 |
|
|
//
|
414 |
|
|
`define OR1200_WB_CAB
|
415 |
|
|
|
416 |
|
|
//
|
417 |
|
|
// WISHBONE B3 compatible interface
|
418 |
|
|
//
|
419 |
|
|
// This follows the WISHBONE B3 specification.
|
420 |
|
|
// It is not enabled by default because most
|
421 |
|
|
// designs still don't use WB b3.
|
422 |
|
|
//
|
423 |
|
|
// To enable *wb_cti_o/*wb_bte_o ports,
|
424 |
|
|
// define this macro.
|
425 |
|
|
//
|
426 |
|
|
//`define OR1200_WB_B3
|
427 |
|
|
|
428 |
|
|
//
|
429 |
788 |
lampret |
// Enable additional synthesis directives if using
|
430 |
790 |
lampret |
// _Synopsys_ synthesis tool
|
431 |
788 |
lampret |
//
|
432 |
|
|
//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
|
433 |
|
|
|
434 |
|
|
//
|
435 |
1022 |
lampret |
// Enables default statement in some case blocks
|
436 |
|
|
// and disables Synopsys synthesis directive full_case
|
437 |
|
|
//
|
438 |
|
|
// By default it is enabled. When disabled it
|
439 |
|
|
// can increase clock frequency.
|
440 |
|
|
//
|
441 |
|
|
`define OR1200_CASE_DEFAULT
|
442 |
|
|
|
443 |
|
|
//
|
444 |
504 |
lampret |
// Operand width / register file address width
|
445 |
788 |
lampret |
//
|
446 |
|
|
// (DO NOT CHANGE)
|
447 |
|
|
//
|
448 |
504 |
lampret |
`define OR1200_OPERAND_WIDTH 32
|
449 |
|
|
`define OR1200_REGFILE_ADDR_WIDTH 5
|
450 |
|
|
|
451 |
|
|
//
|
452 |
1032 |
lampret |
// l.add/l.addi/l.and and optional l.addc/l.addic
|
453 |
|
|
// also set (compare) flag when result of their
|
454 |
|
|
// operation equals zero
|
455 |
|
|
//
|
456 |
|
|
// At the time of writing this, default or32
|
457 |
|
|
// C/C++ compiler doesn't generate code that
|
458 |
|
|
// would benefit from this optimization.
|
459 |
|
|
//
|
460 |
|
|
// By default this optimization is disabled to
|
461 |
|
|
// save area.
|
462 |
|
|
//
|
463 |
|
|
//`define OR1200_ADDITIONAL_FLAG_MODIFIERS
|
464 |
|
|
|
465 |
|
|
//
|
466 |
1267 |
lampret |
// Implement l.addc/l.addic instructions
|
467 |
1032 |
lampret |
//
|
468 |
|
|
// By default implementation of l.addc/l.addic
|
469 |
1267 |
lampret |
// instructions is enabled in case you need them.
|
470 |
|
|
// If you don't use them, then disable implementation
|
471 |
|
|
// to save area.
|
472 |
1032 |
lampret |
//
|
473 |
1267 |
lampret |
`define OR1200_IMPL_ADDC
|
474 |
|
|
|
475 |
1033 |
lampret |
//
|
476 |
1267 |
lampret |
// Implement carry bit SR[CY]
|
477 |
|
|
//
|
478 |
|
|
// By default implementation of SR[CY] is enabled
|
479 |
|
|
// to be compliant with the simulator. However
|
480 |
|
|
// SR[CY] is explicitly only used by l.addc/l.addic
|
481 |
|
|
// instructions and if these two insns are not
|
482 |
|
|
// implemented there is not much point having SR[CY].
|
483 |
|
|
//
|
484 |
|
|
`define OR1200_IMPL_CY
|
485 |
1032 |
lampret |
|
486 |
|
|
//
|
487 |
1035 |
lampret |
// Implement optional l.div/l.divu instructions
|
488 |
|
|
//
|
489 |
|
|
// By default divide instructions are not implemented
|
490 |
|
|
// to save area and increase clock frequency. or32 C/C++
|
491 |
|
|
// compiler can use soft library for division.
|
492 |
|
|
//
|
493 |
1159 |
lampret |
// To implement divide, multiplier needs to be implemented.
|
494 |
|
|
//
|
495 |
1035 |
lampret |
//`define OR1200_IMPL_DIV
|
496 |
|
|
|
497 |
|
|
//
|
498 |
504 |
lampret |
// Implement rotate in the ALU
|
499 |
|
|
//
|
500 |
1032 |
lampret |
// At the time of writing this, or32
|
501 |
|
|
// C/C++ compiler doesn't generate rotate
|
502 |
|
|
// instructions. However or32 assembler
|
503 |
|
|
// can assemble code that uses rotate insn.
|
504 |
|
|
// This means that rotate instructions
|
505 |
|
|
// must be used manually inserted.
|
506 |
|
|
//
|
507 |
|
|
// By default implementation of rotate
|
508 |
|
|
// is disabled to save area and increase
|
509 |
|
|
// clock frequency.
|
510 |
|
|
//
|
511 |
504 |
lampret |
//`define OR1200_IMPL_ALU_ROTATE
|
512 |
|
|
|
513 |
|
|
//
|
514 |
|
|
// Type of ALU compare to implement
|
515 |
|
|
//
|
516 |
1032 |
lampret |
// Try either one to find what yields
|
517 |
|
|
// higher clock frequencyin your case.
|
518 |
|
|
//
|
519 |
504 |
lampret |
//`define OR1200_IMPL_ALU_COMP1
|
520 |
|
|
`define OR1200_IMPL_ALU_COMP2
|
521 |
|
|
|
522 |
|
|
//
|
523 |
1159 |
lampret |
// Implement multiplier
|
524 |
504 |
lampret |
//
|
525 |
1159 |
lampret |
// By default multiplier is implemented
|
526 |
|
|
//
|
527 |
|
|
`define OR1200_MULT_IMPLEMENTED
|
528 |
|
|
|
529 |
|
|
//
|
530 |
|
|
// Implement multiply-and-accumulate
|
531 |
|
|
//
|
532 |
|
|
// By default MAC is implemented. To
|
533 |
|
|
// implement MAC, multiplier needs to be
|
534 |
|
|
// implemented.
|
535 |
|
|
//
|
536 |
|
|
`define OR1200_MAC_IMPLEMENTED
|
537 |
|
|
|
538 |
|
|
//
|
539 |
|
|
// Low power, slower multiplier
|
540 |
|
|
//
|
541 |
|
|
// Select between low-power (larger) multiplier
|
542 |
|
|
// and faster multiplier. The actual difference
|
543 |
|
|
// is only AND logic that prevents distribution
|
544 |
|
|
// of operands into the multiplier when instruction
|
545 |
|
|
// in execution is not multiply instruction
|
546 |
|
|
//
|
547 |
776 |
lampret |
//`define OR1200_LOWPWR_MULT
|
548 |
504 |
lampret |
|
549 |
|
|
//
|
550 |
1139 |
lampret |
// Clock ratio RISC clock versus WB clock
|
551 |
504 |
lampret |
//
|
552 |
1139 |
lampret |
// If you plan to run WB:RISC clock fixed to 1:1, disable
|
553 |
|
|
// both defines
|
554 |
504 |
lampret |
//
|
555 |
1139 |
lampret |
// For WB:RISC 1:2 or 1:1, enable OR1200_CLKDIV_2_SUPPORTED
|
556 |
|
|
// and use clmode to set ratio
|
557 |
|
|
//
|
558 |
|
|
// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use
|
559 |
|
|
// clmode to set ratio
|
560 |
|
|
//
|
561 |
504 |
lampret |
`define OR1200_CLKDIV_2_SUPPORTED
|
562 |
776 |
lampret |
//`define OR1200_CLKDIV_4_SUPPORTED
|
563 |
504 |
lampret |
|
564 |
|
|
//
|
565 |
|
|
// Type of register file RAM
|
566 |
|
|
//
|
567 |
1132 |
lampret |
// Memory macro w/ two ports (see or1200_tpram_32x32.v)
|
568 |
504 |
lampret |
// `define OR1200_RFRAM_TWOPORT
|
569 |
870 |
lampret |
//
|
570 |
1132 |
lampret |
// Memory macro dual port (see or1200_dpram_32x32.v)
|
571 |
870 |
lampret |
`define OR1200_RFRAM_DUALPORT
|
572 |
|
|
//
|
573 |
1132 |
lampret |
// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
|
574 |
|
|
//`define OR1200_RFRAM_GENERIC
|
575 |
504 |
lampret |
|
576 |
|
|
//
|
577 |
776 |
lampret |
// Type of mem2reg aligner to implement.
|
578 |
504 |
lampret |
//
|
579 |
776 |
lampret |
// Once OR1200_IMPL_MEM2REG2 yielded faster
|
580 |
|
|
// circuit, however with today tools it will
|
581 |
|
|
// most probably give you slower circuit.
|
582 |
|
|
//
|
583 |
|
|
`define OR1200_IMPL_MEM2REG1
|
584 |
|
|
//`define OR1200_IMPL_MEM2REG2
|
585 |
504 |
lampret |
|
586 |
|
|
//
|
587 |
|
|
// ALUOPs
|
588 |
|
|
//
|
589 |
|
|
`define OR1200_ALUOP_WIDTH 4
|
590 |
636 |
lampret |
`define OR1200_ALUOP_NOP 4'd4
|
591 |
504 |
lampret |
/* Order defined by arith insns that have two source operands both in regs
|
592 |
|
|
(see binutils/include/opcode/or32.h) */
|
593 |
|
|
`define OR1200_ALUOP_ADD 4'd0
|
594 |
|
|
`define OR1200_ALUOP_ADDC 4'd1
|
595 |
|
|
`define OR1200_ALUOP_SUB 4'd2
|
596 |
|
|
`define OR1200_ALUOP_AND 4'd3
|
597 |
636 |
lampret |
`define OR1200_ALUOP_OR 4'd4
|
598 |
504 |
lampret |
`define OR1200_ALUOP_XOR 4'd5
|
599 |
|
|
`define OR1200_ALUOP_MUL 4'd6
|
600 |
1284 |
lampret |
`define OR1200_ALUOP_CUST5 4'd7
|
601 |
504 |
lampret |
`define OR1200_ALUOP_SHROT 4'd8
|
602 |
|
|
`define OR1200_ALUOP_DIV 4'd9
|
603 |
|
|
`define OR1200_ALUOP_DIVU 4'd10
|
604 |
|
|
/* Order not specifically defined. */
|
605 |
|
|
`define OR1200_ALUOP_IMM 4'd11
|
606 |
|
|
`define OR1200_ALUOP_MOVHI 4'd12
|
607 |
|
|
`define OR1200_ALUOP_COMP 4'd13
|
608 |
|
|
`define OR1200_ALUOP_MTSR 4'd14
|
609 |
|
|
`define OR1200_ALUOP_MFSR 4'd15
|
610 |
|
|
|
611 |
|
|
//
|
612 |
|
|
// MACOPs
|
613 |
|
|
//
|
614 |
|
|
`define OR1200_MACOP_WIDTH 2
|
615 |
|
|
`define OR1200_MACOP_NOP 2'b00
|
616 |
|
|
`define OR1200_MACOP_MAC 2'b01
|
617 |
|
|
`define OR1200_MACOP_MSB 2'b10
|
618 |
|
|
|
619 |
|
|
//
|
620 |
|
|
// Shift/rotate ops
|
621 |
|
|
//
|
622 |
|
|
`define OR1200_SHROTOP_WIDTH 2
|
623 |
|
|
`define OR1200_SHROTOP_NOP 2'd0
|
624 |
|
|
`define OR1200_SHROTOP_SLL 2'd0
|
625 |
|
|
`define OR1200_SHROTOP_SRL 2'd1
|
626 |
|
|
`define OR1200_SHROTOP_SRA 2'd2
|
627 |
|
|
`define OR1200_SHROTOP_ROR 2'd3
|
628 |
|
|
|
629 |
|
|
// Execution cycles per instruction
|
630 |
|
|
`define OR1200_MULTICYCLE_WIDTH 2
|
631 |
|
|
`define OR1200_ONE_CYCLE 2'd0
|
632 |
|
|
`define OR1200_TWO_CYCLES 2'd1
|
633 |
|
|
|
634 |
|
|
// Operand MUX selects
|
635 |
|
|
`define OR1200_SEL_WIDTH 2
|
636 |
|
|
`define OR1200_SEL_RF 2'd0
|
637 |
|
|
`define OR1200_SEL_IMM 2'd1
|
638 |
|
|
`define OR1200_SEL_EX_FORW 2'd2
|
639 |
|
|
`define OR1200_SEL_WB_FORW 2'd3
|
640 |
|
|
|
641 |
|
|
//
|
642 |
|
|
// BRANCHOPs
|
643 |
|
|
//
|
644 |
|
|
`define OR1200_BRANCHOP_WIDTH 3
|
645 |
|
|
`define OR1200_BRANCHOP_NOP 3'd0
|
646 |
|
|
`define OR1200_BRANCHOP_J 3'd1
|
647 |
|
|
`define OR1200_BRANCHOP_JR 3'd2
|
648 |
|
|
`define OR1200_BRANCHOP_BAL 3'd3
|
649 |
|
|
`define OR1200_BRANCHOP_BF 3'd4
|
650 |
|
|
`define OR1200_BRANCHOP_BNF 3'd5
|
651 |
|
|
`define OR1200_BRANCHOP_RFE 3'd6
|
652 |
|
|
|
653 |
|
|
//
|
654 |
|
|
// LSUOPs
|
655 |
|
|
//
|
656 |
|
|
// Bit 0: sign extend
|
657 |
|
|
// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword
|
658 |
|
|
// Bit 3: 0 load, 1 store
|
659 |
|
|
`define OR1200_LSUOP_WIDTH 4
|
660 |
|
|
`define OR1200_LSUOP_NOP 4'b0000
|
661 |
|
|
`define OR1200_LSUOP_LBZ 4'b0010
|
662 |
|
|
`define OR1200_LSUOP_LBS 4'b0011
|
663 |
|
|
`define OR1200_LSUOP_LHZ 4'b0100
|
664 |
|
|
`define OR1200_LSUOP_LHS 4'b0101
|
665 |
|
|
`define OR1200_LSUOP_LWZ 4'b0110
|
666 |
|
|
`define OR1200_LSUOP_LWS 4'b0111
|
667 |
|
|
`define OR1200_LSUOP_LD 4'b0001
|
668 |
|
|
`define OR1200_LSUOP_SD 4'b1000
|
669 |
|
|
`define OR1200_LSUOP_SB 4'b1010
|
670 |
|
|
`define OR1200_LSUOP_SH 4'b1100
|
671 |
|
|
`define OR1200_LSUOP_SW 4'b1110
|
672 |
|
|
|
673 |
|
|
// FETCHOPs
|
674 |
|
|
`define OR1200_FETCHOP_WIDTH 1
|
675 |
|
|
`define OR1200_FETCHOP_NOP 1'b0
|
676 |
|
|
`define OR1200_FETCHOP_LW 1'b1
|
677 |
|
|
|
678 |
|
|
//
|
679 |
|
|
// Register File Write-Back OPs
|
680 |
|
|
//
|
681 |
|
|
// Bit 0: register file write enable
|
682 |
|
|
// Bits 2-1: write-back mux selects
|
683 |
|
|
`define OR1200_RFWBOP_WIDTH 3
|
684 |
|
|
`define OR1200_RFWBOP_NOP 3'b000
|
685 |
|
|
`define OR1200_RFWBOP_ALU 3'b001
|
686 |
|
|
`define OR1200_RFWBOP_LSU 3'b011
|
687 |
|
|
`define OR1200_RFWBOP_SPRS 3'b101
|
688 |
|
|
`define OR1200_RFWBOP_LR 3'b111
|
689 |
|
|
|
690 |
|
|
// Compare instructions
|
691 |
|
|
`define OR1200_COP_SFEQ 3'b000
|
692 |
|
|
`define OR1200_COP_SFNE 3'b001
|
693 |
|
|
`define OR1200_COP_SFGT 3'b010
|
694 |
|
|
`define OR1200_COP_SFGE 3'b011
|
695 |
|
|
`define OR1200_COP_SFLT 3'b100
|
696 |
|
|
`define OR1200_COP_SFLE 3'b101
|
697 |
|
|
`define OR1200_COP_X 3'b111
|
698 |
|
|
`define OR1200_SIGNED_COMPARE 'd3
|
699 |
|
|
`define OR1200_COMPOP_WIDTH 4
|
700 |
|
|
|
701 |
|
|
//
|
702 |
|
|
// TAGs for instruction bus
|
703 |
|
|
//
|
704 |
|
|
`define OR1200_ITAG_IDLE 4'h0 // idle bus
|
705 |
|
|
`define OR1200_ITAG_NI 4'h1 // normal insn
|
706 |
|
|
`define OR1200_ITAG_BE 4'hb // Bus error exception
|
707 |
|
|
`define OR1200_ITAG_PE 4'hc // Page fault exception
|
708 |
|
|
`define OR1200_ITAG_TE 4'hd // TLB miss exception
|
709 |
|
|
|
710 |
|
|
//
|
711 |
|
|
// TAGs for data bus
|
712 |
|
|
//
|
713 |
|
|
`define OR1200_DTAG_IDLE 4'h0 // idle bus
|
714 |
|
|
`define OR1200_DTAG_ND 4'h1 // normal data
|
715 |
|
|
`define OR1200_DTAG_AE 4'ha // Alignment exception
|
716 |
|
|
`define OR1200_DTAG_BE 4'hb // Bus error exception
|
717 |
|
|
`define OR1200_DTAG_PE 4'hc // Page fault exception
|
718 |
|
|
`define OR1200_DTAG_TE 4'hd // TLB miss exception
|
719 |
|
|
|
720 |
|
|
|
721 |
|
|
//////////////////////////////////////////////
|
722 |
|
|
//
|
723 |
|
|
// ORBIS32 ISA specifics
|
724 |
|
|
//
|
725 |
|
|
|
726 |
|
|
// SHROT_OP position in machine word
|
727 |
|
|
`define OR1200_SHROTOP_POS 7:6
|
728 |
|
|
|
729 |
|
|
// ALU instructions multicycle field in machine word
|
730 |
|
|
`define OR1200_ALUMCYC_POS 9:8
|
731 |
|
|
|
732 |
|
|
//
|
733 |
|
|
// Instruction opcode groups (basic)
|
734 |
|
|
//
|
735 |
|
|
`define OR1200_OR32_J 6'b000000
|
736 |
|
|
`define OR1200_OR32_JAL 6'b000001
|
737 |
|
|
`define OR1200_OR32_BNF 6'b000011
|
738 |
|
|
`define OR1200_OR32_BF 6'b000100
|
739 |
|
|
`define OR1200_OR32_NOP 6'b000101
|
740 |
|
|
`define OR1200_OR32_MOVHI 6'b000110
|
741 |
|
|
`define OR1200_OR32_XSYNC 6'b001000
|
742 |
|
|
`define OR1200_OR32_RFE 6'b001001
|
743 |
|
|
/* */
|
744 |
|
|
`define OR1200_OR32_JR 6'b010001
|
745 |
|
|
`define OR1200_OR32_JALR 6'b010010
|
746 |
|
|
`define OR1200_OR32_MACI 6'b010011
|
747 |
|
|
/* */
|
748 |
|
|
`define OR1200_OR32_LWZ 6'b100001
|
749 |
|
|
`define OR1200_OR32_LBZ 6'b100011
|
750 |
|
|
`define OR1200_OR32_LBS 6'b100100
|
751 |
|
|
`define OR1200_OR32_LHZ 6'b100101
|
752 |
|
|
`define OR1200_OR32_LHS 6'b100110
|
753 |
|
|
`define OR1200_OR32_ADDI 6'b100111
|
754 |
|
|
`define OR1200_OR32_ADDIC 6'b101000
|
755 |
|
|
`define OR1200_OR32_ANDI 6'b101001
|
756 |
|
|
`define OR1200_OR32_ORI 6'b101010
|
757 |
|
|
`define OR1200_OR32_XORI 6'b101011
|
758 |
|
|
`define OR1200_OR32_MULI 6'b101100
|
759 |
|
|
`define OR1200_OR32_MFSPR 6'b101101
|
760 |
|
|
`define OR1200_OR32_SH_ROTI 6'b101110
|
761 |
|
|
`define OR1200_OR32_SFXXI 6'b101111
|
762 |
|
|
/* */
|
763 |
|
|
`define OR1200_OR32_MTSPR 6'b110000
|
764 |
|
|
`define OR1200_OR32_MACMSB 6'b110001
|
765 |
|
|
/* */
|
766 |
|
|
`define OR1200_OR32_SW 6'b110101
|
767 |
|
|
`define OR1200_OR32_SB 6'b110110
|
768 |
|
|
`define OR1200_OR32_SH 6'b110111
|
769 |
|
|
`define OR1200_OR32_ALU 6'b111000
|
770 |
|
|
`define OR1200_OR32_SFXX 6'b111001
|
771 |
1288 |
lampret |
//`define OR1200_OR32_CUST5 6'b111100
|
772 |
504 |
lampret |
|
773 |
|
|
|
774 |
|
|
/////////////////////////////////////////////////////
|
775 |
|
|
//
|
776 |
|
|
// Exceptions
|
777 |
|
|
//
|
778 |
1155 |
lampret |
|
779 |
|
|
//
|
780 |
|
|
// Exception vectors per OR1K architecture:
|
781 |
1228 |
simons |
// 0xPPPPP100 - reset
|
782 |
|
|
// 0xPPPPP200 - bus error
|
783 |
1155 |
lampret |
// ... etc
|
784 |
|
|
// where P represents exception prefix.
|
785 |
|
|
//
|
786 |
|
|
// Exception vectors can be customized as per
|
787 |
|
|
// the following formula:
|
788 |
1228 |
simons |
// 0xPPPPPNVV - exception N
|
789 |
1155 |
lampret |
//
|
790 |
|
|
// P represents exception prefix
|
791 |
|
|
// N represents exception N
|
792 |
|
|
// VV represents length of the individual vector space,
|
793 |
|
|
// usually it is 8 bits wide and starts with all bits zero
|
794 |
|
|
//
|
795 |
|
|
|
796 |
|
|
//
|
797 |
1228 |
simons |
// PPPPP and VV parts
|
798 |
1155 |
lampret |
//
|
799 |
1228 |
simons |
// Sum of these two defines needs to be 28
|
800 |
1155 |
lampret |
//
|
801 |
1228 |
simons |
`define OR1200_EXCEPT_EPH0_P 20'h00000
|
802 |
|
|
`define OR1200_EXCEPT_EPH1_P 20'hF0000
|
803 |
|
|
`define OR1200_EXCEPT_V 8'h00
|
804 |
1155 |
lampret |
|
805 |
|
|
//
|
806 |
|
|
// N part width
|
807 |
|
|
//
|
808 |
504 |
lampret |
`define OR1200_EXCEPT_WIDTH 4
|
809 |
1155 |
lampret |
|
810 |
|
|
//
|
811 |
|
|
// Definition of exception vectors
|
812 |
|
|
//
|
813 |
|
|
// To avoid implementation of a certain exception,
|
814 |
|
|
// simply comment out corresponding line
|
815 |
|
|
//
|
816 |
504 |
lampret |
`define OR1200_EXCEPT_UNUSED `OR1200_EXCEPT_WIDTH'hf
|
817 |
|
|
`define OR1200_EXCEPT_TRAP `OR1200_EXCEPT_WIDTH'he
|
818 |
|
|
`define OR1200_EXCEPT_BREAK `OR1200_EXCEPT_WIDTH'hd
|
819 |
|
|
`define OR1200_EXCEPT_SYSCALL `OR1200_EXCEPT_WIDTH'hc
|
820 |
|
|
`define OR1200_EXCEPT_RANGE `OR1200_EXCEPT_WIDTH'hb
|
821 |
|
|
`define OR1200_EXCEPT_ITLBMISS `OR1200_EXCEPT_WIDTH'ha
|
822 |
|
|
`define OR1200_EXCEPT_DTLBMISS `OR1200_EXCEPT_WIDTH'h9
|
823 |
589 |
lampret |
`define OR1200_EXCEPT_INT `OR1200_EXCEPT_WIDTH'h8
|
824 |
504 |
lampret |
`define OR1200_EXCEPT_ILLEGAL `OR1200_EXCEPT_WIDTH'h7
|
825 |
|
|
`define OR1200_EXCEPT_ALIGN `OR1200_EXCEPT_WIDTH'h6
|
826 |
589 |
lampret |
`define OR1200_EXCEPT_TICK `OR1200_EXCEPT_WIDTH'h5
|
827 |
504 |
lampret |
`define OR1200_EXCEPT_IPF `OR1200_EXCEPT_WIDTH'h4
|
828 |
|
|
`define OR1200_EXCEPT_DPF `OR1200_EXCEPT_WIDTH'h3
|
829 |
|
|
`define OR1200_EXCEPT_BUSERR `OR1200_EXCEPT_WIDTH'h2
|
830 |
|
|
`define OR1200_EXCEPT_RESET `OR1200_EXCEPT_WIDTH'h1
|
831 |
|
|
`define OR1200_EXCEPT_NONE `OR1200_EXCEPT_WIDTH'h0
|
832 |
|
|
|
833 |
|
|
|
834 |
|
|
/////////////////////////////////////////////////////
|
835 |
|
|
//
|
836 |
|
|
// SPR groups
|
837 |
|
|
//
|
838 |
|
|
|
839 |
|
|
// Bits that define the group
|
840 |
|
|
`define OR1200_SPR_GROUP_BITS 15:11
|
841 |
|
|
|
842 |
|
|
// Width of the group bits
|
843 |
|
|
`define OR1200_SPR_GROUP_WIDTH 5
|
844 |
|
|
|
845 |
|
|
// Bits that define offset inside the group
|
846 |
|
|
`define OR1200_SPR_OFS_BITS 10:0
|
847 |
|
|
|
848 |
|
|
// List of groups
|
849 |
|
|
`define OR1200_SPR_GROUP_SYS 5'd00
|
850 |
|
|
`define OR1200_SPR_GROUP_DMMU 5'd01
|
851 |
|
|
`define OR1200_SPR_GROUP_IMMU 5'd02
|
852 |
|
|
`define OR1200_SPR_GROUP_DC 5'd03
|
853 |
|
|
`define OR1200_SPR_GROUP_IC 5'd04
|
854 |
|
|
`define OR1200_SPR_GROUP_MAC 5'd05
|
855 |
|
|
`define OR1200_SPR_GROUP_DU 5'd06
|
856 |
|
|
`define OR1200_SPR_GROUP_PM 5'd08
|
857 |
|
|
`define OR1200_SPR_GROUP_PIC 5'd09
|
858 |
|
|
`define OR1200_SPR_GROUP_TT 5'd10
|
859 |
|
|
|
860 |
|
|
|
861 |
|
|
/////////////////////////////////////////////////////
|
862 |
|
|
//
|
863 |
|
|
// System group
|
864 |
|
|
//
|
865 |
|
|
|
866 |
|
|
//
|
867 |
|
|
// System registers
|
868 |
|
|
//
|
869 |
|
|
`define OR1200_SPR_CFGR 7'd0
|
870 |
|
|
`define OR1200_SPR_RF 6'd32 // 1024 >> 5
|
871 |
|
|
`define OR1200_SPR_NPC 11'd16
|
872 |
|
|
`define OR1200_SPR_SR 11'd17
|
873 |
|
|
`define OR1200_SPR_PPC 11'd18
|
874 |
|
|
`define OR1200_SPR_EPCR 11'd32
|
875 |
|
|
`define OR1200_SPR_EEAR 11'd48
|
876 |
|
|
`define OR1200_SPR_ESR 11'd64
|
877 |
|
|
|
878 |
|
|
//
|
879 |
|
|
// SR bits
|
880 |
|
|
//
|
881 |
589 |
lampret |
`define OR1200_SR_WIDTH 16
|
882 |
|
|
`define OR1200_SR_SM 0
|
883 |
|
|
`define OR1200_SR_TEE 1
|
884 |
|
|
`define OR1200_SR_IEE 2
|
885 |
504 |
lampret |
`define OR1200_SR_DCE 3
|
886 |
|
|
`define OR1200_SR_ICE 4
|
887 |
|
|
`define OR1200_SR_DME 5
|
888 |
|
|
`define OR1200_SR_IME 6
|
889 |
|
|
`define OR1200_SR_LEE 7
|
890 |
|
|
`define OR1200_SR_CE 8
|
891 |
|
|
`define OR1200_SR_F 9
|
892 |
589 |
lampret |
`define OR1200_SR_CY 10 // Unused
|
893 |
|
|
`define OR1200_SR_OV 11 // Unused
|
894 |
|
|
`define OR1200_SR_OVE 12 // Unused
|
895 |
|
|
`define OR1200_SR_DSX 13 // Unused
|
896 |
|
|
`define OR1200_SR_EPH 14
|
897 |
|
|
`define OR1200_SR_FO 15
|
898 |
|
|
`define OR1200_SR_CID 31:28 // Unimplemented
|
899 |
504 |
lampret |
|
900 |
1267 |
lampret |
//
|
901 |
504 |
lampret |
// Bits that define offset inside the group
|
902 |
1267 |
lampret |
//
|
903 |
504 |
lampret |
`define OR1200_SPROFS_BITS 10:0
|
904 |
|
|
|
905 |
1228 |
simons |
//
|
906 |
|
|
// Default Exception Prefix
|
907 |
|
|
//
|
908 |
|
|
// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
|
909 |
|
|
// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
|
910 |
|
|
//
|
911 |
|
|
`define OR1200_SR_EPH_DEF 1'b0
|
912 |
504 |
lampret |
|
913 |
|
|
/////////////////////////////////////////////////////
|
914 |
|
|
//
|
915 |
|
|
// Power Management (PM)
|
916 |
|
|
//
|
917 |
|
|
|
918 |
|
|
// Define it if you want PM implemented
|
919 |
|
|
`define OR1200_PM_IMPLEMENTED
|
920 |
|
|
|
921 |
|
|
// Bit positions inside PMR (don't change)
|
922 |
|
|
`define OR1200_PM_PMR_SDF 3:0
|
923 |
|
|
`define OR1200_PM_PMR_DME 4
|
924 |
|
|
`define OR1200_PM_PMR_SME 5
|
925 |
|
|
`define OR1200_PM_PMR_DCGE 6
|
926 |
|
|
`define OR1200_PM_PMR_UNUSED 31:7
|
927 |
|
|
|
928 |
|
|
// PMR offset inside PM group of registers
|
929 |
|
|
`define OR1200_PM_OFS_PMR 11'b0
|
930 |
|
|
|
931 |
|
|
// PM group
|
932 |
|
|
`define OR1200_SPRGRP_PM 5'd8
|
933 |
|
|
|
934 |
|
|
// Define if PMR can be read/written at any address inside PM group
|
935 |
|
|
`define OR1200_PM_PARTIAL_DECODING
|
936 |
|
|
|
937 |
|
|
// Define if reading PMR is allowed
|
938 |
|
|
`define OR1200_PM_READREGS
|
939 |
|
|
|
940 |
|
|
// Define if unused PMR bits should be zero
|
941 |
|
|
`define OR1200_PM_UNUSED_ZERO
|
942 |
|
|
|
943 |
|
|
|
944 |
|
|
/////////////////////////////////////////////////////
|
945 |
|
|
//
|
946 |
|
|
// Debug Unit (DU)
|
947 |
|
|
//
|
948 |
|
|
|
949 |
|
|
// Define it if you want DU implemented
|
950 |
|
|
`define OR1200_DU_IMPLEMENTED
|
951 |
|
|
|
952 |
1267 |
lampret |
//
|
953 |
|
|
// Define if you want HW Breakpoints
|
954 |
|
|
// (if HW breakpoints are not implemented
|
955 |
|
|
// only default software trapping is
|
956 |
|
|
// possible with l.trap insn - this is
|
957 |
|
|
// however already enough for use
|
958 |
|
|
// with or32 gdb)
|
959 |
|
|
//
|
960 |
|
|
//`define OR1200_DU_HWBKPTS
|
961 |
|
|
|
962 |
|
|
// Number of DVR/DCR pairs if HW breakpoints enabled
|
963 |
|
|
`define OR1200_DU_DVRDCR_PAIRS 8
|
964 |
|
|
|
965 |
895 |
lampret |
// Define if you want trace buffer
|
966 |
|
|
// (for now only available for Xilinx Virtex FPGAs)
|
967 |
962 |
lampret |
`ifdef OR1200_ASIC
|
968 |
|
|
`else
|
969 |
895 |
lampret |
`define OR1200_DU_TB_IMPLEMENTED
|
970 |
962 |
lampret |
`endif
|
971 |
895 |
lampret |
|
972 |
1267 |
lampret |
//
|
973 |
504 |
lampret |
// Address offsets of DU registers inside DU group
|
974 |
1267 |
lampret |
//
|
975 |
|
|
// To not implement a register, do not define its address
|
976 |
|
|
//
|
977 |
|
|
`ifdef OR1200_DU_HWBKPTS
|
978 |
|
|
`define OR1200_DU_DVR0 11'd0
|
979 |
|
|
`define OR1200_DU_DVR1 11'd1
|
980 |
|
|
`define OR1200_DU_DVR2 11'd2
|
981 |
|
|
`define OR1200_DU_DVR3 11'd3
|
982 |
|
|
`define OR1200_DU_DVR4 11'd4
|
983 |
|
|
`define OR1200_DU_DVR5 11'd5
|
984 |
|
|
`define OR1200_DU_DVR6 11'd6
|
985 |
|
|
`define OR1200_DU_DVR7 11'd7
|
986 |
|
|
`define OR1200_DU_DCR0 11'd8
|
987 |
|
|
`define OR1200_DU_DCR1 11'd9
|
988 |
|
|
`define OR1200_DU_DCR2 11'd10
|
989 |
|
|
`define OR1200_DU_DCR3 11'd11
|
990 |
|
|
`define OR1200_DU_DCR4 11'd12
|
991 |
|
|
`define OR1200_DU_DCR5 11'd13
|
992 |
|
|
`define OR1200_DU_DCR6 11'd14
|
993 |
|
|
`define OR1200_DU_DCR7 11'd15
|
994 |
|
|
`endif
|
995 |
|
|
`define OR1200_DU_DMR1 11'd16
|
996 |
|
|
`ifdef OR1200_DU_HWBKPTS
|
997 |
|
|
`define OR1200_DU_DMR2 11'd17
|
998 |
|
|
`define OR1200_DU_DWCR0 11'd18
|
999 |
|
|
`define OR1200_DU_DWCR1 11'd19
|
1000 |
|
|
`endif
|
1001 |
|
|
`define OR1200_DU_DSR 11'd20
|
1002 |
|
|
`define OR1200_DU_DRR 11'd21
|
1003 |
|
|
`ifdef OR1200_DU_TB_IMPLEMENTED
|
1004 |
|
|
`define OR1200_DU_TBADR 11'h0ff
|
1005 |
|
|
`define OR1200_DU_TBIA 11'h1xx
|
1006 |
|
|
`define OR1200_DU_TBIM 11'h2xx
|
1007 |
|
|
`define OR1200_DU_TBAR 11'h3xx
|
1008 |
|
|
`define OR1200_DU_TBTS 11'h4xx
|
1009 |
|
|
`endif
|
1010 |
504 |
lampret |
|
1011 |
|
|
// Position of offset bits inside SPR address
|
1012 |
1267 |
lampret |
`define OR1200_DUOFS_BITS 10:0
|
1013 |
504 |
lampret |
|
1014 |
1267 |
lampret |
// DCR bits
|
1015 |
|
|
`define OR1200_DU_DCR_DP 0
|
1016 |
|
|
`define OR1200_DU_DCR_CC 3:1
|
1017 |
|
|
`define OR1200_DU_DCR_SC 4
|
1018 |
|
|
`define OR1200_DU_DCR_CT 7:5
|
1019 |
504 |
lampret |
|
1020 |
|
|
// DMR1 bits
|
1021 |
1267 |
lampret |
`define OR1200_DU_DMR1_CW0 1:0
|
1022 |
|
|
`define OR1200_DU_DMR1_CW1 3:2
|
1023 |
|
|
`define OR1200_DU_DMR1_CW2 5:4
|
1024 |
|
|
`define OR1200_DU_DMR1_CW3 7:6
|
1025 |
|
|
`define OR1200_DU_DMR1_CW4 9:8
|
1026 |
|
|
`define OR1200_DU_DMR1_CW5 11:10
|
1027 |
|
|
`define OR1200_DU_DMR1_CW6 13:12
|
1028 |
|
|
`define OR1200_DU_DMR1_CW7 15:14
|
1029 |
|
|
`define OR1200_DU_DMR1_CW8 17:16
|
1030 |
|
|
`define OR1200_DU_DMR1_CW9 19:18
|
1031 |
|
|
`define OR1200_DU_DMR1_CW10 21:20
|
1032 |
|
|
`define OR1200_DU_DMR1_ST 22
|
1033 |
|
|
`define OR1200_DU_DMR1_BT 23
|
1034 |
|
|
`define OR1200_DU_DMR1_DXFW 24
|
1035 |
|
|
`define OR1200_DU_DMR1_ETE 25
|
1036 |
504 |
lampret |
|
1037 |
1267 |
lampret |
// DMR2 bits
|
1038 |
|
|
`define OR1200_DU_DMR2_WCE0 0
|
1039 |
|
|
`define OR1200_DU_DMR2_WCE1 1
|
1040 |
|
|
`define OR1200_DU_DMR2_AWTC 12:2
|
1041 |
|
|
`define OR1200_DU_DMR2_WGB 23:13
|
1042 |
|
|
|
1043 |
|
|
// DWCR bits
|
1044 |
|
|
`define OR1200_DU_DWCR_COUNT 15:0
|
1045 |
|
|
`define OR1200_DU_DWCR_MATCH 31:16
|
1046 |
|
|
|
1047 |
504 |
lampret |
// DSR bits
|
1048 |
|
|
`define OR1200_DU_DSR_WIDTH 14
|
1049 |
|
|
`define OR1200_DU_DSR_RSTE 0
|
1050 |
|
|
`define OR1200_DU_DSR_BUSEE 1
|
1051 |
|
|
`define OR1200_DU_DSR_DPFE 2
|
1052 |
|
|
`define OR1200_DU_DSR_IPFE 3
|
1053 |
589 |
lampret |
`define OR1200_DU_DSR_TTE 4
|
1054 |
504 |
lampret |
`define OR1200_DU_DSR_AE 5
|
1055 |
|
|
`define OR1200_DU_DSR_IIE 6
|
1056 |
589 |
lampret |
`define OR1200_DU_DSR_IE 7
|
1057 |
504 |
lampret |
`define OR1200_DU_DSR_DME 8
|
1058 |
|
|
`define OR1200_DU_DSR_IME 9
|
1059 |
|
|
`define OR1200_DU_DSR_RE 10
|
1060 |
|
|
`define OR1200_DU_DSR_SCE 11
|
1061 |
|
|
`define OR1200_DU_DSR_BE 12
|
1062 |
|
|
`define OR1200_DU_DSR_TE 13
|
1063 |
|
|
|
1064 |
|
|
// DRR bits
|
1065 |
|
|
`define OR1200_DU_DRR_RSTE 0
|
1066 |
|
|
`define OR1200_DU_DRR_BUSEE 1
|
1067 |
|
|
`define OR1200_DU_DRR_DPFE 2
|
1068 |
|
|
`define OR1200_DU_DRR_IPFE 3
|
1069 |
589 |
lampret |
`define OR1200_DU_DRR_TTE 4
|
1070 |
504 |
lampret |
`define OR1200_DU_DRR_AE 5
|
1071 |
|
|
`define OR1200_DU_DRR_IIE 6
|
1072 |
589 |
lampret |
`define OR1200_DU_DRR_IE 7
|
1073 |
504 |
lampret |
`define OR1200_DU_DRR_DME 8
|
1074 |
|
|
`define OR1200_DU_DRR_IME 9
|
1075 |
|
|
`define OR1200_DU_DRR_RE 10
|
1076 |
|
|
`define OR1200_DU_DRR_SCE 11
|
1077 |
|
|
`define OR1200_DU_DRR_BE 12
|
1078 |
|
|
`define OR1200_DU_DRR_TE 13
|
1079 |
|
|
|
1080 |
|
|
// Define if reading DU regs is allowed
|
1081 |
|
|
`define OR1200_DU_READREGS
|
1082 |
|
|
|
1083 |
|
|
// Define if unused DU registers bits should be zero
|
1084 |
|
|
`define OR1200_DU_UNUSED_ZERO
|
1085 |
|
|
|
1086 |
737 |
lampret |
// Define if IF/LSU status is not needed by devel i/f
|
1087 |
|
|
`define OR1200_DU_STATUS_UNIMPLEMENTED
|
1088 |
504 |
lampret |
|
1089 |
|
|
/////////////////////////////////////////////////////
|
1090 |
|
|
//
|
1091 |
|
|
// Programmable Interrupt Controller (PIC)
|
1092 |
|
|
//
|
1093 |
|
|
|
1094 |
|
|
// Define it if you want PIC implemented
|
1095 |
|
|
`define OR1200_PIC_IMPLEMENTED
|
1096 |
|
|
|
1097 |
|
|
// Define number of interrupt inputs (2-31)
|
1098 |
|
|
`define OR1200_PIC_INTS 20
|
1099 |
|
|
|
1100 |
|
|
// Address offsets of PIC registers inside PIC group
|
1101 |
|
|
`define OR1200_PIC_OFS_PICMR 2'd0
|
1102 |
|
|
`define OR1200_PIC_OFS_PICSR 2'd2
|
1103 |
|
|
|
1104 |
|
|
// Position of offset bits inside SPR address
|
1105 |
|
|
`define OR1200_PICOFS_BITS 1:0
|
1106 |
|
|
|
1107 |
|
|
// Define if you want these PIC registers to be implemented
|
1108 |
|
|
`define OR1200_PIC_PICMR
|
1109 |
|
|
`define OR1200_PIC_PICSR
|
1110 |
|
|
|
1111 |
|
|
// Define if reading PIC registers is allowed
|
1112 |
|
|
`define OR1200_PIC_READREGS
|
1113 |
|
|
|
1114 |
|
|
// Define if unused PIC register bits should be zero
|
1115 |
|
|
`define OR1200_PIC_UNUSED_ZERO
|
1116 |
|
|
|
1117 |
|
|
|
1118 |
|
|
/////////////////////////////////////////////////////
|
1119 |
|
|
//
|
1120 |
|
|
// Tick Timer (TT)
|
1121 |
|
|
//
|
1122 |
|
|
|
1123 |
|
|
// Define it if you want TT implemented
|
1124 |
|
|
`define OR1200_TT_IMPLEMENTED
|
1125 |
|
|
|
1126 |
|
|
// Address offsets of TT registers inside TT group
|
1127 |
|
|
`define OR1200_TT_OFS_TTMR 1'd0
|
1128 |
|
|
`define OR1200_TT_OFS_TTCR 1'd1
|
1129 |
|
|
|
1130 |
|
|
// Position of offset bits inside SPR group
|
1131 |
|
|
`define OR1200_TTOFS_BITS 0
|
1132 |
|
|
|
1133 |
|
|
// Define if you want these TT registers to be implemented
|
1134 |
|
|
`define OR1200_TT_TTMR
|
1135 |
|
|
`define OR1200_TT_TTCR
|
1136 |
|
|
|
1137 |
|
|
// TTMR bits
|
1138 |
|
|
`define OR1200_TT_TTMR_TP 27:0
|
1139 |
|
|
`define OR1200_TT_TTMR_IP 28
|
1140 |
|
|
`define OR1200_TT_TTMR_IE 29
|
1141 |
|
|
`define OR1200_TT_TTMR_M 31:30
|
1142 |
|
|
|
1143 |
|
|
// Define if reading TT registers is allowed
|
1144 |
|
|
`define OR1200_TT_READREGS
|
1145 |
|
|
|
1146 |
|
|
|
1147 |
|
|
//////////////////////////////////////////////
|
1148 |
|
|
//
|
1149 |
|
|
// MAC
|
1150 |
|
|
//
|
1151 |
|
|
`define OR1200_MAC_ADDR 0 // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0
|
1152 |
|
|
`define OR1200_MAC_SPR_WE // Define if MACLO/MACHI are SPR writable
|
1153 |
|
|
|
1154 |
|
|
|
1155 |
|
|
//////////////////////////////////////////////
|
1156 |
|
|
//
|
1157 |
|
|
// Data MMU (DMMU)
|
1158 |
|
|
//
|
1159 |
|
|
|
1160 |
|
|
//
|
1161 |
|
|
// Address that selects between TLB TR and MR
|
1162 |
|
|
//
|
1163 |
660 |
lampret |
`define OR1200_DTLB_TM_ADDR 7
|
1164 |
504 |
lampret |
|
1165 |
|
|
//
|
1166 |
|
|
// DTLBMR fields
|
1167 |
|
|
//
|
1168 |
|
|
`define OR1200_DTLBMR_V_BITS 0
|
1169 |
|
|
`define OR1200_DTLBMR_CID_BITS 4:1
|
1170 |
|
|
`define OR1200_DTLBMR_RES_BITS 11:5
|
1171 |
|
|
`define OR1200_DTLBMR_VPN_BITS 31:13
|
1172 |
|
|
|
1173 |
|
|
//
|
1174 |
|
|
// DTLBTR fields
|
1175 |
|
|
//
|
1176 |
|
|
`define OR1200_DTLBTR_CC_BITS 0
|
1177 |
|
|
`define OR1200_DTLBTR_CI_BITS 1
|
1178 |
|
|
`define OR1200_DTLBTR_WBC_BITS 2
|
1179 |
|
|
`define OR1200_DTLBTR_WOM_BITS 3
|
1180 |
|
|
`define OR1200_DTLBTR_A_BITS 4
|
1181 |
|
|
`define OR1200_DTLBTR_D_BITS 5
|
1182 |
|
|
`define OR1200_DTLBTR_URE_BITS 6
|
1183 |
|
|
`define OR1200_DTLBTR_UWE_BITS 7
|
1184 |
|
|
`define OR1200_DTLBTR_SRE_BITS 8
|
1185 |
|
|
`define OR1200_DTLBTR_SWE_BITS 9
|
1186 |
|
|
`define OR1200_DTLBTR_RES_BITS 11:10
|
1187 |
|
|
`define OR1200_DTLBTR_PPN_BITS 31:13
|
1188 |
|
|
|
1189 |
|
|
//
|
1190 |
|
|
// DTLB configuration
|
1191 |
|
|
//
|
1192 |
|
|
`define OR1200_DMMU_PS 13 // 13 for 8KB page size
|
1193 |
|
|
`define OR1200_DTLB_INDXW 6 // 6 for 64 entry DTLB 7 for 128 entries
|
1194 |
|
|
`define OR1200_DTLB_INDXL `OR1200_DMMU_PS // 13 13
|
1195 |
|
|
`define OR1200_DTLB_INDXH `OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1 // 18 19
|
1196 |
|
|
`define OR1200_DTLB_INDX `OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL // 18:13 19:13
|
1197 |
|
|
`define OR1200_DTLB_TAGW 32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS // 13 12
|
1198 |
|
|
`define OR1200_DTLB_TAGL `OR1200_DTLB_INDXH+1 // 19 20
|
1199 |
|
|
`define OR1200_DTLB_TAG 31:`OR1200_DTLB_TAGL // 31:19 31:20
|
1200 |
|
|
`define OR1200_DTLBMRW `OR1200_DTLB_TAGW+1 // +1 because of V bit
|
1201 |
|
|
`define OR1200_DTLBTRW 32-`OR1200_DMMU_PS+5 // +5 because of protection bits and CI
|
1202 |
|
|
|
1203 |
660 |
lampret |
//
|
1204 |
|
|
// Cache inhibit while DMMU is not enabled/implemented
|
1205 |
|
|
//
|
1206 |
|
|
// cache inhibited 0GB-4GB 1'b1
|
1207 |
735 |
lampret |
// cache inhibited 0GB-2GB !dcpu_adr_i[31]
|
1208 |
|
|
// cache inhibited 0GB-1GB 2GB-3GB !dcpu_adr_i[30]
|
1209 |
|
|
// cache inhibited 1GB-2GB 3GB-4GB dcpu_adr_i[30]
|
1210 |
|
|
// cache inhibited 2GB-4GB (default) dcpu_adr_i[31]
|
1211 |
660 |
lampret |
// cached 0GB-4GB 1'b0
|
1212 |
|
|
//
|
1213 |
|
|
`define OR1200_DMMU_CI dcpu_adr_i[31]
|
1214 |
504 |
lampret |
|
1215 |
660 |
lampret |
|
1216 |
504 |
lampret |
//////////////////////////////////////////////
|
1217 |
|
|
//
|
1218 |
|
|
// Insn MMU (IMMU)
|
1219 |
|
|
//
|
1220 |
|
|
|
1221 |
|
|
//
|
1222 |
|
|
// Address that selects between TLB TR and MR
|
1223 |
|
|
//
|
1224 |
660 |
lampret |
`define OR1200_ITLB_TM_ADDR 7
|
1225 |
504 |
lampret |
|
1226 |
|
|
//
|
1227 |
|
|
// ITLBMR fields
|
1228 |
|
|
//
|
1229 |
|
|
`define OR1200_ITLBMR_V_BITS 0
|
1230 |
|
|
`define OR1200_ITLBMR_CID_BITS 4:1
|
1231 |
|
|
`define OR1200_ITLBMR_RES_BITS 11:5
|
1232 |
|
|
`define OR1200_ITLBMR_VPN_BITS 31:13
|
1233 |
|
|
|
1234 |
|
|
//
|
1235 |
|
|
// ITLBTR fields
|
1236 |
|
|
//
|
1237 |
|
|
`define OR1200_ITLBTR_CC_BITS 0
|
1238 |
|
|
`define OR1200_ITLBTR_CI_BITS 1
|
1239 |
|
|
`define OR1200_ITLBTR_WBC_BITS 2
|
1240 |
|
|
`define OR1200_ITLBTR_WOM_BITS 3
|
1241 |
|
|
`define OR1200_ITLBTR_A_BITS 4
|
1242 |
|
|
`define OR1200_ITLBTR_D_BITS 5
|
1243 |
|
|
`define OR1200_ITLBTR_SXE_BITS 6
|
1244 |
|
|
`define OR1200_ITLBTR_UXE_BITS 7
|
1245 |
|
|
`define OR1200_ITLBTR_RES_BITS 11:8
|
1246 |
|
|
`define OR1200_ITLBTR_PPN_BITS 31:13
|
1247 |
|
|
|
1248 |
|
|
//
|
1249 |
|
|
// ITLB configuration
|
1250 |
|
|
//
|
1251 |
|
|
`define OR1200_IMMU_PS 13 // 13 for 8KB page size
|
1252 |
|
|
`define OR1200_ITLB_INDXW 6 // 6 for 64 entry ITLB 7 for 128 entries
|
1253 |
|
|
`define OR1200_ITLB_INDXL `OR1200_IMMU_PS // 13 13
|
1254 |
|
|
`define OR1200_ITLB_INDXH `OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1 // 18 19
|
1255 |
|
|
`define OR1200_ITLB_INDX `OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL // 18:13 19:13
|
1256 |
|
|
`define OR1200_ITLB_TAGW 32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS // 13 12
|
1257 |
|
|
`define OR1200_ITLB_TAGL `OR1200_ITLB_INDXH+1 // 19 20
|
1258 |
|
|
`define OR1200_ITLB_TAG 31:`OR1200_ITLB_TAGL // 31:19 31:20
|
1259 |
|
|
`define OR1200_ITLBMRW `OR1200_ITLB_TAGW+1 // +1 because of V bit
|
1260 |
|
|
`define OR1200_ITLBTRW 32-`OR1200_IMMU_PS+3 // +3 because of protection bits and CI
|
1261 |
|
|
|
1262 |
660 |
lampret |
//
|
1263 |
|
|
// Cache inhibit while IMMU is not enabled/implemented
|
1264 |
735 |
lampret |
// Note: all combinations that use icpu_adr_i cause async loop
|
1265 |
660 |
lampret |
//
|
1266 |
|
|
// cache inhibited 0GB-4GB 1'b1
|
1267 |
735 |
lampret |
// cache inhibited 0GB-2GB !icpu_adr_i[31]
|
1268 |
|
|
// cache inhibited 0GB-1GB 2GB-3GB !icpu_adr_i[30]
|
1269 |
|
|
// cache inhibited 1GB-2GB 3GB-4GB icpu_adr_i[30]
|
1270 |
|
|
// cache inhibited 2GB-4GB (default) icpu_adr_i[31]
|
1271 |
660 |
lampret |
// cached 0GB-4GB 1'b0
|
1272 |
|
|
//
|
1273 |
735 |
lampret |
`define OR1200_IMMU_CI 1'b0
|
1274 |
504 |
lampret |
|
1275 |
660 |
lampret |
|
1276 |
504 |
lampret |
/////////////////////////////////////////////////
|
1277 |
|
|
//
|
1278 |
|
|
// Insn cache (IC)
|
1279 |
|
|
//
|
1280 |
|
|
|
1281 |
|
|
// 3 for 8 bytes, 4 for 16 bytes etc
|
1282 |
|
|
`define OR1200_ICLS 4
|
1283 |
|
|
|
1284 |
|
|
//
|
1285 |
|
|
// IC configurations
|
1286 |
|
|
//
|
1287 |
1273 |
simont |
`ifdef OR1200_IC_1W_512B
|
1288 |
|
|
`define OR1200_ICSIZE 9 // 512
|
1289 |
|
|
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 7
|
1290 |
|
|
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 8
|
1291 |
|
|
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 9
|
1292 |
|
|
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 5
|
1293 |
|
|
`define OR1200_ICTAG_W 24
|
1294 |
|
|
`endif
|
1295 |
504 |
lampret |
`ifdef OR1200_IC_1W_4KB
|
1296 |
|
|
`define OR1200_ICSIZE 12 // 4096
|
1297 |
|
|
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 10
|
1298 |
|
|
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 11
|
1299 |
|
|
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 12
|
1300 |
|
|
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 8
|
1301 |
|
|
`define OR1200_ICTAG_W 21
|
1302 |
|
|
`endif
|
1303 |
|
|
`ifdef OR1200_IC_1W_8KB
|
1304 |
|
|
`define OR1200_ICSIZE 13 // 8192
|
1305 |
|
|
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 11
|
1306 |
|
|
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 12
|
1307 |
|
|
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 13
|
1308 |
|
|
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 9
|
1309 |
|
|
`define OR1200_ICTAG_W 20
|
1310 |
|
|
`endif
|
1311 |
|
|
|
1312 |
|
|
|
1313 |
|
|
/////////////////////////////////////////////////
|
1314 |
|
|
//
|
1315 |
|
|
// Data cache (DC)
|
1316 |
|
|
//
|
1317 |
|
|
|
1318 |
|
|
// 3 for 8 bytes, 4 for 16 bytes etc
|
1319 |
|
|
`define OR1200_DCLS 4
|
1320 |
|
|
|
1321 |
636 |
lampret |
// Define to perform store refill (potential performance penalty)
|
1322 |
|
|
// `define OR1200_DC_STORE_REFILL
|
1323 |
|
|
|
1324 |
504 |
lampret |
//
|
1325 |
|
|
// DC configurations
|
1326 |
|
|
//
|
1327 |
|
|
`ifdef OR1200_DC_1W_4KB
|
1328 |
|
|
`define OR1200_DCSIZE 12 // 4096
|
1329 |
|
|
`define OR1200_DCINDX `OR1200_DCSIZE-2 // 10
|
1330 |
|
|
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 11
|
1331 |
|
|
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 12
|
1332 |
|
|
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 8
|
1333 |
|
|
`define OR1200_DCTAG_W 21
|
1334 |
|
|
`endif
|
1335 |
|
|
`ifdef OR1200_DC_1W_8KB
|
1336 |
|
|
`define OR1200_DCSIZE 13 // 8192
|
1337 |
|
|
`define OR1200_DCINDX `OR1200_DCSIZE-2 // 11
|
1338 |
|
|
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 12
|
1339 |
|
|
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 13
|
1340 |
|
|
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 9
|
1341 |
|
|
`define OR1200_DCTAG_W 20
|
1342 |
|
|
`endif
|
1343 |
994 |
lampret |
|
1344 |
|
|
/////////////////////////////////////////////////
|
1345 |
|
|
//
|
1346 |
|
|
// Store buffer (SB)
|
1347 |
|
|
//
|
1348 |
|
|
|
1349 |
|
|
//
|
1350 |
|
|
// Store buffer
|
1351 |
|
|
//
|
1352 |
|
|
// It will improve performance by "caching" CPU stores
|
1353 |
|
|
// using store buffer. This is most important for function
|
1354 |
|
|
// prologues because DC can only work in write though mode
|
1355 |
|
|
// and all stores would have to complete external WB writes
|
1356 |
|
|
// to memory.
|
1357 |
|
|
// Store buffer is between DC and data BIU.
|
1358 |
|
|
// All stores will be stored into store buffer and immediately
|
1359 |
|
|
// completed by the CPU, even though actual external writes
|
1360 |
|
|
// will be performed later. As a consequence store buffer masks
|
1361 |
|
|
// all data bus errors related to stores (data bus errors
|
1362 |
|
|
// related to loads are delivered normally).
|
1363 |
|
|
// All pending CPU loads will wait until store buffer is empty to
|
1364 |
|
|
// ensure strict memory model. Right now this is necessary because
|
1365 |
|
|
// we don't make destinction between cached and cache inhibited
|
1366 |
|
|
// address space, so we simply empty store buffer until loads
|
1367 |
|
|
// can begin.
|
1368 |
|
|
//
|
1369 |
|
|
// It makes design a bit bigger, depending what is the number of
|
1370 |
|
|
// entries in SB FIFO. Number of entries can be changed further
|
1371 |
|
|
// down.
|
1372 |
|
|
//
|
1373 |
|
|
//`define OR1200_SB_IMPLEMENTED
|
1374 |
|
|
|
1375 |
|
|
//
|
1376 |
|
|
// Number of store buffer entries
|
1377 |
|
|
//
|
1378 |
|
|
// Verified number of entries are 4 and 8 entries
|
1379 |
|
|
// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must
|
1380 |
|
|
// always match 2**OR1200_SB_LOG.
|
1381 |
|
|
// To disable store buffer, undefine
|
1382 |
|
|
// OR1200_SB_IMPLEMENTED.
|
1383 |
|
|
//
|
1384 |
|
|
`define OR1200_SB_LOG 2 // 2 or 3
|
1385 |
|
|
`define OR1200_SB_ENTRIES 4 // 4 or 8
|
1386 |
1023 |
lampret |
|
1387 |
|
|
|
1388 |
1267 |
lampret |
/////////////////////////////////////////////////
|
1389 |
|
|
//
|
1390 |
|
|
// Quick Embedded Memory (QMEM)
|
1391 |
|
|
//
|
1392 |
|
|
|
1393 |
|
|
//
|
1394 |
|
|
// Quick Embedded Memory
|
1395 |
|
|
//
|
1396 |
|
|
// Instantiation of dedicated insn/data memory (RAM or ROM).
|
1397 |
|
|
// Insn fetch has effective throughput 1insn / clock cycle.
|
1398 |
|
|
// Data load takes two clock cycles / access, data store
|
1399 |
|
|
// takes 1 clock cycle / access (if there is no insn fetch)).
|
1400 |
|
|
// Memory instantiation is shared between insn and data,
|
1401 |
|
|
// meaning if insn fetch are performed, data load/store
|
1402 |
|
|
// performance will be lower.
|
1403 |
|
|
//
|
1404 |
|
|
// Main reason for QMEM is to put some time critical functions
|
1405 |
|
|
// into this memory and to have predictable and fast access
|
1406 |
|
|
// to these functions. (soft fpu, context switch, exception
|
1407 |
|
|
// handlers, stack, etc)
|
1408 |
|
|
//
|
1409 |
|
|
// It makes design a bit bigger and slower. QMEM sits behind
|
1410 |
|
|
// IMMU/DMMU so all addresses are physical (so the MMUs can be
|
1411 |
|
|
// used with QMEM and QMEM is seen by the CPU just like any other
|
1412 |
|
|
// memory in the system). IC/DC are sitting behind QMEM so the
|
1413 |
|
|
// whole design timing might be worse with QMEM implemented.
|
1414 |
|
|
//
|
1415 |
|
|
`define OR1200_QMEM_IMPLEMENTED
|
1416 |
|
|
|
1417 |
|
|
//
|
1418 |
|
|
// Base address and mask of QMEM
|
1419 |
|
|
//
|
1420 |
|
|
// Base address defines first address of QMEM. Mask defines
|
1421 |
|
|
// QMEM range in address space. Actual size of QMEM is however
|
1422 |
|
|
// determined with instantiated RAM/ROM. However bigger
|
1423 |
|
|
// mask will reserve more address space for QMEM, but also
|
1424 |
|
|
// make design faster, while more tight mask will take
|
1425 |
|
|
// less address space but also make design slower. If
|
1426 |
|
|
// instantiated RAM/ROM is smaller than space reserved with
|
1427 |
|
|
// the mask, instatiated RAM/ROM will also be shadowed
|
1428 |
|
|
// at higher addresses in reserved space.
|
1429 |
|
|
//
|
1430 |
|
|
`define OR1200_QMEM_IADDR 32'h0080_0000
|
1431 |
|
|
`define OR1200_QMEM_IMASK 32'hfff0_0000 // Max QMEM size 1MB
|
1432 |
|
|
`define OR1200_QMEM_DADDR 32'h0080_0000
|
1433 |
|
|
`define OR1200_QMEM_DMASK 32'hfff0_0000 // Max QMEM size 1MB
|
1434 |
|
|
|
1435 |
|
|
//
|
1436 |
|
|
// QMEM interface byte-select capability
|
1437 |
|
|
//
|
1438 |
|
|
// To enable qmem_sel* ports, define this macro.
|
1439 |
|
|
//
|
1440 |
|
|
//`define OR1200_QMEM_BSEL
|
1441 |
|
|
|
1442 |
|
|
//
|
1443 |
|
|
// QMEM interface acknowledge
|
1444 |
|
|
//
|
1445 |
|
|
// To enable qmem_ack port, define this macro.
|
1446 |
|
|
//
|
1447 |
|
|
//`define OR1200_QMEM_ACK
|
1448 |
|
|
|
1449 |
1023 |
lampret |
/////////////////////////////////////////////////////
|
1450 |
|
|
//
|
1451 |
|
|
// VR, UPR and Configuration Registers
|
1452 |
|
|
//
|
1453 |
|
|
//
|
1454 |
|
|
// VR, UPR and configuration registers are optional. If
|
1455 |
|
|
// implemented, operating system can automatically figure
|
1456 |
|
|
// out how to use the processor because it knows
|
1457 |
|
|
// what units are available in the processor and how they
|
1458 |
|
|
// are configured.
|
1459 |
|
|
//
|
1460 |
|
|
// This section must be last in or1200_defines.v file so
|
1461 |
|
|
// that all units are already configured and thus
|
1462 |
|
|
// configuration registers are properly set.
|
1463 |
|
|
//
|
1464 |
|
|
|
1465 |
|
|
// Define if you want configuration registers implemented
|
1466 |
|
|
`define OR1200_CFGR_IMPLEMENTED
|
1467 |
|
|
|
1468 |
|
|
// Define if you want full address decode inside SYS group
|
1469 |
|
|
`define OR1200_SYS_FULL_DECODE
|
1470 |
|
|
|
1471 |
|
|
// Offsets of VR, UPR and CFGR registers
|
1472 |
|
|
`define OR1200_SPRGRP_SYS_VR 4'h0
|
1473 |
|
|
`define OR1200_SPRGRP_SYS_UPR 4'h1
|
1474 |
|
|
`define OR1200_SPRGRP_SYS_CPUCFGR 4'h2
|
1475 |
|
|
`define OR1200_SPRGRP_SYS_DMMUCFGR 4'h3
|
1476 |
|
|
`define OR1200_SPRGRP_SYS_IMMUCFGR 4'h4
|
1477 |
|
|
`define OR1200_SPRGRP_SYS_DCCFGR 4'h5
|
1478 |
|
|
`define OR1200_SPRGRP_SYS_ICCFGR 4'h6
|
1479 |
|
|
`define OR1200_SPRGRP_SYS_DCFGR 4'h7
|
1480 |
|
|
|
1481 |
|
|
// VR fields
|
1482 |
|
|
`define OR1200_VR_REV_BITS 5:0
|
1483 |
|
|
`define OR1200_VR_RES1_BITS 15:6
|
1484 |
|
|
`define OR1200_VR_CFG_BITS 23:16
|
1485 |
|
|
`define OR1200_VR_VER_BITS 31:24
|
1486 |
|
|
|
1487 |
|
|
// VR values
|
1488 |
1267 |
lampret |
`define OR1200_VR_REV 6'h01
|
1489 |
1023 |
lampret |
`define OR1200_VR_RES1 10'h000
|
1490 |
|
|
`define OR1200_VR_CFG 8'h00
|
1491 |
|
|
`define OR1200_VR_VER 8'h12
|
1492 |
|
|
|
1493 |
|
|
// UPR fields
|
1494 |
|
|
`define OR1200_UPR_UP_BITS 0
|
1495 |
|
|
`define OR1200_UPR_DCP_BITS 1
|
1496 |
|
|
`define OR1200_UPR_ICP_BITS 2
|
1497 |
|
|
`define OR1200_UPR_DMP_BITS 3
|
1498 |
|
|
`define OR1200_UPR_IMP_BITS 4
|
1499 |
|
|
`define OR1200_UPR_MP_BITS 5
|
1500 |
|
|
`define OR1200_UPR_DUP_BITS 6
|
1501 |
|
|
`define OR1200_UPR_PCUP_BITS 7
|
1502 |
|
|
`define OR1200_UPR_PMP_BITS 8
|
1503 |
|
|
`define OR1200_UPR_PICP_BITS 9
|
1504 |
|
|
`define OR1200_UPR_TTP_BITS 10
|
1505 |
|
|
`define OR1200_UPR_RES1_BITS 23:11
|
1506 |
|
|
`define OR1200_UPR_CUP_BITS 31:24
|
1507 |
|
|
|
1508 |
|
|
// UPR values
|
1509 |
|
|
`define OR1200_UPR_UP 1'b1
|
1510 |
|
|
`ifdef OR1200_NO_DC
|
1511 |
|
|
`define OR1200_UPR_DCP 1'b0
|
1512 |
|
|
`else
|
1513 |
|
|
`define OR1200_UPR_DCP 1'b1
|
1514 |
|
|
`endif
|
1515 |
|
|
`ifdef OR1200_NO_IC
|
1516 |
|
|
`define OR1200_UPR_ICP 1'b0
|
1517 |
|
|
`else
|
1518 |
|
|
`define OR1200_UPR_ICP 1'b1
|
1519 |
|
|
`endif
|
1520 |
|
|
`ifdef OR1200_NO_DMMU
|
1521 |
|
|
`define OR1200_UPR_DMP 1'b0
|
1522 |
|
|
`else
|
1523 |
|
|
`define OR1200_UPR_DMP 1'b1
|
1524 |
|
|
`endif
|
1525 |
|
|
`ifdef OR1200_NO_IMMU
|
1526 |
|
|
`define OR1200_UPR_IMP 1'b0
|
1527 |
|
|
`else
|
1528 |
|
|
`define OR1200_UPR_IMP 1'b1
|
1529 |
|
|
`endif
|
1530 |
|
|
`define OR1200_UPR_MP 1'b1 // MAC always present
|
1531 |
|
|
`ifdef OR1200_DU_IMPLEMENTED
|
1532 |
|
|
`define OR1200_UPR_DUP 1'b1
|
1533 |
|
|
`else
|
1534 |
|
|
`define OR1200_UPR_DUP 1'b0
|
1535 |
|
|
`endif
|
1536 |
|
|
`define OR1200_UPR_PCUP 1'b0 // Performance counters not present
|
1537 |
|
|
`ifdef OR1200_DU_IMPLEMENTED
|
1538 |
|
|
`define OR1200_UPR_PMP 1'b1
|
1539 |
|
|
`else
|
1540 |
|
|
`define OR1200_UPR_PMP 1'b0
|
1541 |
|
|
`endif
|
1542 |
|
|
`ifdef OR1200_DU_IMPLEMENTED
|
1543 |
|
|
`define OR1200_UPR_PICP 1'b1
|
1544 |
|
|
`else
|
1545 |
|
|
`define OR1200_UPR_PICP 1'b0
|
1546 |
|
|
`endif
|
1547 |
|
|
`ifdef OR1200_DU_IMPLEMENTED
|
1548 |
|
|
`define OR1200_UPR_TTP 1'b1
|
1549 |
|
|
`else
|
1550 |
|
|
`define OR1200_UPR_TTP 1'b0
|
1551 |
|
|
`endif
|
1552 |
|
|
`define OR1200_UPR_RES1 13'h0000
|
1553 |
|
|
`define OR1200_UPR_CUP 8'h00
|
1554 |
|
|
|
1555 |
|
|
// CPUCFGR fields
|
1556 |
|
|
`define OR1200_CPUCFGR_NSGF_BITS 3:0
|
1557 |
|
|
`define OR1200_CPUCFGR_HGF_BITS 4
|
1558 |
|
|
`define OR1200_CPUCFGR_OB32S_BITS 5
|
1559 |
|
|
`define OR1200_CPUCFGR_OB64S_BITS 6
|
1560 |
|
|
`define OR1200_CPUCFGR_OF32S_BITS 7
|
1561 |
|
|
`define OR1200_CPUCFGR_OF64S_BITS 8
|
1562 |
|
|
`define OR1200_CPUCFGR_OV64S_BITS 9
|
1563 |
|
|
`define OR1200_CPUCFGR_RES1_BITS 31:10
|
1564 |
|
|
|
1565 |
|
|
// CPUCFGR values
|
1566 |
|
|
`define OR1200_CPUCFGR_NSGF 4'h0
|
1567 |
|
|
`define OR1200_CPUCFGR_HGF 1'b0
|
1568 |
|
|
`define OR1200_CPUCFGR_OB32S 1'b1
|
1569 |
|
|
`define OR1200_CPUCFGR_OB64S 1'b0
|
1570 |
|
|
`define OR1200_CPUCFGR_OF32S 1'b0
|
1571 |
|
|
`define OR1200_CPUCFGR_OF64S 1'b0
|
1572 |
|
|
`define OR1200_CPUCFGR_OV64S 1'b0
|
1573 |
|
|
`define OR1200_CPUCFGR_RES1 22'h000000
|
1574 |
|
|
|
1575 |
|
|
// DMMUCFGR fields
|
1576 |
|
|
`define OR1200_DMMUCFGR_NTW_BITS 1:0
|
1577 |
|
|
`define OR1200_DMMUCFGR_NTS_BITS 4:2
|
1578 |
|
|
`define OR1200_DMMUCFGR_NAE_BITS 7:5
|
1579 |
|
|
`define OR1200_DMMUCFGR_CRI_BITS 8
|
1580 |
|
|
`define OR1200_DMMUCFGR_PRI_BITS 9
|
1581 |
|
|
`define OR1200_DMMUCFGR_TEIRI_BITS 10
|
1582 |
|
|
`define OR1200_DMMUCFGR_HTR_BITS 11
|
1583 |
|
|
`define OR1200_DMMUCFGR_RES1_BITS 31:12
|
1584 |
|
|
|
1585 |
|
|
// DMMUCFGR values
|
1586 |
|
|
`ifdef OR1200_NO_DMMU
|
1587 |
|
|
`define OR1200_DMMUCFGR_NTW 2'h0 // Irrelevant
|
1588 |
|
|
`define OR1200_DMMUCFGR_NTS 3'h0 // Irrelevant
|
1589 |
|
|
`define OR1200_DMMUCFGR_NAE 3'h0 // Irrelevant
|
1590 |
|
|
`define OR1200_DMMUCFGR_CRI 1'b0 // Irrelevant
|
1591 |
|
|
`define OR1200_DMMUCFGR_PRI 1'b0 // Irrelevant
|
1592 |
|
|
`define OR1200_DMMUCFGR_TEIRI 1'b0 // Irrelevant
|
1593 |
|
|
`define OR1200_DMMUCFGR_HTR 1'b0 // Irrelevant
|
1594 |
|
|
`define OR1200_DMMUCFGR_RES1 20'h00000
|
1595 |
|
|
`else
|
1596 |
|
|
`define OR1200_DMMUCFGR_NTW 2'h0 // 1 TLB way
|
1597 |
|
|
`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW // Num TLB sets
|
1598 |
|
|
`define OR1200_DMMUCFGR_NAE 3'h0 // No ATB entries
|
1599 |
|
|
`define OR1200_DMMUCFGR_CRI 1'b0 // No control register
|
1600 |
|
|
`define OR1200_DMMUCFGR_PRI 1'b0 // No protection reg
|
1601 |
|
|
`define OR1200_DMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl.
|
1602 |
|
|
`define OR1200_DMMUCFGR_HTR 1'b0 // No HW TLB reload
|
1603 |
|
|
`define OR1200_DMMUCFGR_RES1 20'h00000
|
1604 |
|
|
`endif
|
1605 |
|
|
|
1606 |
|
|
// IMMUCFGR fields
|
1607 |
|
|
`define OR1200_IMMUCFGR_NTW_BITS 1:0
|
1608 |
|
|
`define OR1200_IMMUCFGR_NTS_BITS 4:2
|
1609 |
|
|
`define OR1200_IMMUCFGR_NAE_BITS 7:5
|
1610 |
|
|
`define OR1200_IMMUCFGR_CRI_BITS 8
|
1611 |
|
|
`define OR1200_IMMUCFGR_PRI_BITS 9
|
1612 |
|
|
`define OR1200_IMMUCFGR_TEIRI_BITS 10
|
1613 |
|
|
`define OR1200_IMMUCFGR_HTR_BITS 11
|
1614 |
|
|
`define OR1200_IMMUCFGR_RES1_BITS 31:12
|
1615 |
|
|
|
1616 |
|
|
// IMMUCFGR values
|
1617 |
|
|
`ifdef OR1200_NO_IMMU
|
1618 |
|
|
`define OR1200_IMMUCFGR_NTW 2'h0 // Irrelevant
|
1619 |
|
|
`define OR1200_IMMUCFGR_NTS 3'h0 // Irrelevant
|
1620 |
|
|
`define OR1200_IMMUCFGR_NAE 3'h0 // Irrelevant
|
1621 |
|
|
`define OR1200_IMMUCFGR_CRI 1'b0 // Irrelevant
|
1622 |
|
|
`define OR1200_IMMUCFGR_PRI 1'b0 // Irrelevant
|
1623 |
|
|
`define OR1200_IMMUCFGR_TEIRI 1'b0 // Irrelevant
|
1624 |
|
|
`define OR1200_IMMUCFGR_HTR 1'b0 // Irrelevant
|
1625 |
|
|
`define OR1200_IMMUCFGR_RES1 20'h00000
|
1626 |
|
|
`else
|
1627 |
|
|
`define OR1200_IMMUCFGR_NTW 2'h0 // 1 TLB way
|
1628 |
|
|
`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW // Num TLB sets
|
1629 |
|
|
`define OR1200_IMMUCFGR_NAE 3'h0 // No ATB entry
|
1630 |
|
|
`define OR1200_IMMUCFGR_CRI 1'b0 // No control reg
|
1631 |
|
|
`define OR1200_IMMUCFGR_PRI 1'b0 // No protection reg
|
1632 |
|
|
`define OR1200_IMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl
|
1633 |
|
|
`define OR1200_IMMUCFGR_HTR 1'b0 // No HW TLB reload
|
1634 |
|
|
`define OR1200_IMMUCFGR_RES1 20'h00000
|
1635 |
|
|
`endif
|
1636 |
|
|
|
1637 |
|
|
// DCCFGR fields
|
1638 |
|
|
`define OR1200_DCCFGR_NCW_BITS 2:0
|
1639 |
|
|
`define OR1200_DCCFGR_NCS_BITS 6:3
|
1640 |
|
|
`define OR1200_DCCFGR_CBS_BITS 7
|
1641 |
|
|
`define OR1200_DCCFGR_CWS_BITS 8
|
1642 |
|
|
`define OR1200_DCCFGR_CCRI_BITS 9
|
1643 |
|
|
`define OR1200_DCCFGR_CBIRI_BITS 10
|
1644 |
|
|
`define OR1200_DCCFGR_CBPRI_BITS 11
|
1645 |
|
|
`define OR1200_DCCFGR_CBLRI_BITS 12
|
1646 |
|
|
`define OR1200_DCCFGR_CBFRI_BITS 13
|
1647 |
|
|
`define OR1200_DCCFGR_CBWBRI_BITS 14
|
1648 |
|
|
`define OR1200_DCCFGR_RES1_BITS 31:15
|
1649 |
|
|
|
1650 |
|
|
// DCCFGR values
|
1651 |
|
|
`ifdef OR1200_NO_DC
|
1652 |
|
|
`define OR1200_DCCFGR_NCW 3'h0 // Irrelevant
|
1653 |
|
|
`define OR1200_DCCFGR_NCS 4'h0 // Irrelevant
|
1654 |
|
|
`define OR1200_DCCFGR_CBS 1'b0 // Irrelevant
|
1655 |
|
|
`define OR1200_DCCFGR_CWS 1'b0 // Irrelevant
|
1656 |
|
|
`define OR1200_DCCFGR_CCRI 1'b1 // Irrelevant
|
1657 |
|
|
`define OR1200_DCCFGR_CBIRI 1'b1 // Irrelevant
|
1658 |
|
|
`define OR1200_DCCFGR_CBPRI 1'b0 // Irrelevant
|
1659 |
|
|
`define OR1200_DCCFGR_CBLRI 1'b0 // Irrelevant
|
1660 |
|
|
`define OR1200_DCCFGR_CBFRI 1'b1 // Irrelevant
|
1661 |
|
|
`define OR1200_DCCFGR_CBWBRI 1'b0 // Irrelevant
|
1662 |
|
|
`define OR1200_DCCFGR_RES1 17'h00000
|
1663 |
|
|
`else
|
1664 |
|
|
`define OR1200_DCCFGR_NCW 3'h0 // 1 cache way
|
1665 |
|
|
`define OR1200_DCCFGR_NCS (`OR1200_DCTAG) // Num cache sets
|
1666 |
|
|
`define OR1200_DCCFGR_CBS (`OR1200_DCLS-4) // 16 byte cache block
|
1667 |
|
|
`define OR1200_DCCFGR_CWS 1'b0 // Write-through strategy
|
1668 |
|
|
`define OR1200_DCCFGR_CCRI 1'b1 // Cache control reg impl.
|
1669 |
|
|
`define OR1200_DCCFGR_CBIRI 1'b1 // Cache block inv reg impl.
|
1670 |
|
|
`define OR1200_DCCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl.
|
1671 |
|
|
`define OR1200_DCCFGR_CBLRI 1'b0 // Cache block lock reg not impl.
|
1672 |
|
|
`define OR1200_DCCFGR_CBFRI 1'b1 // Cache block flush reg impl.
|
1673 |
|
|
`define OR1200_DCCFGR_CBWBRI 1'b0 // Cache block WB reg not impl.
|
1674 |
|
|
`define OR1200_DCCFGR_RES1 17'h00000
|
1675 |
|
|
`endif
|
1676 |
|
|
|
1677 |
|
|
// ICCFGR fields
|
1678 |
|
|
`define OR1200_ICCFGR_NCW_BITS 2:0
|
1679 |
|
|
`define OR1200_ICCFGR_NCS_BITS 6:3
|
1680 |
|
|
`define OR1200_ICCFGR_CBS_BITS 7
|
1681 |
|
|
`define OR1200_ICCFGR_CWS_BITS 8
|
1682 |
|
|
`define OR1200_ICCFGR_CCRI_BITS 9
|
1683 |
|
|
`define OR1200_ICCFGR_CBIRI_BITS 10
|
1684 |
|
|
`define OR1200_ICCFGR_CBPRI_BITS 11
|
1685 |
|
|
`define OR1200_ICCFGR_CBLRI_BITS 12
|
1686 |
|
|
`define OR1200_ICCFGR_CBFRI_BITS 13
|
1687 |
|
|
`define OR1200_ICCFGR_CBWBRI_BITS 14
|
1688 |
|
|
`define OR1200_ICCFGR_RES1_BITS 31:15
|
1689 |
|
|
|
1690 |
|
|
// ICCFGR values
|
1691 |
|
|
`ifdef OR1200_NO_IC
|
1692 |
|
|
`define OR1200_ICCFGR_NCW 3'h0 // Irrelevant
|
1693 |
|
|
`define OR1200_ICCFGR_NCS 4'h0 // Irrelevant
|
1694 |
|
|
`define OR1200_ICCFGR_CBS 1'b0 // Irrelevant
|
1695 |
|
|
`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant
|
1696 |
|
|
`define OR1200_ICCFGR_CCRI 1'b0 // Irrelevant
|
1697 |
|
|
`define OR1200_ICCFGR_CBIRI 1'b0 // Irrelevant
|
1698 |
|
|
`define OR1200_ICCFGR_CBPRI 1'b0 // Irrelevant
|
1699 |
|
|
`define OR1200_ICCFGR_CBLRI 1'b0 // Irrelevant
|
1700 |
|
|
`define OR1200_ICCFGR_CBFRI 1'b0 // Irrelevant
|
1701 |
|
|
`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant
|
1702 |
|
|
`define OR1200_ICCFGR_RES1 17'h00000
|
1703 |
|
|
`else
|
1704 |
|
|
`define OR1200_ICCFGR_NCW 3'h0 // 1 cache way
|
1705 |
|
|
`define OR1200_ICCFGR_NCS (`OR1200_ICTAG) // Num cache sets
|
1706 |
|
|
`define OR1200_ICCFGR_CBS (`OR1200_ICLS-4) // 16 byte cache block
|
1707 |
|
|
`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant
|
1708 |
|
|
`define OR1200_ICCFGR_CCRI 1'b1 // Cache control reg impl.
|
1709 |
|
|
`define OR1200_ICCFGR_CBIRI 1'b1 // Cache block inv reg impl.
|
1710 |
|
|
`define OR1200_ICCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl.
|
1711 |
|
|
`define OR1200_ICCFGR_CBLRI 1'b0 // Cache block lock reg not impl.
|
1712 |
|
|
`define OR1200_ICCFGR_CBFRI 1'b1 // Cache block flush reg impl.
|
1713 |
|
|
`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant
|
1714 |
|
|
`define OR1200_ICCFGR_RES1 17'h00000
|
1715 |
|
|
`endif
|
1716 |
|
|
|
1717 |
|
|
// DCFGR fields
|
1718 |
|
|
`define OR1200_DCFGR_NDP_BITS 2:0
|
1719 |
|
|
`define OR1200_DCFGR_WPCI_BITS 3
|
1720 |
|
|
`define OR1200_DCFGR_RES1_BITS 31:4
|
1721 |
|
|
|
1722 |
|
|
// DCFGR values
|
1723 |
1267 |
lampret |
`ifdef OR1200_DU_HWBKPTS
|
1724 |
|
|
`define OR1200_DCFGR_NDP 3'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs
|
1725 |
|
|
`ifdef OR1200_DU_DWCR0
|
1726 |
|
|
`define OR1200_DCFGR_WPCI 1'b1
|
1727 |
|
|
`else
|
1728 |
|
|
`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl.
|
1729 |
|
|
`endif
|
1730 |
|
|
`else
|
1731 |
1023 |
lampret |
`define OR1200_DCFGR_NDP 3'h0 // Zero DVR/DCR pairs
|
1732 |
|
|
`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl.
|
1733 |
1267 |
lampret |
`endif
|
1734 |
1023 |
lampret |
`define OR1200_DCFGR_RES1 28'h0000000
|