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/* dmmu.c -- Data MMU simulation
 
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
   Copyright (C) 2008 Embecosm Limited
 
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
 
   This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by the Free
   Software Foundation; either version 3 of the License, or (at your option)
   any later version.
 
   This program is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   more details.
 
   You should have received a copy of the GNU General Public License along
   with this program.  If not, see <http://www.gnu.org/licenses/>.  */
 
/* This program is commented throughout in a fashion suitable for processing
   with Doxygen. */
 
/* DMMU model, perfectly functional. */
 
 
/* Autoconf and/or portability configuration */
#include "config.h"
#include "port.h"
 
/* System includes */
#include <stdlib.h>
 
/* Package includes */
#include "dmmu.h"
#include "sim-config.h"
#include "arch.h"
#include "execute.h"
#include "spr-defs.h"
#include "stats.h"
#include "except.h"
#include "sprs.h"
#include "misc.h"
#include "sim-cmd.h"
 
 
struct dmmu *dmmu_state;
 
/* Data MMU */
 
static uorreg_t *
dmmu_find_tlbmr (oraddr_t virtaddr, uorreg_t ** dtlbmr_lru, struct dmmu *dmmu)
{
  int set;
  int i;
  oraddr_t vpn;
  uorreg_t *dtlbmr;
 
  /* Which set to check out? */
  set = DADDR_PAGE (virtaddr) >> dmmu->pagesize_log2;
  set &= dmmu->set_mask;
  vpn = virtaddr & dmmu->vpn_mask;
 
  dtlbmr = &cpu_state.sprs[SPR_DTLBMR_BASE (0) + set];
  *dtlbmr_lru = dtlbmr;
 
  /* FIXME: Should this be reversed? */
  for (i = dmmu->nways; i; i--, dtlbmr += (128 * 2))
    {
      if (((*dtlbmr & dmmu->vpn_mask) == vpn) && (*dtlbmr & SPR_DTLBMR_V))
        return dtlbmr;
    }
 
  return NULL;
}
 
oraddr_t
dmmu_translate (oraddr_t virtaddr, int write_access)
{
  int i;
  uorreg_t *dtlbmr;
  uorreg_t *dtlbtr;
  uorreg_t *dtlbmr_lru;
  struct dmmu *dmmu = dmmu_state;
 
  if (!(cpu_state.sprs[SPR_SR] & SPR_SR_DME) ||
      !(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP))
    {
      data_ci = (virtaddr >= 0x80000000);
      return virtaddr;
    }
 
  dtlbmr = dmmu_find_tlbmr (virtaddr, &dtlbmr_lru, dmmu);
 
  /* Did we find our tlb entry? */
  if (dtlbmr)
    {                           /* Yes, we did. */
      dmmu_stats.loads_tlbhit++;
 
      dtlbtr = dtlbmr + 128;
 
      /* Set LRUs */
      for (i = 0; i < dmmu->nways; i++, dtlbmr_lru += (128 * 2))
        {
          if (*dtlbmr_lru & SPR_DTLBMR_LRU)
            *dtlbmr_lru = (*dtlbmr_lru & ~SPR_DTLBMR_LRU) |
              ((*dtlbmr_lru & SPR_DTLBMR_LRU) - 0x40);
        }
 
      /* This is not necessary `*dtlbmr &= ~SPR_DTLBMR_LRU;' since SPR_DTLBMR_LRU
       * is always decremented and the number of sets is always a power of two and
       * as such lru_reload has all bits set that get touched during decrementing
       * SPR_DTLBMR_LRU */
      *dtlbmr |= dmmu->lru_reload;
 
      /* Check if page is cache inhibited */
      data_ci = *dtlbtr & SPR_DTLBTR_CI;
 
      runtime.sim.mem_cycles += dmmu->hitdelay;
 
      /* Test for page fault */
      if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
        {
          if ((write_access && !(*dtlbtr & SPR_DTLBTR_SWE))
              || (!write_access && !(*dtlbtr & SPR_DTLBTR_SRE)))
            except_handle (EXCEPT_DPF, virtaddr);
        }
      else
        {
          if ((write_access && !(*dtlbtr & SPR_DTLBTR_UWE))
              || (!write_access && !(*dtlbtr & SPR_DTLBTR_URE)))
            except_handle (EXCEPT_DPF, virtaddr);
        }
 
      return (*dtlbtr & SPR_DTLBTR_PPN) | (virtaddr &
                                           (dmmu->page_offset_mask));
    }
 
  /* No, we didn't. */
  dmmu_stats.loads_tlbmiss++;
#if 0
  for (i = 0; i < dmmu->nways; i++)
    if (((cpu_state.sprs[SPR_DTLBMR_BASE (i) + set] & SPR_DTLBMR_LRU) >> 6) <
        minlru)
      minway = i;
 
  cpu_state.sprs[SPR_DTLBMR_BASE (minway) + set] &= ~SPR_DTLBMR_VPN;
  cpu_state.sprs[SPR_DTLBMR_BASE (minway) + set] |= vpn << 12;
  for (i = 0; i < dmmu->nways; i++)
    {
      uorreg_t lru = cpu_state.sprs[SPR_DTLBMR_BASE (i) + set];
      if (lru & SPR_DTLBMR_LRU)
        {
          lru = (lru & ~SPR_DTLBMR_LRU) | ((lru & SPR_DTLBMR_LRU) - 0x40);
          cpu_state.sprs[SPR_DTLBMR_BASE (i) + set] = lru;
        }
    }
  cpu_state.sprs[SPR_DTLBMR_BASE (way) + set] &= ~SPR_DTLBMR_LRU;
  cpu_state.sprs[SPR_DTLBMR_BASE (way) + set] |= (dmmu->nsets - 1) << 6;
 
  /* 1 to 1 mapping */
  cpu_state.sprs[SPR_DTLBTR_BASE (minway) + set] &= ~SPR_DTLBTR_PPN;
  cpu_state.sprs[SPR_DTLBTR_BASE (minway) + set] |= vpn << 12;
 
  cpu_state.sprs[SPR_DTLBMR_BASE (minway) + set] |= SPR_DTLBMR_V;
#endif
  runtime.sim.mem_cycles += dmmu->missdelay;
  /* if tlb refill implemented in HW */
  /* return ((cpu_state.sprs[SPR_DTLBTR_BASE(minway) + set] & SPR_DTLBTR_PPN) >> 12) * dmmu->pagesize + (virtaddr % dmmu->pagesize); */
 
  except_handle (EXCEPT_DTLBMISS, virtaddr);
  return 0;
}
 
/* DESC: try to find EA -> PA transaltion without changing
 *       any of precessor states. if this is not passible gives up
 *       (without triggering exceptions)
 *
 * PRMS: virtaddr     - EA for which to find translation
 *
 *       write_access - 0 ignore testing for write access
 *                      1 test for write access, if fails
 *                        do not return translation
 *
 *       through_dc   - 1 go through data cache
 *                      0 ignore data cache
 *
 * RTRN: 0            - no DMMU, DMMU disabled or ITLB miss
 *       else         - appropriate PA (note it DMMU is not present
 *                      PA === EA)
 */
oraddr_t
peek_into_dtlb (oraddr_t virtaddr, int write_access, int through_dc)
{
  uorreg_t *dtlbmr;
  uorreg_t *dtlbtr;
  uorreg_t *dtlbmr_lru;
  struct dmmu *dmmu = dmmu_state;
 
  if (!(cpu_state.sprs[SPR_SR] & SPR_SR_DME) ||
      !(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP))
    {
      if (through_dc)
        data_ci = (virtaddr >= 0x80000000);
      return virtaddr;
    }
 
  dtlbmr = dmmu_find_tlbmr (virtaddr, &dtlbmr_lru, dmmu);
 
  /* Did we find our tlb entry? */
  if (dtlbmr)
    {                           /* Yes, we did. */
      dmmu_stats.loads_tlbhit++;
 
      dtlbtr = dtlbmr + 128;
 
      /* Test for page fault */
      if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
        {
          if ((write_access && !(*dtlbtr & SPR_DTLBTR_SWE)) ||
              (!write_access && !(*dtlbtr & SPR_DTLBTR_SRE)))
 
            /* otherwise exception DPF would be raised */
            return (0);
        }
      else
        {
          if ((write_access && !(*dtlbtr & SPR_DTLBTR_UWE)) ||
              (!write_access && !(*dtlbtr & SPR_DTLBTR_URE)))
 
            /* otherwise exception DPF would be raised */
            return (0);
        }
 
      if (through_dc)
        {
          /* Check if page is cache inhibited */
          data_ci = *dtlbtr & SPR_DTLBTR_CI;
        }
 
      return (*dtlbtr & SPR_DTLBTR_PPN) | (virtaddr &
                                           (dmmu->page_offset_mask));
    }
 
  return (0);
}
 
/* FIXME: Is this comment valid? */
/* First check if virtual address is covered by DTLB and if it is:
    - increment DTLB read hit stats,
    - set 'lru' at this way to dmmu->ustates - 1 and
      decrement 'lru' of other ways unless they have reached 0,
    - check page access attributes and invoke DMMU page fault exception
      handler if necessary
   and if not:
    - increment DTLB read miss stats
    - find lru way and entry and invoke DTLB miss exception handler
    - set 'lru' with dmmu->ustates - 1 and decrement 'lru' of other
      ways unless they have reached 0
*/
 
static void
dtlb_status (void *dat)
{
  struct dmmu *dmmu = dat;
  int set;
  int way;
  int end_set = dmmu->nsets;
 
  if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP))
    {
      PRINTF ("DMMU not implemented. Set UPR[DMP].\n");
      return;
    }
 
  if (0 < end_set)
    PRINTF ("\nDMMU: ");
  /* Scan set(s) and way(s). */
  for (set = 0; set < end_set; set++)
    {
      for (way = 0; way < dmmu->nways; way++)
        {
          PRINTF ("%s\n", dump_spr (SPR_DTLBMR_BASE (way) + set,
                                    cpu_state.sprs[SPR_DTLBMR_BASE (way) +
                                                   set]));
          PRINTF ("%s\n",
                  dump_spr (SPR_DTLBTR_BASE (way) + set,
                            cpu_state.sprs[SPR_DTLBTR_BASE (way) + set]));
        }
    }
  if (0 < end_set)
    PRINTF ("\n");
}
 
/*---------------------------------------------------[ DMMU configuration ]---*/
 
/*---------------------------------------------------------------------------*/
/*!Enable or disable the DMMU
 
   Set the corresponding field in the UPR
 
   @param[in] val  The value to use
   @param[in] dat  The config data structure                                 */
/*---------------------------------------------------------------------------*/
static void
dmmu_enabled (union param_val val, void *dat)
{
  struct dmmu *dmmu = dat;
 
  if (val.int_val)
    {
      cpu_state.sprs[SPR_UPR] |= SPR_UPR_DMP;
    }
  else
    {
      cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_DMP;
    }
 
  dmmu->enabled = val.int_val;
 
}       /* dmmu_enabled() */
 
 
/*---------------------------------------------------------------------------*/
/*!Set the number of DMMU sets
 
   Value must be a power of 2 <= 256. Ignore any other values with a
   warning. Set the corresponding DMMU configuration flags.
 
   @param[in] val  The value to use
   @param[in] dat  The config data structure                                 */
/*---------------------------------------------------------------------------*/
static void
dmmu_nsets (union param_val  val,
            void            *dat)
{
  struct dmmu *dmmu = dat;
 
  if (is_power2 (val.int_val) && val.int_val <= 128)
    {
      int  set_bits = log2_int (val.int_val);
 
      dmmu->nsets = val.int_val;
 
      cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTS;
      cpu_state.sprs[SPR_DMMUCFGR] |= set_bits << SPR_DMMUCFGR_NTS_OFF;
    }
  else
    {
      fprintf (stderr, "Warning DMMU nsets not a power of 2 <= 128: ignored\n");
    }
}       /* dmmu_nsets() */
 
 
/*---------------------------------------------------------------------------*/
/*!Set the number of DMMU ways
 
   Value must be in the range 1-4. Ignore other values with a warning. Set the
   corresponding DMMU configuration flags.
 
   @param[in] val  The value to use
   @param[in] dat  The config data structure                                 */
/*---------------------------------------------------------------------------*/
static void
dmmu_nways (union param_val  val,
            void            *dat)
{
  struct dmmu *dmmu = dat;
 
  if (val.int_val >= 1 && val.int_val <= 4)
    {
      int  way_bits = val.int_val - 1;
 
      dmmu->nways = val.int_val;
 
      cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTW;
      cpu_state.sprs[SPR_DMMUCFGR] |= way_bits << SPR_DMMUCFGR_NTW_OFF;
    }
  else
    {
      fprintf (stderr, "Warning DMMU nways not in range 1-4: ignored\n");
    }
}       /* dmmu_nways() */
 
 
/*---------------------------------------------------------------------------*/
/*!Set the DMMU page size
 
   Value must be a power of 2. Ignore other values with a warning
 
   @param[in] val  The value to use
   @param[in] dat  The config data structure                                 */
/*---------------------------------------------------------------------------*/
static void
dmmu_pagesize (union param_val  val,
               void            *dat)
{
  struct dmmu *dmmu = dat;
 
  if (is_power2 (val.int_val))
    {
      dmmu->pagesize = val.int_val;
    }
  else
    {
      fprintf (stderr, "Warning DMMU page size must be power of 2: ignored\n");
    }
}       /* dmmu_pagesize() */
 
 
/*---------------------------------------------------------------------------*/
/*!Set the DMMU entry size
 
   Value must be a power of 2. Ignore other values with a warning
 
   @param[in] val  The value to use
   @param[in] dat  The config data structure                                 */
/*---------------------------------------------------------------------------*/
static void
dmmu_entrysize (union param_val  val,
                void            *dat)
{
  struct dmmu *dmmu = dat;
 
  if (is_power2 (val.int_val))
    {
      dmmu->entrysize = val.int_val;
    }
  else
    {
      fprintf (stderr, "Warning DMMU entry size must be power of 2: ignored\n");
    }
}       /* dmmu_entrysize() */
 
 
/*---------------------------------------------------------------------------*/
/*!Set the number of DMMU usage states
 
   Value must be 2, 3 or 4. Ignore other values with a warning
 
   @param[in] val  The value to use
   @param[in] dat  The config data structure                                 */
/*---------------------------------------------------------------------------*/
static void
dmmu_ustates (union param_val  val,
              void            *dat)
{
  struct dmmu *dmmu = dat;
 
  if ((val.int_val >= 2) && (val.int_val <= 4))
    {
      dmmu->ustates = val.int_val;
    }
  else
    {
      fprintf (stderr, "Warning number of DMMU usage states must be 2, 3 or 4:"
               "ignored\n");
    }
}       /* dmmu_ustates() */
 
 
static void
dmmu_missdelay (union param_val val, void *dat)
{
  struct dmmu *dmmu = dat;
 
  dmmu->missdelay = val.int_val;
}
 
static void
dmmu_hitdelay (union param_val val, void *dat)
{
  struct dmmu *dmmu = dat;
 
  dmmu->hitdelay = val.int_val;
}
 
/*---------------------------------------------------------------------------*/
/*!Initialize a new DMMU configuration
 
   ALL parameters are set explicitly to default values. Corresponding SPR
   flags are set as appropriate.
 
   @return  The new memory configuration data structure                      */
/*---------------------------------------------------------------------------*/
static void *
dmmu_start_sec ()
{
  struct dmmu *dmmu;
  int          set_bits;
  int          way_bits;
 
  if (NULL == (dmmu = malloc (sizeof (struct dmmu))))
    {
      fprintf (stderr, "OOM\n");
      exit (1);
    }
 
  dmmu->enabled   = 0;
  dmmu->nsets     = 1;
  dmmu->nways     = 1;
  dmmu->pagesize  = 8192;
  dmmu->entrysize = 1;          /* Not currently used */
  dmmu->ustates   = 2;
  dmmu->hitdelay  = 1;
  dmmu->missdelay = 1;
 
  if (dmmu->enabled)
    {
      cpu_state.sprs[SPR_UPR] |= SPR_UPR_DMP;
    }
  else
    {
      cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_DMP;
    }
 
  set_bits = log2_int (dmmu->nsets);
  cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTS;
  cpu_state.sprs[SPR_DMMUCFGR] |= set_bits << SPR_DMMUCFGR_NTS_OFF;
 
  way_bits = dmmu->nways - 1;
  cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTW;
  cpu_state.sprs[SPR_DMMUCFGR] |= way_bits << SPR_DMMUCFGR_NTW_OFF;
 
  dmmu_state = dmmu;
  return dmmu;
 
}       /* dmmu_start_sec() */
 
 
static void
dmmu_end_sec (void *dat)
{
  struct dmmu *dmmu = dat;
 
  /* Precalculate some values for use during address translation */
  dmmu->pagesize_log2 = log2_int (dmmu->pagesize);
  dmmu->page_offset_mask = dmmu->pagesize - 1;
  dmmu->page_mask = ~dmmu->page_offset_mask;
  dmmu->vpn_mask = ~((dmmu->pagesize * dmmu->nsets) - 1);
  dmmu->set_mask = dmmu->nsets - 1;
  dmmu->lru_reload = (dmmu->set_mask << 6) & SPR_DTLBMR_LRU;
 
  if (dmmu->enabled)
    {
      PRINTF ("Data MMU %dKB: %d ways, %d sets, entry size %d bytes\n",
              dmmu->nsets * dmmu->entrysize * dmmu->nways / 1024, dmmu->nways,
              dmmu->nsets, dmmu->entrysize);
      reg_sim_stat (dtlb_status, dmmu);
    }
}
 
void
reg_dmmu_sec (void)
{
  struct config_section *sec = reg_config_sec ("dmmu", dmmu_start_sec,
                                               dmmu_end_sec);
 
  reg_config_param (sec, "enabled", paramt_int, dmmu_enabled);
  reg_config_param (sec, "nsets", paramt_int, dmmu_nsets);
  reg_config_param (sec, "nways", paramt_int, dmmu_nways);
  reg_config_param (sec, "pagesize", paramt_int, dmmu_pagesize);
  reg_config_param (sec, "entrysize", paramt_int, dmmu_entrysize);
  reg_config_param (sec, "ustates", paramt_int, dmmu_ustates);
  reg_config_param (sec, "hitdelay", paramt_int, dmmu_hitdelay);
  reg_config_param (sec, "missdelay", paramt_int, dmmu_missdelay);
}

Line No.	Rev	Author	Line
1	62	lampret	`/* dmmu.c -- Data MMU simulation`
2	1748	jeremybenn
3	6	lampret	`Copyright (C) 1999 Damjan Lampret, lampret@opencores.org`
4	1748	jeremybenn	`Copyright (C) 2008 Embecosm Limited`
5	6	lampret
6	1748	jeremybenn	`Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>`
7	6	lampret
8	1748	jeremybenn	`This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.`
9	6	lampret
10	1748	jeremybenn	`This program is free software; you can redistribute it and/or modify it`
11			`under the terms of the GNU General Public License as published by the Free`
12			`Software Foundation; either version 3 of the License, or (at your option)`
13			`any later version.`
14	6	lampret
15	1748	jeremybenn	`This program is distributed in the hope that it will be useful, but WITHOUT`
16			`ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
17			`FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for`
18			`more details.`
19
20			`You should have received a copy of the GNU General Public License along`
21			`with this program. If not, see <http://www.gnu.org/licenses/>. */`
22
23			`/* This program is commented throughout in a fashion suitable for processing`
24			`with Doxygen. */`
25
26	1539	nogj	`/* DMMU model, perfectly functional. */`
27	6	lampret
28	1748	jeremybenn
29			`/* Autoconf and/or portability configuration */`
30	1350	nogj	`#include "config.h"`
31	1748	jeremybenn	`#include "port.h"`
32	1350	nogj
33	1748	jeremybenn	`/* System includes */`
34			`#include <stdlib.h>`
35	1350	nogj
36	1748	jeremybenn	`/* Package includes */`
37			`#include "dmmu.h"`
38			`#include "sim-config.h"`
39	1350	nogj	`#include "arch.h"`
40	1432	nogj	`#include "execute.h"`
41	1748	jeremybenn	`#include "spr-defs.h"`
42	6	lampret	`#include "stats.h"`
43	1748	jeremybenn	`#include "except.h"`
44	62	lampret	`#include "sprs.h"`
45	1555	nogj	`#include "misc.h"`
46	1748	jeremybenn	`#include "sim-cmd.h"`
47	6	lampret
48	1412	nogj
49	1718	nogj	`struct dmmu *dmmu_state;`
50
51	6	lampret	`/* Data MMU */`
52
53	1748	jeremybenn	`static uorreg_t *`
54			`dmmu_find_tlbmr (oraddr_t virtaddr, uorreg_t ** dtlbmr_lru, struct dmmu *dmmu)`
55	1539	nogj	`{`
56			`int set;`
57	430	markom	`int i;`
58	1539	nogj	`oraddr_t vpn;`
59			`uorreg_t *dtlbmr;`
60	572	simons
61	1539	nogj	`/* Which set to check out? */`
62	1748	jeremybenn	`set = DADDR_PAGE (virtaddr) >> dmmu->pagesize_log2;`
63	1718	nogj	`set &= dmmu->set_mask;`
64			`vpn = virtaddr & dmmu->vpn_mask;`
65	1539	nogj
66	1748	jeremybenn	`dtlbmr = &cpu_state.sprs[SPR_DTLBMR_BASE (0) + set];`
67	1539	nogj	`*dtlbmr_lru = dtlbmr;`
68
69			`/* FIXME: Should this be reversed? */`
70	1748	jeremybenn	`for (i = dmmu->nways; i; i--, dtlbmr += (128 * 2))`
71			`{`
72			`if (((dtlbmr & dmmu->vpn_mask) == vpn) && (dtlbmr & SPR_DTLBMR_V))`
73			`return dtlbmr;`
74			`}`
75	1539	nogj
76			`return NULL;`
77			`}`
78
79	1748	jeremybenn	`oraddr_t`
80			`dmmu_translate (oraddr_t virtaddr, int write_access)`
81	1539	nogj	`{`
82			`int i;`
83			`uorreg_t *dtlbmr;`
84			`uorreg_t *dtlbtr;`
85			`uorreg_t *dtlbmr_lru;`
86	1718	nogj	`struct dmmu *dmmu = dmmu_state;`
87	1539	nogj
88	1506	nogj	`if (!(cpu_state.sprs[SPR_SR] & SPR_SR_DME) \|\|`
89	1748	jeremybenn	`!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP))`
90			`{`
91			`data_ci = (virtaddr >= 0x80000000);`
92			`return virtaddr;`
93			`}`
94	430	markom
95	1748	jeremybenn	`dtlbmr = dmmu_find_tlbmr (virtaddr, &dtlbmr_lru, dmmu);`
96	456	simons
97	1539	nogj	`/* Did we find our tlb entry? */`
98	1748	jeremybenn	`if (dtlbmr)`
99			`{ /* Yes, we did. */`
100			`dmmu_stats.loads_tlbhit++;`
101	1539	nogj
102	1748	jeremybenn	`dtlbtr = dtlbmr + 128;`
103	1414	nogj
104	1748	jeremybenn	`/* Set LRUs */`
105			`for (i = 0; i < dmmu->nways; i++, dtlbmr_lru += (128 * 2))`
106			`{`
107			`if (*dtlbmr_lru & SPR_DTLBMR_LRU)`
108			`dtlbmr_lru = (dtlbmr_lru & ~SPR_DTLBMR_LRU) \|`
109			`((*dtlbmr_lru & SPR_DTLBMR_LRU) - 0x40);`
110			`}`
111	1414	nogj
112	1748	jeremybenn	/* This is not necessary `*dtlbmr &= ~SPR_DTLBMR_LRU;' since SPR_DTLBMR_LRU
113			`* is always decremented and the number of sets is always a power of two and`
114			`* as such lru_reload has all bits set that get touched during decrementing`
115			`* SPR_DTLBMR_LRU */`
116			`*dtlbmr \|= dmmu->lru_reload;`
117	1414	nogj
118	1748	jeremybenn	`/* Check if page is cache inhibited */`
119			`data_ci = *dtlbtr & SPR_DTLBTR_CI;`
120
121			`runtime.sim.mem_cycles += dmmu->hitdelay;`
122
123			`/* Test for page fault */`
124			`if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)`
125			`{`
126			`if ((write_access && !(*dtlbtr & SPR_DTLBTR_SWE))`
127			`\|\| (!write_access && !(*dtlbtr & SPR_DTLBTR_SRE)))`
128			`except_handle (EXCEPT_DPF, virtaddr);`
129			`}`
130			`else`
131			`{`
132			`if ((write_access && !(*dtlbtr & SPR_DTLBTR_UWE))`
133			`\|\| (!write_access && !(*dtlbtr & SPR_DTLBTR_URE)))`
134			`except_handle (EXCEPT_DPF, virtaddr);`
135			`}`
136
137			`return (*dtlbtr & SPR_DTLBTR_PPN) \| (virtaddr &`
138			`(dmmu->page_offset_mask));`
139	430	markom	`}`
140
141	1539	nogj	`/* No, we didn't. */`
142			`dmmu_stats.loads_tlbmiss++;`
143	430	markom	`#if 0`
144	1718	nogj	`for (i = 0; i < dmmu->nways; i++)`
145	1748	jeremybenn	`if (((cpu_state.sprs[SPR_DTLBMR_BASE (i) + set] & SPR_DTLBMR_LRU) >> 6) <`
146			`minlru)`
147	1539	nogj	`minway = i;`
148	1748	jeremybenn
149			`cpu_state.sprs[SPR_DTLBMR_BASE (minway) + set] &= ~SPR_DTLBMR_VPN;`
150			`cpu_state.sprs[SPR_DTLBMR_BASE (minway) + set] \|= vpn << 12;`
151			`for (i = 0; i < dmmu->nways; i++)`
152			`{`
153			`uorreg_t lru = cpu_state.sprs[SPR_DTLBMR_BASE (i) + set];`
154			`if (lru & SPR_DTLBMR_LRU)`
155			`{`
156			`lru = (lru & ~SPR_DTLBMR_LRU) \| ((lru & SPR_DTLBMR_LRU) - 0x40);`
157			`cpu_state.sprs[SPR_DTLBMR_BASE (i) + set] = lru;`
158			`}`
159	1506	nogj	`}`
160	1748	jeremybenn	`cpu_state.sprs[SPR_DTLBMR_BASE (way) + set] &= ~SPR_DTLBMR_LRU;`
161			`cpu_state.sprs[SPR_DTLBMR_BASE (way) + set] \|= (dmmu->nsets - 1) << 6;`
162	1506	nogj
163	1539	nogj	`/* 1 to 1 mapping */`
164	1748	jeremybenn	`cpu_state.sprs[SPR_DTLBTR_BASE (minway) + set] &= ~SPR_DTLBTR_PPN;`
165			`cpu_state.sprs[SPR_DTLBTR_BASE (minway) + set] \|= vpn << 12;`
166	1506	nogj
167	1748	jeremybenn	`cpu_state.sprs[SPR_DTLBMR_BASE (minway) + set] \|= SPR_DTLBMR_V;`
168	430	markom	`#endif`
169	1718	nogj	`runtime.sim.mem_cycles += dmmu->missdelay;`
170	1539	nogj	`/* if tlb refill implemented in HW */`
171	1718	nogj	`/* return ((cpu_state.sprs[SPR_DTLBTR_BASE(minway) + set] & SPR_DTLBTR_PPN) >> 12) * dmmu->pagesize + (virtaddr % dmmu->pagesize); */`
172	1539	nogj
173	1748	jeremybenn	`except_handle (EXCEPT_DTLBMISS, virtaddr);`
174	1539	nogj	`return 0;`
175	430	markom	`}`
176
177	1240	phoenix	`/* DESC: try to find EA -> PA transaltion without changing`
178			`* any of precessor states. if this is not passible gives up`
179			`* (without triggering exceptions)`
180			`*`
181			`* PRMS: virtaddr - EA for which to find translation`
182			`*`
183			`* write_access - 0 ignore testing for write access`
184			`* 1 test for write access, if fails`
185			`* do not return translation`
186			`*`
187			`* through_dc - 1 go through data cache`
188			`* 0 ignore data cache`
189			`*`
190			`* RTRN: 0 - no DMMU, DMMU disabled or ITLB miss`
191			`* else - appropriate PA (note it DMMU is not present`
192			`* PA === EA)`
193			`*/`
194	1748	jeremybenn	`oraddr_t`
195			`peek_into_dtlb (oraddr_t virtaddr, int write_access, int through_dc)`
196	1240	phoenix	`{`
197	1539	nogj	`uorreg_t *dtlbmr;`
198			`uorreg_t *dtlbtr;`
199			`uorreg_t *dtlbmr_lru;`
200	1718	nogj	`struct dmmu *dmmu = dmmu_state;`
201	1240	phoenix
202	1506	nogj	`if (!(cpu_state.sprs[SPR_SR] & SPR_SR_DME) \|\|`
203	1748	jeremybenn	`!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP))`
204			`{`
205			`if (through_dc)`
206			`data_ci = (virtaddr >= 0x80000000);`
207			`return virtaddr;`
208			`}`
209	1240	phoenix
210	1748	jeremybenn	`dtlbmr = dmmu_find_tlbmr (virtaddr, &dtlbmr_lru, dmmu);`
211	1240	phoenix
212	1539	nogj	`/* Did we find our tlb entry? */`
213	1748	jeremybenn	`if (dtlbmr)`
214			`{ /* Yes, we did. */`
215			`dmmu_stats.loads_tlbhit++;`
216	1539	nogj
217	1748	jeremybenn	`dtlbtr = dtlbmr + 128;`
218	1240	phoenix
219	1748	jeremybenn	`/* Test for page fault */`
220			`if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)`
221			`{`
222			`if ((write_access && !(*dtlbtr & SPR_DTLBTR_SWE)) \|\|`
223			`(!write_access && !(*dtlbtr & SPR_DTLBTR_SRE)))`
224
225			`/* otherwise exception DPF would be raised */`
226			`return (0);`
227			`}`
228			`else`
229			`{`
230			`if ((write_access && !(*dtlbtr & SPR_DTLBTR_UWE)) \|\|`
231			`(!write_access && !(*dtlbtr & SPR_DTLBTR_URE)))`
232
233			`/* otherwise exception DPF would be raised */`
234			`return (0);`
235			`}`
236
237			`if (through_dc)`
238			`{`
239			`/* Check if page is cache inhibited */`
240			`data_ci = *dtlbtr & SPR_DTLBTR_CI;`
241			`}`
242
243			`return (*dtlbtr & SPR_DTLBTR_PPN) \| (virtaddr &`
244			`(dmmu->page_offset_mask));`
245	1240	phoenix	`}`
246
247	1748	jeremybenn	`return (0);`
248	1240	phoenix	`}`
249
250	1718	nogj	`/* FIXME: Is this comment valid? */`
251	62	lampret	`/* First check if virtual address is covered by DTLB and if it is:`
252			`- increment DTLB read hit stats,`
253	1718	nogj	`- set 'lru' at this way to dmmu->ustates - 1 and`
254	6	lampret	`decrement 'lru' of other ways unless they have reached 0,`
255	62	lampret	`- check page access attributes and invoke DMMU page fault exception`
256			`handler if necessary`
257	6	lampret	`and if not:`
258	62	lampret	`- increment DTLB read miss stats`
259			`- find lru way and entry and invoke DTLB miss exception handler`
260	1718	nogj	`- set 'lru' with dmmu->ustates - 1 and decrement 'lru' of other`
261	6	lampret	`ways unless they have reached 0`
262			`*/`
263
264	1748	jeremybenn	`static void`
265			`dtlb_status (void *dat)`
266	6	lampret	`{`
267	1718	nogj	`struct dmmu *dmmu = dat;`
268	429	markom	`int set;`
269			`int way;`
270	1718	nogj	`int end_set = dmmu->nsets;`
271	62	lampret
272	1748	jeremybenn	`if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP))`
273			`{`
274			`PRINTF ("DMMU not implemented. Set UPR[DMP].\n");`
275			`return;`
276			`}`
277	102	lampret
278	1748	jeremybenn	`if (0 < end_set)`
279			`PRINTF ("\nDMMU: ");`
280	429	markom	`/* Scan set(s) and way(s). */`
281	1748	jeremybenn	`for (set = 0; set < end_set; set++)`
282			`{`
283			`for (way = 0; way < dmmu->nways; way++)`
284			`{`
285			`PRINTF ("%s\n", dump_spr (SPR_DTLBMR_BASE (way) + set,`
286			`cpu_state.sprs[SPR_DTLBMR_BASE (way) +`
287			`set]));`
288			`PRINTF ("%s\n",`
289			`dump_spr (SPR_DTLBTR_BASE (way) + set,`
290			`cpu_state.sprs[SPR_DTLBTR_BASE (way) + set]));`
291			`}`
292	429	markom	`}`
293	1748	jeremybenn	`if (0 < end_set)`
294			`PRINTF ("\n");`
295	6	lampret	`}`
296	1358	nogj
297			`/---------------------------------------------------[ DMMU configuration ]---/`
298	1748	jeremybenn
299			`/---------------------------------------------------------------------------/`
300			`/*!Enable or disable the DMMU`
301
302			`Set the corresponding field in the UPR`
303
304			`@param[in] val The value to use`
305			`@param[in] dat The config data structure */`
306			`/---------------------------------------------------------------------------/`
307			`static void`
308			`dmmu_enabled (union param_val val, void *dat)`
309	1358	nogj	`{`
310	1718	nogj	`struct dmmu *dmmu = dat;`
311
312	1748	jeremybenn	`if (val.int_val)`
313			`{`
314			`cpu_state.sprs[SPR_UPR] \|= SPR_UPR_DMP;`
315			`}`
316	1506	nogj	`else`
317	1748	jeremybenn	`{`
318			`cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_DMP;`
319			`}`
320
321	1718	nogj	`dmmu->enabled = val.int_val;`
322	1358	nogj
323	1748	jeremybenn	`} /* dmmu_enabled() */`
324
325
326			`/---------------------------------------------------------------------------/`
327			`/*!Set the number of DMMU sets`
328
329			`Value must be a power of 2 <= 256. Ignore any other values with a`
330			`warning. Set the corresponding DMMU configuration flags.`
331
332			`@param[in] val The value to use`
333			`@param[in] dat The config data structure */`
334			`/---------------------------------------------------------------------------/`
335			`static void`
336			`dmmu_nsets (union param_val val,`
337			`void *dat)`
338	1358	nogj	`{`
339	1718	nogj	`struct dmmu *dmmu = dat;`
340
341	1748	jeremybenn	`if (is_power2 (val.int_val) && val.int_val <= 128)`
342			`{`
343			`int set_bits = log2_int (val.int_val);`
344	1358	nogj
345	1748	jeremybenn	`dmmu->nsets = val.int_val;`
346
347			`cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTS;`
348			`cpu_state.sprs[SPR_DMMUCFGR] \|= set_bits << SPR_DMMUCFGR_NTS_OFF;`
349			`}`
350			`else`
351			`{`
352			`fprintf (stderr, "Warning DMMU nsets not a power of 2 <= 128: ignored\n");`
353			`}`
354			`} /* dmmu_nsets() */`
355
356
357			`/---------------------------------------------------------------------------/`
358			`/*!Set the number of DMMU ways`
359
360			`Value must be in the range 1-4. Ignore other values with a warning. Set the`
361			`corresponding DMMU configuration flags.`
362
363			`@param[in] val The value to use`
364			`@param[in] dat The config data structure */`
365			`/---------------------------------------------------------------------------/`
366			`static void`
367			`dmmu_nways (union param_val val,`
368			`void *dat)`
369	1358	nogj	`{`
370	1718	nogj	`struct dmmu *dmmu = dat;`
371
372	1748	jeremybenn	`if (val.int_val >= 1 && val.int_val <= 4)`
373			`{`
374			`int way_bits = val.int_val - 1;`
375
376			`dmmu->nways = val.int_val;`
377
378			`cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTW;`
379			`cpu_state.sprs[SPR_DMMUCFGR] \|= way_bits << SPR_DMMUCFGR_NTW_OFF;`
380			`}`
381	1358	nogj	`else`
382	1748	jeremybenn	`{`
383			`fprintf (stderr, "Warning DMMU nways not in range 1-4: ignored\n");`
384			`}`
385			`} /* dmmu_nways() */`
386	1358	nogj
387	1748	jeremybenn
388			`/---------------------------------------------------------------------------/`
389			`/*!Set the DMMU page size`
390
391			`Value must be a power of 2. Ignore other values with a warning`
392
393			`@param[in] val The value to use`
394			`@param[in] dat The config data structure */`
395			`/---------------------------------------------------------------------------/`
396			`static void`
397			`dmmu_pagesize (union param_val val,`
398			`void *dat)`
399	1358	nogj	`{`
400	1718	nogj	`struct dmmu *dmmu = dat;`
401
402	1748	jeremybenn	`if (is_power2 (val.int_val))`
403			`{`
404			`dmmu->pagesize = val.int_val;`
405			`}`
406	1358	nogj	`else`
407	1748	jeremybenn	`{`
408			`fprintf (stderr, "Warning DMMU page size must be power of 2: ignored\n");`
409			`}`
410			`} /* dmmu_pagesize() */`
411	1358	nogj
412	1748	jeremybenn
413			`/---------------------------------------------------------------------------/`
414			`/*!Set the DMMU entry size`
415
416			`Value must be a power of 2. Ignore other values with a warning`
417
418			`@param[in] val The value to use`
419			`@param[in] dat The config data structure */`
420			`/---------------------------------------------------------------------------/`
421			`static void`
422			`dmmu_entrysize (union param_val val,`
423			`void *dat)`
424	1358	nogj	`{`
425	1718	nogj	`struct dmmu *dmmu = dat;`
426
427	1748	jeremybenn	`if (is_power2 (val.int_val))`
428			`{`
429			`dmmu->entrysize = val.int_val;`
430			`}`
431	1358	nogj	`else`
432	1748	jeremybenn	`{`
433			`fprintf (stderr, "Warning DMMU entry size must be power of 2: ignored\n");`
434			`}`
435			`} /* dmmu_entrysize() */`
436	1358	nogj
437	1748	jeremybenn
438			`/---------------------------------------------------------------------------/`
439			`/*!Set the number of DMMU usage states`
440
441			`Value must be 2, 3 or 4. Ignore other values with a warning`
442
443			`@param[in] val The value to use`
444			`@param[in] dat The config data structure */`
445			`/---------------------------------------------------------------------------/`
446			`static void`
447			`dmmu_ustates (union param_val val,`
448			`void *dat)`
449	1358	nogj	`{`
450	1718	nogj	`struct dmmu *dmmu = dat;`
451
452	1748	jeremybenn	`if ((val.int_val >= 2) && (val.int_val <= 4))`
453			`{`
454			`dmmu->ustates = val.int_val;`
455			`}`
456	1358	nogj	`else`
457	1748	jeremybenn	`{`
458			`fprintf (stderr, "Warning number of DMMU usage states must be 2, 3 or 4:"`
459			`"ignored\n");`
460			`}`
461			`} /* dmmu_ustates() */`
462	1358	nogj
463	1748	jeremybenn
464			`static void`
465			`dmmu_missdelay (union param_val val, void *dat)`
466	1358	nogj	`{`
467	1718	nogj	`struct dmmu *dmmu = dat;`
468
469			`dmmu->missdelay = val.int_val;`
470	1358	nogj	`}`
471
472	1748	jeremybenn	`static void`
473			`dmmu_hitdelay (union param_val val, void *dat)`
474	1358	nogj	`{`
475	1718	nogj	`struct dmmu *dmmu = dat;`
476
477			`dmmu->hitdelay = val.int_val;`
478	1358	nogj	`}`
479
480	1748	jeremybenn	`/---------------------------------------------------------------------------/`
481			`/*!Initialize a new DMMU configuration`
482
483			`ALL parameters are set explicitly to default values. Corresponding SPR`
484			`flags are set as appropriate.`
485
486			`@return The new memory configuration data structure */`
487			`/---------------------------------------------------------------------------/`
488			`static void *`
489			`dmmu_start_sec ()`
490	1655	nogj	`{`
491	1718	nogj	`struct dmmu *dmmu;`
492	1748	jeremybenn	`int set_bits;`
493			`int way_bits;`
494	1718	nogj
495	1748	jeremybenn	`if (NULL == (dmmu = malloc (sizeof (struct dmmu))))`
496			`{`
497			`fprintf (stderr, "OOM\n");`
498			`exit (1);`
499			`}`
500	1718	nogj

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