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[/] [or1k_old/] [trunk/] [or1ksim/] [sim.cfg] - Blame information for rev 1748

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1 264 markom
/* sim.cfg -- Simulator configuration script file
2 897 markom
   Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
3 428 markom
 
4 264 markom
This file is part of OpenRISC 1000 Architectural Simulator.
5 876 rherveille
It contains the default configuration and help about configuring
6
the simulator.
7 264 markom
 
8
This program is free software; you can redistribute it and/or modify
9
it under the terms of the GNU General Public License as published by
10
the Free Software Foundation; either version 2 of the License, or
11
(at your option) any later version.
12
 
13
This program is distributed in the hope that it will be useful,
14
but WITHOUT ANY WARRANTY; without even the implied warranty of
15
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
GNU General Public License for more details.
17
 
18
You should have received a copy of the GNU General Public License
19
along with this program; if not, write to the Free Software
20
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
21
 
22 312 markom
 
23
/* INTRODUCTION
24
 
25 876 rherveille
   The ork1sim has various parameters, that are set in configuration files
26
   like this one. The user can switch between configurations at startup by
27
   specifying the required configuration file with the -f  option.
28
   If no configuration file is specified or1ksim searches for the default
29
   configuration file sim.cfg. First it searches for './sim.cfg'. If this
30
   file is not found, it searches for '~/or1k/sim.cfg'. If this file is
31
   not found too, it reverts to the built-in default configuration.
32 1021 rherveille
 
33 876 rherveille
   NOTE: Users should not rely on the built-in configuration, since the
34
         default configuration may differ between version.
35
         Rather create a configuration file that sets all critical values.
36
 
37
   This file may contain (standard C) comments only - no // support.
38 1021 rherveille
 
39 876 rherveille
   Configure files may be be included, using:
40 568 markom
   include "file_name_to_include"
41 312 markom
 
42 876 rherveille
   Like normal configuration files, the included file is divided into
43
   sections. Each section is described in detail also.
44 428 markom
 
45 876 rherveille
   Some section have subsections. One example of such a subsection is:
46 428 markom
 
47 312 markom
   device 
48
     instance specific parameters...
49
   enddevice
50 428 markom
 
51 312 markom
   which creates a device instance.
52
*/
53
 
54 876 rherveille
 
55 312 markom
/* MEMORY SECTION
56
 
57 876 rherveille
   This section specifies how the memory is generated and the blocks
58
   it consists of.
59 428 markom
 
60 312 markom
   type = random/unknown/pattern
61 876 rherveille
      Specifies the initial memory values.
62
      'random' generates random memory using seed 'random_seed'.
63
      'pattern' fills memory with 'pattern'.
64
      'unknown' does not specify how memory should be generated,
65
      leaving the memory in a undefined state. This is the fastest
66
      option.
67 428 markom
 
68 312 markom
   random_seed = 
69 876 rherveille
      random seed for randomizer, used if type = 'random'.
70 428 markom
 
71 312 markom
   pattern = 
72 876 rherveille
      pattern to fill memory, used if type = 'pattern'.
73 428 markom
 
74 1486 nogj
   baseaddr = 
75
      memory start address
76 428 markom
 
77 1486 nogj
   size = 
78
      memory size
79 424 markom
 
80 1486 nogj
   name = ""
81
      memory block name
82 428 markom
 
83 1486 nogj
   ce = 
84
      chip enable index of the memory instance
85 424 markom
 
86 1486 nogj
   mc = 
87
      memory controller this memory is connected to
88 428 markom
 
89 1486 nogj
   delayr = 
90
      cycles, required for read access, -1 if instance does not support reading
91 428 markom
 
92 1486 nogj
   delayw = 
93 1748 jeremybenn
      cycles, required for write access, -1 if instance does not support
94
      writing
95 1486 nogj
 
96
   log = ""
97 1748 jeremybenn
      filename, where to log memory accesses to. If log command is not
98
      specified, accesses are not logged.
99 312 markom
*/
100
 
101 1021 rherveille
 
102 262 markom
section memory
103 1748 jeremybenn
  name        = "RAM"
104
  random_seed = 12345
105
  type        = random
106
  ce          = 0
107
  mc          = 0
108
  baseaddr    = 0x00000000
109
  size        = 0x00400000
110
  delayr      = 1
111
  delayw      = 2
112 1486 nogj
end
113 1021 rherveille
 
114 427 markom
/* IMMU SECTION
115 312 markom
 
116 876 rherveille
    This section configures the Instruction Memory Manangement Unit
117 428 markom
 
118 427 markom
    enabled = 0/1
119 876 rherveille
       '0': disabled
120
       '1': enabled
121 428 markom
       (NOTE: UPR bit is set)
122
 
123 427 markom
    nsets = 
124 428 markom
       number of ITLB sets; must be power of two
125
 
126 427 markom
    nways = 
127
       number of ITLB ways
128 428 markom
 
129 427 markom
    pagesize = 
130
       instruction page size; must be power of two
131 428 markom
 
132 427 markom
    entrysize = 
133
       instruction entry size in bytes
134 428 markom
 
135 427 markom
    ustates = 
136
       number of ITLB usage states (2, 3, 4 etc., max is 4)
137 1021 rherveille
 
138 541 markom
    hitdelay = 
139
       number of cycles immu hit costs
140 1021 rherveille
 
141 541 markom
    missdelay = 
142
       number of cycles immu miss costs
143 427 markom
*/
144
 
145
section immu
146 1021 rherveille
  enabled = 1
147
  nsets = 64
148 427 markom
  nways = 1
149 428 markom
  pagesize = 8192
150 541 markom
  hitdelay = 0
151
  missdelay = 0
152 427 markom
end
153 428 markom
 
154 434 markom
 
155 427 markom
/* DMMU SECTION
156
 
157 876 rherveille
    This section configures the Data Memory Manangement Unit
158 428 markom
 
159 427 markom
    enabled = 0/1
160 876 rherveille
       '0': disabled
161
       '1': enabled
162 428 markom
       (NOTE: UPR bit is set)
163
 
164 427 markom
    nsets = 
165
       number of DTLB sets; must be power of two
166 428 markom
 
167 427 markom
    nways = 
168
       number of DTLB ways
169 428 markom
 
170 427 markom
    pagesize = 
171
       data page size; must be power of two
172 428 markom
 
173 427 markom
    entrysize = 
174
       data entry size in bytes
175 428 markom
 
176 427 markom
    ustates = 
177
       number of DTLB usage states (2, 3, 4 etc., max is 4)
178 541 markom
 
179
    hitdelay = 
180 876 rherveille
       number of cycles dmmu hit costs
181
 
182 541 markom
    missdelay = 
183 876 rherveille
       number of cycles dmmu miss costs
184 427 markom
*/
185
 
186
section dmmu
187 1021 rherveille
  enabled = 1
188
  nsets = 64
189 427 markom
  nways = 1
190 428 markom
  pagesize = 8192
191 541 markom
  hitdelay = 0
192
  missdelay = 0
193 427 markom
end
194
 
195 428 markom
 
196
/* IC SECTION
197
 
198 876 rherveille
   This section configures the Instruction Cache
199 428 markom
 
200 541 markom
   enabled = 0/1
201 876 rherveille
       '0': disabled
202
       '1': enabled
203 541 markom
      (NOTE: UPR bit is set)
204 428 markom
 
205 541 markom
   nsets = 
206
      number of IC sets; must be power of two
207 428 markom
 
208 541 markom
   nways = 
209
      number of IC ways
210 428 markom
 
211 541 markom
   blocksize = 
212
      IC block size in bytes; must be power of two
213 428 markom
 
214 541 markom
   ustates = 
215
      number of IC usage states (2, 3, 4 etc., max is 4)
216
 
217
   hitdelay = 
218
      number of cycles ic hit costs
219 1021 rherveille
 
220 541 markom
    missdelay = 
221
      number of cycles ic miss costs
222 428 markom
*/
223
 
224
section ic
225 1021 rherveille
  enabled = 1
226
  nsets = 256
227 428 markom
  nways = 1
228
  blocksize = 16
229 541 markom
  hitdelay = 0
230
  missdelay = 0
231 428 markom
end
232
 
233 434 markom
 
234 428 markom
/* DC SECTION
235
 
236 876 rherveille
   This section configures the Data Cache
237 428 markom
 
238 541 markom
   enabled = 0/1
239 876 rherveille
       '0': disabled
240
       '1': enabled
241 541 markom
      (NOTE: UPR bit is set)
242 428 markom
 
243 541 markom
   nsets = 
244
      number of DC sets; must be power of two
245 428 markom
 
246 541 markom
   nways = 
247
      number of DC ways
248 428 markom
 
249 541 markom
   blocksize = 
250
      DC block size in bytes; must be power of two
251 428 markom
 
252 541 markom
   ustates = 
253
      number of DC usage states (2, 3, 4 etc., max is 4)
254
 
255
   load_hitdelay = 
256
      number of cycles dc load hit costs
257 1021 rherveille
 
258 541 markom
   load_missdelay = 
259
      number of cycles dc load miss costs
260 1021 rherveille
 
261 541 markom
   store_hitdelay = 
262 1748 jeremybenn
      number of cycles dc store hit costs
263 1021 rherveille
 
264 541 markom
   store_missdelay = 
265 1748 jeremybenn
      number of cycles dc store miss costs
266 428 markom
*/
267
 
268
section dc
269 1021 rherveille
  enabled = 1
270
  nsets = 256
271 428 markom
  nways = 1
272
  blocksize = 16
273 541 markom
  load_hitdelay = 0
274
  load_missdelay = 0
275
  store_hitdelay = 0
276
  store_missdelay = 0
277 428 markom
end
278
 
279 1021 rherveille
 
280 1715 nogj
/* PIC SECTION
281
 
282
  This section specifies how the pic should behave
283
 
284
  enabled = 0/1
285
      '0': PIC is disabled
286
      '1': PIC is enabled
287
 
288
  edge_trigger = 0/1
289
      '0': Level triggered PIC
290
      '1': Edge triggered PIC
291
*/
292
 
293
section pic
294
  enabled = 1
295
  edge_trigger = 1
296
end
297
 
298
 
299 312 markom
/* SIM SECTION
300
 
301 876 rherveille
  This section specifies how or1ksim should behave.
302 428 markom
 
303 312 markom
  verbose = 0/1
304 876 rherveille
       '0': don't print extra messages
305
       '1': print extra messages
306 428 markom
 
307 344 markom
  debug = 0-9
308 876 rherveille
 
309
      1-9: debug message level.
310
           higher numbers produce more messages
311 428 markom
 
312 312 markom
  profile = 0/1
313 876 rherveille
      '0': don't generate profiling file 'sim.profile'
314
      '1': don't generate profiling file 'sim.profile'
315 428 markom
 
316 1748 jeremybenn
  prof_file = ""
317 876 rherveille
      optional filename for the profiling file.
318
      valid only if 'profile' is set
319 1021 rherveille
 
320 547 markom
  mprofile = 0/1
321 876 rherveille
      '0': don't generate memory profiling file 'sim.mprofile'
322
      '1': generate memory profiling file 'sim.mprofile'
323 428 markom
 
324 1748 jeremybenn
  mprof_file = ""
325 876 rherveille
      optional filename for the memory profiling file.
326
      valid only if 'mprofile' is set
327 547 markom
 
328 394 markom
  history = 0/1
329 876 rherveille
      '0': don't track execution flow
330
      '1': track execution flow
331
      Execution flow can be tracked for the simulator's
332
      'hist' command. Useful for back-trace debugging.
333 428 markom
 
334 312 markom
  iprompt = 0/1
335 876 rherveille
     '0': start in  (so what do we start in ???)
336
     '1': start in interactive prompt.
337 312 markom
 
338
  exe_log = 0/1
339 876 rherveille
      '0': don't generate execution log.
340
      '1': generate execution log.
341 1021 rherveille
 
342 1748 jeremybenn
  exe_log_type = default/hardware/simple/software
343 876 rherveille
      type of execution log, default is used when not specified
344 1021 rherveille
 
345 672 markom
  exe_log_start = 
346 876 rherveille
      index of first instruction to start logging, default = 0
347 1021 rherveille
 
348 672 markom
  exe_log_end = 
349 876 rherveille
      index of last instruction to end logging; not limited, if omitted
350 1021 rherveille
 
351 672 markom
  exe_log_marker = 
352
       specifies number of instructions before horizontal marker is
353
      printed; if zero, markers are disabled (default)
354 428 markom
 
355 1748 jeremybenn
  exe_log_file = ""
356 876 rherveille
      filename for the exection log file.
357
      valid only if 'exe_log' is set
358 624 ivang
 
359 433 markom
  clkcycle = [ps|ns|us|ms]
360
      specifies time measurement for one cycle
361 335 markom
*/
362
 
363 312 markom
section sim
364 335 markom
  /* verbose = 1 */
365 879 markom
  debug = 0
366 689 markom
  profile = 0
367 1748 jeremybenn
  prof_file = "sim.profile"
368 428 markom
 
369 1748 jeremybenn
  history = 0
370 312 markom
  /* iprompt = 0 */
371
  exe_log = 0
372 1021 rherveille
  exe_log_type = software
373 672 markom
  exe_log_start = 0
374 1021 rherveille
/*  exe_log_end = 20000000*/
375
  exe_log_marker = 10000
376 1748 jeremybenn
  exe_log_file = "executed.log"
377 1021 rherveille
 
378 624 ivang
  clkcycle = 100ns
379 312 markom
end
380
 
381
 
382
/* SECTION VAPI
383
 
384 876 rherveille
    This section configures the Verification API, used for Advanced
385 312 markom
    Core Verification.
386 428 markom
 
387 312 markom
    enabled = 0/1
388 876 rherveille
        '0': disbable VAPI server
389
        '1': enable/start VAPI server
390 428 markom
 
391 312 markom
    server_port = 
392
        TCP/IP port to start VAPI server on
393 428 markom
 
394 355 markom
    log_enabled = 0/1
395 876 rherveille
       '0': disable VAPI requests logging
396
       '1': enable VAPI requests logging
397 428 markom
 
398 486 erez
    hide_device_id = 0/1
399 1748 jeremybenn
       '1': don't log device id (for compatability with old version)
400
       '0': log device id
401 1021 rherveille
 
402 486 erez
 
403 1748 jeremybenn
    vapi_log_file = 
404 876 rherveille
       filename for the log file.
405
       valid only if log_enabled is set
406 312 markom
*/
407
 
408
section VAPI
409
  enabled = 0
410 1748 jeremybenn
  server_port = 50000
411 355 markom
  log_enabled = 0
412 1748 jeremybenn
  vapi_log_file = "vapi.log"
413 312 markom
end
414
 
415
 
416
/* CPU SECTION
417
 
418
   This section specifies various CPU parameters.
419 428 markom
 
420 312 markom
   ver = 
421 1748 jeremybenn
   cfg = 
422 312 markom
   rev = 
423 1748 jeremybenn
      specifies version, configuration and revision fields of the CPU version
424
      register.
425 428 markom
 
426 312 markom
   upr = 
427
      changes the upr register
428 1021 rherveille
 
429 1748 jeremybenn
   cfgr = 
430
      changes the CPU configuration register
431
 
432 556 markom
   sr = 
433
      sets the initial Supervision Register value
434 428 markom
 
435 312 markom
   superscalar = 0/1
436 876 rherveille
      '0': CPU is scalar
437
      '1': CPU is superscalar
438 388 lampret
      (modify cpu/or32/execute.c to tune superscalar model)
439
 
440 312 markom
   hazards = 0/1
441 876 rherveille
      '0': don't track data hazards in superscalar CPU
442
      '1': track data hazards in superscalar CPU
443
      If tracked, data hazards can be displayed using the
444
      simulator's 'r' command.
445 388 lampret
 
446 312 markom
   dependstats = 0/1
447 876 rherveille
      '0': don't calculate inter-instruction dependencies.
448
      '1': calculate inter-instruction dependencies.
449
      If calculated, inter-instruction dependencies can be
450
      displayed using the simulator's 'stat' command.
451 388 lampret
 
452 626 markom
   sbuf_len = 
453
      length of store buffer (<= 256), 0 = disabled
454 312 markom
*/
455
 
456 263 markom
section cpu
457 1748 jeremybenn
  ver = 0x12
458
  cfg = 0x00
459 263 markom
  rev = 0x0001
460
  superscalar = 0
461
  hazards = 0
462
  dependstats = 0
463 626 markom
  sbuf_len = 0
464 263 markom
end
465
 
466 312 markom
 
467 557 markom
/* PM SECTION
468
 
469 876 rherveille
   This section specifies Power Management parameters
470
 
471 557 markom
   enabled = 0/1
472 876 rherveille
      '0': disable power management
473
      '1': enable power management
474 557 markom
*/
475
 
476
section pm
477 1748 jeremybenn
  enabled = 1
478 557 markom
end
479
 
480 1021 rherveille
 
481 541 markom
/* BPB SECTION
482
 
483
   This section specifies how branch prediction should behave.
484 1021 rherveille
 
485 541 markom
   enabled = 0/1
486 876 rherveille
     '0': disable branch prediction
487
     '1': enable branch prediction
488 1021 rherveille
 
489 541 markom
   btic = 0/1
490 876 rherveille
     '0': disable branch target instruction cache model
491
     '1': enable branch target instruction cache model
492 541 markom
 
493
   sbp_bf_fwd = 0/1
494 876 rherveille
     Static branch prediction for 'l.bf'
495
     '0': don't use forward prediction
496 1021 rherveille
     '1': use forward prediction
497
 
498 541 markom
   sbp_bnf_fwd = 0/1
499 876 rherveille
     Static branch prediction for 'l.bnf'
500
     '0': don't use forward prediction
501
     '1': use forward prediction
502 541 markom
 
503
   hitdelay = 
504
       number of cycles bpb hit costs
505 1021 rherveille
 
506 541 markom
   missdelay = 
507
       number of cycles bpb miss costs
508
*/
509
 
510
section bpb
511 1748 jeremybenn
  enabled = 1
512 541 markom
  btic = 0
513
  sbp_bf_fwd = 0
514
  sbp_bnf_fwd = 0
515
  hitdelay = 0
516
  missdelay = 0
517
end
518
 
519
 
520 312 markom
/* DEBUG SECTION
521
 
522 876 rherveille
   This sections specifies how the debug unit should behave.
523 428 markom
 
524 312 markom
   enabled = 0/1
525 876 rherveille
      '0': disable debug unit
526
      '1': enable debug unit
527 428 markom
 
528 312 markom
   gdb_enabled = 0/1
529 876 rherveille
      '0': don't start gdb server
530
      '1': start gdb server at port 'server_port'
531 428 markom
 
532 312 markom
   server_port = 
533 876 rherveille
      TCP/IP port to start gdb server on
534
      valid only if gdb_enabled is set
535 486 erez
 
536
   vapi_id = 
537
      Used to create "fake" vapi log file containing the JTAG proxy messages.
538 479 markom
*/
539 428 markom
 
540 269 markom
section debug
541 1021 rherveille
  enabled = 0
542 312 markom
  gdb_enabled = 0
543 1748 jeremybenn
  server_port = 51000
544 269 markom
end
545
 
546 264 markom
 
547 312 markom
/* MC SECTION
548
 
549
   This section configures the memory controller
550
 
551
   enabled = 0/1
552 876 rherveille
     '0': disable memory controller
553
     '1': enable memory controller
554 428 markom
 
555 312 markom
   baseaddr = 
556
      address of first MC register
557 428 markom
 
558 312 markom
   POC = 
559
      Power On Configuration register
560 1486 nogj
 
561
   index = 
562
      Index of this memory controller amongst all the memory controllers
563 312 markom
*/
564
 
565 243 markom
section mc
566 1021 rherveille
  enabled = 1
567
  baseaddr = 0x93000000
568 1748 jeremybenn
  POC = 0x0000000a                 /* 32 bit SSRAM */
569 1486 nogj
  index = 0
570 243 markom
end
571 261 markom
 
572 312 markom
 
573
/* UART SECTION
574
 
575 876 rherveille
   This section configures the UARTs
576 312 markom
 
577 1461 nogj
     enabled = <0|1>
578
        Enable/disable the peripheral.  By default if it is enabled.
579
 
580 312 markom
     baseaddr = 
581
        address of first UART register for this device
582 428 markom
 
583 1126 sfurman
 
584
     channel = :
585
 
586
        The channel parameter indicates the source of received UART characters
587
        and the sink for transmitted UART characters.
588 428 markom
 
589 1126 sfurman
        The  can be either "file", "xterm", "tcp", "fd", or "tty"
590
        (without quotes).
591 332 markom
 
592 1126 sfurman
          A) To send/receive characters from a pair of files, use a file
593
             channel:
594
 
595
               channel=file:,
596
 
597
          B) To create an interactive terminal window, use an xterm channel:
598
 
599
               channel=xterm:[]*
600
 
601
          C) To create a bidirectional tcp socket which one could, for example,
602
             access via telnet, use a tcp channel:
603
 
604
               channel=tcp:
605
 
606
          D) To cause the UART to read/write from existing numeric file
607
             descriptors, use an fd channel:
608
 
609
               channel=fd:,
610
 
611
          E) To connect the UART to a physical serial port, create a tty
612
             channel:
613
 
614
               channel=tty:device=/dev/ttyS0,baud=9600
615
 
616 332 markom
     irq = 
617
        irq number for this device
618 428 markom
 
619 341 markom
     16550 = 0/1
620 876 rherveille
        '0': this device is a UART16450
621
        '1': this device is a UART16550
622 428 markom
 
623 312 markom
     jitter = 
624
        in msecs... time to block, -1 to disable it
625 428 markom
 
626 313 markom
     vapi_id = 
627
        VAPI id of this instance
628 312 markom
*/
629
 
630 261 markom
section uart
631 1461 nogj
  enabled = 1
632 1367 nogj
  baseaddr = 0x90000000
633
  irq = 2
634
  channel = "file:uart0.rx,uart0.tx"
635
  jitter = -1                     /* async behaviour */
636
  16550 = 1
637 261 markom
end
638
 
639 312 markom
 
640
/* DMA SECTION
641
 
642 876 rherveille
   This section configures the DMAs
643 312 markom
 
644 1461 nogj
     enabled = <0|1>
645
        Enable/disable the peripheral.  By default if it is enabled.
646
 
647 312 markom
     baseaddr = 
648
        address of first DMA register for this device
649
 
650
     irq = 
651
        irq number for this device
652 428 markom
 
653 313 markom
     vapi_id = 
654
        VAPI id of this instance
655 312 markom
*/
656
 
657 261 markom
section dma
658 1461 nogj
  enabled = 1
659 1370 nogj
  baseaddr = 0x9a000000
660
  irq = 11
661 261 markom
end
662 293 markom
 
663 304 markom
 
664 312 markom
/* ETHERNET SECTION
665
 
666 876 rherveille
   This section configures the ETHERNETs
667 312 markom
 
668 1461 nogj
     enabled = <0|1>
669
        Enable/disable the peripheral.  By default if it is enabled.
670
 
671 312 markom
     baseaddr = 
672
        address of first ethernet register for this device
673
 
674
     dma = 
675
        which controller is this ethernet "connected" to
676 428 markom
 
677 724 ivang
     irq = 
678
        ethernet mac IRQ level
679
 
680 725 ivang
     rtx_type = 
681 1748 jeremybenn
        use 0 - file interface, 1 - socket interface. Note the socket
682
        interface must be configured at build time.
683 725 ivang
 
684 312 markom
     rx_channel = 
685
        DMA channel used for RX
686 428 markom
 
687 312 markom
     tx_channel = 
688
        DMA channel used for TX
689
 
690 664 markom
     rxfile = ""
691 312 markom
        filename, where to read data from
692 428 markom
 
693 664 markom
     txfile = ""
694 312 markom
        filename, where to write data to
695 428 markom
 
696 724 ivang
     sockif = ""
697
        interface name of ethernet socket
698
 
699 313 markom
     vapi_id = 
700
        VAPI id of this instance
701 312 markom
*/
702
 
703 304 markom
section ethernet
704 1461 nogj
  enabled = 1
705 1372 nogj
  baseaddr = 0x92000000
706
  irq = 4
707 1748 jeremybenn
  rtx_type = 0
708 1372 nogj
  rxfile = "eth0.rx"
709
  txfile = "eth0.tx"
710
  sockif = "eth0"
711 304 markom
end
712 332 markom
 
713 1021 rherveille
 
714 486 erez
/* GPIO SECTION
715
 
716 876 rherveille
   This section configures the GPIOs
717 486 erez
 
718 1461 nogj
     enabled = <0|1>
719
        Enable/disable the peripheral.  By default if it is enabled.
720
 
721 486 erez
     baseaddr = 
722
        address of first GPIO register for this device
723
 
724
     irq = 
725
        irq number for this device
726
 
727
     base_vapi_id = 
728
        first VAPI id of this instance
729
        GPIO uses 8 consecutive VAPI IDs
730
*/
731
 
732
section gpio
733 1461 nogj
  enabled = 1
734 1374 nogj
  baseaddr = 0x91000000
735
  irq = 3
736
  base_vapi_id = 0x0200
737 486 erez
end
738
 
739 645 markom
/* VGA SECTION
740 1021 rherveille
 
741 876 rherveille
    This section configures the VGA/LCD controller
742 1021 rherveille
 
743 1461 nogj
      enabled = <0|1>
744
        Enable/disable the peripheral.  By default if it is enabled.
745
 
746 645 markom
      baseaddr = 
747
        address of first VGA register
748 1021 rherveille
 
749 645 markom
      irq = 
750
        irq number for this device
751 1021 rherveille
 
752 645 markom
      refresh_rate = 
753
        number of cycles between screen dumps
754 1021 rherveille
 
755 645 markom
      filename = ""
756
        template name for generated names (e.g. "primary" produces "primary0023.bmp")
757
*/
758
 
759
section vga
760 1461 nogj
  enabled = 1
761 1368 nogj
  baseaddr = 0x97100000
762
  irq = 8
763
  refresh_rate = 100000
764
  filename = "primary"
765 645 markom
end
766
 
767 876 rherveille
 
768 1021 rherveille
/* FB SECTION
769
 
770
    This section configures the frame buffer
771
 
772 1461 nogj
    enabled = <0|1>
773
      Enable/disable the peripheral.  By default if it is enabled.
774
 
775 664 markom
    baseaddr = 
776 645 markom
      base address of frame buffer
777 1021 rherveille
 
778 645 markom
    refresh_rate = 
779
      number of cycles between screen dumps
780 1021 rherveille
 
781 645 markom
    filename = ""
782
      template name for generated names (e.g. "primary" produces "primary0023.bmp")
783
*/
784
 
785
section fb
786 1461 nogj
  enabled = 1
787 1021 rherveille
  baseaddr = 0x97000000
788
  refresh_rate = 1000000
789 645 markom
  filename = "primary"
790
end
791 664 markom
 
792 1021 rherveille
 
793 664 markom
/* KBD SECTION
794
 
795 876 rherveille
    This section configures the PS/2 compatible keyboard
796 1021 rherveille
 
797 1748 jeremybenn
    enabled = <0|1>
798
      Enable/disable the peripheral.  By default if it is enabled.
799
 
800 664 markom
    baseaddr = 
801
      base address of the keyboard device
802 1021 rherveille
 
803 1748 jeremybenn
    irq = 
804
      irq number for this device
805
 
806 664 markom
    rxfile = ""
807
      filename, where to read data from
808
*/
809
 
810
section kbd
811 1461 nogj
  enabled = 1
812 1748 jeremybenn
  baseaddr = 0x94000000
813 1021 rherveille
  irq = 5
814
  rxfile = "kbd.rx"
815 664 markom
end
816 876 rherveille
 
817
 
818
/* ATA SECTION
819 1021 rherveille
 
820 876 rherveille
    This section configures the ATA/ATAPI host controller
821 1021 rherveille
 
822 1748 jeremybenn
      enabled = <0|1>
823
        Enable/disable the peripheral.  By default it is enabled.
824
 
825 876 rherveille
      baseaddr = 
826
        address of first ATA register
827 1021 rherveille
 
828 876 rherveille
      irq = 
829
        irq number for this device
830
 
831 1701 nogj
      dev_id = 1/2/3
832
        Which OCIDEC version to imitate
833 876 rherveille
 
834 1701 nogj
      rev = 
835
        Revision of OCIDEC
836
 
837 1702 nogj
      pio_mode0_t1 = <0-255>
838
        PIO T1 reset value
839
 
840
      pio_mode0_t2 = <0-255>
841
        PIO T2 reset value
842
 
843
      pio_mode0_t4 = <0-255>
844
        PIO T4 reset value
845
 
846
      pio_mode0_teoc = <0-255>
847
        PIO Teoc reset value
848
 
849
      dma_mode0_tm = <0-255>
850
        DMA Tm reset value
851
 
852
      dma_mode0_td = <0-255>
853
        DMA Td reset value
854
 
855
      dma_mode0_teoc = <0-255>
856
        DMA Teoc reset value
857
 
858 1703 nogj
      Device specific
859 876 rherveille
 
860 1703 nogj
        type = 
861
          ata device 0 type
862
          0: NO_CONNECT: none (not connected)
863
          1: FILE      : simulated harddisk
864
          2: LOCAL     : local system harddisk
865 876 rherveille
 
866 1703 nogj
        file = ""
867
          filename for simulated ATA device
868
          valid only if dev_type0 == 1
869 876 rherveille
 
870 1703 nogj
        size = 
871
          size of simulated hard-disk (in MBytes)
872
          valid only if dev_type0 == 1
873 876 rherveille
 
874 1703 nogj
        packet = 
875
          0: simulated ATA device does NOT implement PACKET command feature set
876
          1: simulated ATA device does implement PACKET command feature set
877
 
878 1712 nogj
        firmware = 
879
          Firmware to report in `Identify device command'
880
 
881
        heads = 
882
          Number of default heads (-1)
883
 
884
        sectors = 
885
          Number of default sectors per track
886
 
887
        mwdma = 
888
          The highest multiword DMA mode; 2, 1, 0, -1 (No DMA)
889
 
890
        pio = 
891
          The highest supported pio mode; 4, 3, 2, 1, 0
892
 
893 876 rherveille
   FIXME: irq number
894
*/
895
 
896
section ata
897 1461 nogj
  enabled = 1
898 1364 nogj
  baseaddr = 0x9e000000
899
  irq = 15
900 1701 nogj
  dev_id = 1
901
  rev = 0
902 876 rherveille
 
903 1702 nogj
  pio_mode0_t1 = 6
904
  pio_mode0_t2 = 28
905
  pio_mode0_t4 = 2
906
  pio_mode0_teoc = 23
907
 
908
  dma_mode0_tm = 4
909
  dma_mode0_td = 21
910
  dma_mode0_teoc = 21
911
 
912 1703 nogj
  device 0
913
    type   = 1
914
    file   = "/tmp/sim_atadev0"
915
    size   = 1
916
    packet = 0
917 1712 nogj
 
918
    heads  = 7
919
    sectors = 32
920
 
921
    firmware = "02207031"
922
    mwdma = 2
923
    pio = 4
924 1703 nogj
  enddevice
925 876 rherveille
 
926 1703 nogj
  device 1
927
    type   = 0
928
    file   = ""
929
    size   = 0
930
    packet = 0
931
  enddevice
932 876 rherveille
end
933 897 markom
 
934
 
935
/* CUC SECTION
936
 
937
    This section configures the OpenRISC Custom Unit Compiler
938
 
939
    memory_order = none/weak/strong/exact
940
      none   different memory ordering, even if there are dependencies,
941
             burst can be made, width can change
942
      weak   different memory ordering, if there cannot be dependencies
943
             burst can be made, width can change
944
      strong same memory ordering, burst can be made, width can change
945
      exact  exacltly the same memory ordering and widths
946
 
947
    calling_convention = 0/1
948
      whether programs follow OpenRISC calling conventions
949
 
950
    enable_bursts = 0/1
951
      whether burst are detected
952
 
953
    no_multicycle = 0/1
954
      if selected no multicycle logic paths will be generated
955
 
956
    timings_fn = ""
957
*/
958
 
959
section cuc
960
  memory_order = weak
961
  calling_convention = 1
962
  enable_bursts = 1
963
  no_multicycle = 1
964
  timings_fn = "virtex.tim"
965
end
966
 

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