URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] [or1k_old/] [trunk/] [orp/] [orp_soc/] [bench/] [verilog/] [bench_defines.v] - Blame information for rev 1782

Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  XESS test bench definitions                                 ////
////                                                              ////
////  This file is part of the OR1K test application              ////
////  http://www.opencores.org/cores/or1k/xess/                   ////
////                                                              ////
////  Description                                                 ////
////  Definitions for the test bench.                             ////
////                                                              ////
////  To Do:                                                      ////
////   - nothing really                                           ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2002/03/28 19:59:54  lampret
// Added bench directory
//
// Revision 1.2  2002/01/03 08:40:14  lampret
// Added second clock as RISC main clock. Updated or120_monitor.
//
// Revision 1.1.1.1  2001/11/04 18:51:06  lampret
// First import.
//
//
 
//
// Reset active time for simulation
//
`define BENCH_RESET_TIME        10
 
//
// Clock half period for simulation
//
`define BENCH_CLK_HALFPERIOD    75
 
//
// OR1200 clock mode
//
`ifdef OR1200_CLMODE_1TO2
`define CLK2_HALFPERIOD         25
`else
`ifdef OR1200_CLMODE_1TO4
Unsuppported
`else
`define CLK2_HALFPERIOD         50
`endif
`endif
 
//`define FLASH_GENERIC

Line No.	Rev	Author	Line
1	779	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// XESS test bench definitions ////`
4			`//// ////`
5			`//// This file is part of the OR1K test application ////`
6			`//// http://www.opencores.org/cores/or1k/xess/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Definitions for the test bench. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - nothing really ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2001 Authors ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	1268	lampret	`// Revision 1.1 2002/03/28 19:59:54 lampret`
48			`// Added bench directory`
49			`//`
50	779	lampret	`// Revision 1.2 2002/01/03 08:40:14 lampret`
51			`// Added second clock as RISC main clock. Updated or120_monitor.`
52			`//`
53			`// Revision 1.1.1.1 2001/11/04 18:51:06 lampret`
54			`// First import.`
55			`//`
56			`//`
57
58			`//`
59			`// Reset active time for simulation`
60			`//`
61			`define BENCH_RESET_TIME 10
62
63			`//`
64			`// Clock half period for simulation`
65			`//`
66	1268	lampret	`define BENCH_CLK_HALFPERIOD 75
67	779	lampret
68			`//`
69			`// OR1200 clock mode`
70			`//`
71			`ifdef OR1200_CLMODE_1TO2
72			`define CLK2_HALFPERIOD 25
73			`else
74			`ifdef OR1200_CLMODE_1TO4
75			`Unsuppported`
76			`else
77			`define CLK2_HALFPERIOD 50
78			`endif
79			`endif
80
81			//`define FLASH_GENERIC

Browse

Tools

Subversion Repositories or1k_old

[/] [or1k_old/] [trunk/] [orp/] [orp_soc/] [bench/] [verilog/] [bench_defines.v] - Blame information for rev 1782