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[/] [or1k_old/] [trunk/] [orp/] [orp_soc/] [bench/] [verilog/] [dbg_comm.v] - Blame information for rev 1782

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1 779 lampret
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  File_communication.v                                        ////
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////                                                              ////
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////                                                              ////
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////  This file is part of the SoC/OpenRISC Development Interface ////
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////  http://www.opencores.org/cores/DebugInterface/              ////
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////                                                              ////
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////                                                              ////
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////  Author(s):                                                  ////
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////       Igor Mohor                                             ////
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////       igorm@opencores.org                                    ////
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////                                                              ////
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////                                                              ////
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////  All additional information is avaliable in the README.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000,2001 Authors                              ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1  2001/11/04 18:51:07  lampret
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// First import.
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//
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// Revision 1.3  2001/09/24 14:06:13  mohor
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// Changes connected to the OpenRISC access (SPR read, SPR write).
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//
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// Revision 1.2  2001/09/20 10:10:30  mohor
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// Working version. Few bugs fixed, comments added.
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//
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// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
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// Initial official release.
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//
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//
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//
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//
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//
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`ifdef DBG_IF_COMM
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`include "timescale.v"
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`include "dbg_defines.v"
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`include "dbg_tb_defines.v"
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`define GDB_IN  "/projects/xess-damjan/sim/run/gdb_in.dat"
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`define GDB_OUT "/projects/xess-damjan/sim/run/gdb_out.dat"
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//`define GDB_IN        "/tmp/gdb_in.dat"
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//`define GDB_OUT       "/tmp/gdb_out.dat"
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//`define GDB_IN        "../src/gdb_in.dat"
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//`define GDB_OUT       "../src/gdb_out.dat"
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module dbg_comm(P_TMS, P_TCK, P_TRST, P_TDI, P_TDO);
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parameter Tp = 1;
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output          P_TMS;
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output          P_TCK;
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output          P_TRST;
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output          P_TDI;
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input           P_TDO;
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integer handle1, handle2;
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reg [4:0] memory[0:0];
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reg Mclk;
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reg wb_rst_i;
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reg alternator;
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reg StartTesting;
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wire P_TCK;
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wire P_TRST;
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wire P_TDI;
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wire P_TMS;
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wire P_TDO;
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reg [3:0] in_word_r;
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wire [4:0] in_word;
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wire [3:0] Temp;
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initial
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begin
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  alternator = 0;
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  StartTesting = 0;
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  wb_rst_i = 0;
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  #500;
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  wb_rst_i = 1;
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  #500;
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  wb_rst_i = 0;
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  #2000;
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  StartTesting = 1;
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  $display("StartTesting = 1");
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end
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initial
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begin
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  wait(StartTesting);
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  while(1)
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  begin
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    #1;
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    $readmemh(`GDB_OUT, memory);
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    //#1000;
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    if(!(memory[0] & 5'b10000))
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    begin
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      handle1 = $fopen(`GDB_OUT);
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      $fwrite(handle1, "%h", 5'b10000 | memory[0]);  // To ack to jp1 that we read dgb_out.dat
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      $fclose(handle1);
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    end
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  end
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end
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assign in_word = memory[0];
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assign Temp = in_word_r;
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always @ (posedge in_word[4] or posedge wb_rst_i)
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begin
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  if(wb_rst_i)
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    in_word_r<=#Tp 5'b0;
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  else
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    in_word_r<=#Tp in_word[3:0];
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end
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//always alternator = #100 ~alternator;
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always @ (posedge P_TCK or alternator)
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begin
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  handle2 = $fopen(`GDB_IN);
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  $fdisplay(handle2, "%b", P_TDO);  // Vriting output data to file (TDO)
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  $fclose(handle2);
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end
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assign P_TCK  = Temp[0];
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assign P_TRST = Temp[1];
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assign P_TDI  = Temp[2];
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assign P_TMS  = Temp[3];
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// Generating master clock (RISC clock) 10 MHz
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initial
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begin
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  Mclk<=#Tp 0;
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  #1 forever #`RISC_CLOCK Mclk<=~Mclk;
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end
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// Generating random number for use in DATAOUT_RISC[31:0]
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reg [31:0] RandNumb;
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always @ (posedge Mclk or posedge wb_rst_i)
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begin
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  if(wb_rst_i)
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    RandNumb[31:0]<=#Tp 0;
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  else
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    RandNumb[31:0]<=#Tp RandNumb[31:0] + 1;
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end
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wire [31:0] DataIn = RandNumb;
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// Connecting dbgTAP module
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`ifdef UNUSED
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dbg_top dbg1  (.tms_pad_i(P_TMS), .tck_pad_i(P_TCK), .trst_pad_i(P_TRST), .tdi_pad_i(P_TDI), .tdo_pad_o(P_TDO),
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               .wb_rst_i(wb_rst_i), .risc_clk_i(Mclk), .risc_addr_o(), .risc_data_i(DataIn),
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               .risc_data_o(), .wp_i(11'h0), .bp_i(1'b0),
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               .opselect_o(), .lsstatus_i(4'h0), .istatus_i(2'h0),
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               .risc_stall_o(), .reset_o()
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              );
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`endif
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endmodule // TAP
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`endif

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