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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbgTB_defines.v                                             ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/cores/DebugInterface/              ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000,2001 Authors                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/11/04 18:51:07  lampret
// First import.
//
// Revision 1.2  2001/09/18 14:12:43  mohor
// Trace fixed. Some registers changed, trace simplified.
//
// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
// Initial official release.
//
// Revision 1.3  2001/06/01 22:23:40  mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.2  2001/05/18 13:10:05  mohor
// Headers changed. All additional information is now avaliable in the README.txt file.
//
// Revision 1.1.1.1  2001/05/18 06:35:12  mohor
// Initial release
//
//
 
// Following defines are used in the testbench only
 
  // MODER register
  `define ENABLE          32'h00010000
  `define CONTIN          32'h00020000
 
  // TSEL register
  `define WPTRIG_0        32'h00000001
  `define WPTRIG_1        32'h00000002
  `define WPTRIG_2        32'h00000004
  `define WPTRIG_3        32'h00000008
  `define WPTRIG_4        32'h00000010
  `define WPTRIG_5        32'h00000020
  `define WPTRIG_6        32'h00000040
  `define WPTRIG_7        32'h00000080
  `define WPTRIG_8        32'h00000100
  `define WPTRIG_9        32'h00000200
  `define WPTRIG_10       32'h00000400
  `define WPTRIGVALID     32'h00000800
 
  `define BPTRIG          32'h00001000
  `define BPTRIGVALID     32'h00002000
 
  `define LSSTRIG_0       32'h00010000
  `define LSSTRIG_1       32'h00020000
  `define LSSTRIG_2       32'h00040000
  `define LSSTRIG_3       32'h00080000
  `define LSSTRIGVALID    32'h00100000
 
  `define ISTRIGVALID     32'h00800000
 
  `define TRIGOP_AND      32'hc0000000
  `define TRIGOP_OR       32'h80000000
 
  // QSEL register
  `define WPQUALIF_0      32'h00000001
  `define WPQUALIF_1      32'h00000002
  `define WPQUALIF_2      32'h00000004
  `define WPQUALIF_3      32'h00000008
  `define WPQUALIF_4      32'h00000010
  `define WPQUALIF_5      32'h00000020
  `define WPQUALIF_6      32'h00000040
  `define WPQUALIF_7      32'h00000080
  `define WPQUALIF_8      32'h00000100
  `define WPQUALIF_9      32'h00000200
  `define WPQUALIF_10     32'h00000400
  `define WPQUALIFVALID   32'h00000800
 
  `define BPQUALIF        32'h00001000
  `define BPQUALIFVALID   32'h00002000
 
  `define LSSQUALIF_0     32'h00010000
  `define LSSQUALIF_1     32'h00020000
  `define LSSQUALIF_2     32'h00040000
  `define LSSQUALIF_3     32'h00080000
  `define LSSQUALIFVALID  32'h00100000
 
  `define ISQUALIFVALID   32'h00800000
 
  `define QUALIFOP_AND    32'hc0000000
  `define QUALIFOP_OR     32'h80000000
 
 
  // SSEL register
  `define WPSTOP_0      32'h00000001
  `define WPSTOP_1      32'h00000002
  `define WPSTOP_2      32'h00000004
  `define WPSTOP_3      32'h00000008
  `define WPSTOP_4      32'h00000010
  `define WPSTOP_5      32'h00000020
  `define WPSTOP_6      32'h00000040
  `define WPSTOP_7      32'h00000080
  `define WPSTOP_8      32'h00000100
  `define WPSTOP_9      32'h00000200
  `define WPSTOP_10     32'h00000400
  `define WPSTOPVALID   32'h00000800
 
  `define BPSTOP        32'h00001000
  `define BPSTOPVALID   32'h00002000
 
  `define LSSSTOP_0     32'h00010000
  `define LSSSTOP_1     32'h00020000
  `define LSSSTOP_2     32'h00040000
  `define LSSSTOP_3     32'h00080000
  `define LSSSTOPVALID  32'h00100000
 
  `define ISSTOPVALID   32'h00800000
 
  `define STOPOP_AND    32'hc0000000
  `define STOPOP_OR     32'h80000000
 
  `define IS_NO_FETCH     32'h00000000
  `define IS_FETCH        32'h00200000
  `define IS_BRANCH       32'h00400000
  `define IS_FETCH_DELAY  32'h00600000
 
  `define LSS_NO_LOADSTORE      32'h00000000
  `define LSS_LOADBYTE_ZEROEXT  32'h00020000
  `define LSS_LOADBYTE_SIGNEXT  32'h00030000
  `define LSS_LOADHALF_ZEROEXT  32'h00040000
  `define LSS_LOADHALF_SIGNEXT  32'h00050000
  `define LSS_LOADWORD_ZEROEXT  32'h00060000
  `define LSS_LOADWORD_SIGNEXT  32'h00070000
  `define LSS_STORE_BYTE        32'h000A0000
  `define LSS_STORE_HALF        32'h000C0000
 
// End: Following defines are used in the testbench only
 
 

Line No.	Rev	Author	Line
1	779	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbgTB_defines.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/cores/DebugInterface/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is avaliable in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000,2001 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48			`// Revision 1.1.1.1 2001/11/04 18:51:07 lampret`
49			`// First import.`
50			`//`
51			`// Revision 1.2 2001/09/18 14:12:43 mohor`
52			`// Trace fixed. Some registers changed, trace simplified.`
53			`//`
54			`// Revision 1.1.1.1 2001/09/13 13:49:19 mohor`
55			`// Initial official release.`
56			`//`
57			`// Revision 1.3 2001/06/01 22:23:40 mohor`
58			`// This is a backup. It is not a fully working version. Not for use, yet.`
59			`//`
60			`// Revision 1.2 2001/05/18 13:10:05 mohor`
61			`// Headers changed. All additional information is now avaliable in the README.txt file.`
62			`//`
63			`// Revision 1.1.1.1 2001/05/18 06:35:12 mohor`
64			`// Initial release`
65			`//`
66			`//`
67
68			`// Following defines are used in the testbench only`
69
70			`// MODER register`
71			`define ENABLE 32'h00010000
72			`define CONTIN 32'h00020000
73
74			`// TSEL register`
75			`define WPTRIG_0 32'h00000001
76			`define WPTRIG_1 32'h00000002
77			`define WPTRIG_2 32'h00000004
78			`define WPTRIG_3 32'h00000008
79			`define WPTRIG_4 32'h00000010
80			`define WPTRIG_5 32'h00000020
81			`define WPTRIG_6 32'h00000040
82			`define WPTRIG_7 32'h00000080
83			`define WPTRIG_8 32'h00000100
84			`define WPTRIG_9 32'h00000200
85			`define WPTRIG_10 32'h00000400
86			`define WPTRIGVALID 32'h00000800
87
88			`define BPTRIG 32'h00001000
89			`define BPTRIGVALID 32'h00002000
90
91			`define LSSTRIG_0 32'h00010000
92			`define LSSTRIG_1 32'h00020000
93			`define LSSTRIG_2 32'h00040000
94			`define LSSTRIG_3 32'h00080000
95			`define LSSTRIGVALID 32'h00100000
96
97			`define ISTRIGVALID 32'h00800000
98
99			`define TRIGOP_AND 32'hc0000000
100			`define TRIGOP_OR 32'h80000000
101
102			`// QSEL register`
103			`define WPQUALIF_0 32'h00000001
104			`define WPQUALIF_1 32'h00000002
105			`define WPQUALIF_2 32'h00000004
106			`define WPQUALIF_3 32'h00000008
107			`define WPQUALIF_4 32'h00000010
108			`define WPQUALIF_5 32'h00000020
109			`define WPQUALIF_6 32'h00000040
110			`define WPQUALIF_7 32'h00000080
111			`define WPQUALIF_8 32'h00000100
112			`define WPQUALIF_9 32'h00000200
113			`define WPQUALIF_10 32'h00000400
114			`define WPQUALIFVALID 32'h00000800
115
116			`define BPQUALIF 32'h00001000
117			`define BPQUALIFVALID 32'h00002000
118
119			`define LSSQUALIF_0 32'h00010000
120			`define LSSQUALIF_1 32'h00020000
121			`define LSSQUALIF_2 32'h00040000
122			`define LSSQUALIF_3 32'h00080000
123			`define LSSQUALIFVALID 32'h00100000
124
125			`define ISQUALIFVALID 32'h00800000
126
127			`define QUALIFOP_AND 32'hc0000000
128			`define QUALIFOP_OR 32'h80000000
129
130
131			`// SSEL register`
132			`define WPSTOP_0 32'h00000001
133			`define WPSTOP_1 32'h00000002
134			`define WPSTOP_2 32'h00000004
135			`define WPSTOP_3 32'h00000008
136			`define WPSTOP_4 32'h00000010
137			`define WPSTOP_5 32'h00000020
138			`define WPSTOP_6 32'h00000040
139			`define WPSTOP_7 32'h00000080
140			`define WPSTOP_8 32'h00000100
141			`define WPSTOP_9 32'h00000200
142			`define WPSTOP_10 32'h00000400
143			`define WPSTOPVALID 32'h00000800
144
145			`define BPSTOP 32'h00001000
146			`define BPSTOPVALID 32'h00002000
147
148			`define LSSSTOP_0 32'h00010000
149			`define LSSSTOP_1 32'h00020000
150			`define LSSSTOP_2 32'h00040000
151			`define LSSSTOP_3 32'h00080000
152			`define LSSSTOPVALID 32'h00100000
153
154			`define ISSTOPVALID 32'h00800000
155
156			`define STOPOP_AND 32'hc0000000
157			`define STOPOP_OR 32'h80000000
158
159			`define IS_NO_FETCH 32'h00000000
160			`define IS_FETCH 32'h00200000
161			`define IS_BRANCH 32'h00400000
162			`define IS_FETCH_DELAY 32'h00600000
163
164			`define LSS_NO_LOADSTORE 32'h00000000
165			`define LSS_LOADBYTE_ZEROEXT 32'h00020000
166			`define LSS_LOADBYTE_SIGNEXT 32'h00030000
167			`define LSS_LOADHALF_ZEROEXT 32'h00040000
168			`define LSS_LOADHALF_SIGNEXT 32'h00050000
169			`define LSS_LOADWORD_ZEROEXT 32'h00060000
170			`define LSS_LOADWORD_SIGNEXT 32'h00070000
171			`define LSS_STORE_BYTE 32'h000A0000
172			`define LSS_STORE_HALF 32'h000C0000
173
174			`// End: Following defines are used in the testbench only`
175
176

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[/] [or1k_old/] [trunk/] [orp/] [orp_soc/] [bench/] [verilog/] [dbg_tb_defines.v] - Blame information for rev 1765