URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] [or1k_old/] [trunk/] [orp/] [orp_soc/] [bench/] [verilog/] [or1200_monitor.v] - Blame information for rev 1135

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's simulation monitor                                 ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Simulation monitor                                          ////
////                                                              ////
////  To Do:                                                      ////
////   - move it to bench                                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2002/08/12 05:38:11  lampret
// Added more WISHBONE protocol checks. Removed nop.log. Added general.log and lookup.log.
//
// Revision 1.1  2002/03/28 19:59:55  lampret
// Added bench directory
//
// Revision 1.9  2002/02/01 19:56:54  lampret
// Fixed combinational loops.
//
// Revision 1.8  2002/01/28 01:25:22  lampret
// Fixed display of new 'void' nop insns.
//
// Revision 1.7  2002/01/19 14:10:39  lampret
// Fixed OR1200_XILINX_RAM32X1D.
//
// Revision 1.6  2002/01/18 07:57:56  lampret
// Added support for reading XILINX_RAM32X1D register file.
//
// Revision 1.5  2002/01/14 06:19:35  lampret
// Added debug model for testing du. Updated or1200_monitor.
//
// Revision 1.4  2002/01/03 08:40:15  lampret
// Added second clock as RISC main clock. Updated or120_monitor.
//
// Revision 1.3  2001/11/23 08:50:35  lampret
// Typos.
//
// Revision 1.2  2001/11/10 04:22:55  lampret
// Modified monitor tu support exceptions.
//
// Revision 1.1.1.1  2001/11/04 18:51:07  lampret
// First import.
//
// Revision 1.1  2001/08/20 18:17:52  damjan
// Initial revision
//
// Revision 1.1  2001/08/13 03:37:07  lampret
// Added monitor.v and timescale.v
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
`include "or1200_defines.v"
 
//
// Top of OR1200 inside test bench
//
`define OR1200_TOP xess_top.i_xess_fpga.or1200_top
 
//
// Enable display_arch_state task
//
`define OR1200_DISPLAY_ARCH_STATE
 
module or1200_monitor;
 
integer fexe;
reg [23:0]  ref;
integer fspr;
integer fgeneral;
integer flookup;
integer r3;
integer insns;
 
//
// Initialization
//
initial begin
        ref = 0;
        fexe = $fopen("executed.log");
        $timeformat (-9, 2, " ns", 12);
        fspr = $fopen("sprs.log");
        fgeneral = $fopen("general.log");
        flookup = $fopen("lookup.log");
        insns = 0;
end
 
//
// Get GPR
//
task get_gpr;
input   [4:0]    gpr_no;
output  [31:0]   gpr;
integer j;
begin
`ifdef OR1200_RFRAM_GENERIC
        for(j = 0; j < 32; j = j + 1) begin
                gpr[j] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[gpr_no*32+j];
        end
`else
`ifdef OR1200_XILINX_RAM32X1D
                gpr[0] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0.mem[gpr_no];
                gpr[1] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1.mem[gpr_no];
                gpr[2] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_2.mem[gpr_no];
                gpr[3] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_3.mem[gpr_no];
                gpr[4] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_4.mem[gpr_no];
                gpr[5] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_5.mem[gpr_no];
                gpr[6] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_6.mem[gpr_no];
                gpr[7] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_7.mem[gpr_no];
                gpr[8] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0.mem[gpr_no];
                gpr[9] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1.mem[gpr_no];
                gpr[10] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_2.mem[gpr_no];
                gpr[11] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_3.mem[gpr_no];
                gpr[12] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_4.mem[gpr_no];
                gpr[13] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_5.mem[gpr_no];
                gpr[14] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_6.mem[gpr_no];
                gpr[15] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_7.mem[gpr_no];
                gpr[16] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0.mem[gpr_no];
                gpr[17] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1.mem[gpr_no];
                gpr[18] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_2.mem[gpr_no];
                gpr[19] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_3.mem[gpr_no];
                gpr[20] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_4.mem[gpr_no];
                gpr[21] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_5.mem[gpr_no];
                gpr[22] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_6.mem[gpr_no];
                gpr[23] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_7.mem[gpr_no];
                gpr[24] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0.mem[gpr_no];
                gpr[25] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1.mem[gpr_no];
                gpr[26] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_2.mem[gpr_no];
                gpr[27] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_3.mem[gpr_no];
                gpr[28] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_4.mem[gpr_no];
                gpr[29] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_5.mem[gpr_no];
                gpr[30] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_6.mem[gpr_no];
                gpr[31] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_7.mem[gpr_no];
`else
`ifdef OR1200_XILINX_RAMB4
        for(j = 0; j < 16; j = j + 1) begin
                gpr[j] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.ramb4_s16_0.mem[gpr_no*16+j];
        end
        for(j = 0; j < 16; j = j + 1) begin
                gpr[j+16] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.ramb4_s16_1.mem[gpr_no*16+j];
        end
`else
`ifdef OR1200_ARTISAN_SDP
`else
        gpr = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[gpr_no];
`endif
`endif
`endif
`endif
end
endtask
 
//
// Write state of the OR1200 registers into a file
//
// Limitation: only a small subset of register file RAMs
// are supported
//
task display_arch_state;
reg [5:0] i;
reg [31:0] r;
integer j;
begin
`ifdef OR1200_DISPLAY_ARCH_STATE
        ref = ref + 1;
        $fdisplay(flookup, "Instruction %d: %t", insns, $time);
        $fwrite(fexe, "\nEXECUTED(%d): %h:  %h", insns, `OR1200_TOP.or1200_cpu.or1200_except.wb_pc, `OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn);
        for(i = 0; i < 32; i = i + 1) begin
                if (i % 4 == 0)
                        $fdisplay(fexe);
                get_gpr(i, r);
                $fwrite(fexe, "GPR%d: %h  ", i, r);
        end
        $fdisplay(fexe);
        r = `OR1200_TOP.or1200_cpu.or1200_sprs.sr;
        $fwrite(fexe, "SR   : %h  ", r);
        r = `OR1200_TOP.or1200_cpu.or1200_sprs.epcr;
        $fwrite(fexe, "EPCR0: %h  ", r);
        r = `OR1200_TOP.or1200_cpu.or1200_sprs.eear;
        $fwrite(fexe, "EEAR0: %h  ", r);
        r = `OR1200_TOP.or1200_cpu.or1200_sprs.esr;
        $fdisplay(fexe, "ESR0 : %h", r);
        insns = insns + 1;
`endif
end
endtask
 
integer iwb_progress;
reg [31:0] iwb_progress_addr;
//
// WISHBONE bus checker
//
always @(posedge `OR1200_TOP.iwb_clk_i)
        if (`OR1200_TOP.iwb_rst_i) begin
                iwb_progress = 0;
                iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
        end
        else begin
                if (`OR1200_TOP.iwb_cyc_o && (iwb_progress != 2)) begin
                        iwb_progress = 1;
                end
                if (`OR1200_TOP.iwb_stb_o) begin
                        if (iwb_progress >= 1) begin
                                if (iwb_progress == 1)
                                        iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
                                iwb_progress = 2;
                        end
                        else begin
                                $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o raised without `OR1200_TOP.iwb_cyc_o, at %t\n", $time);
                                #100 $finish;
                        end
                end
                if (`OR1200_TOP.iwb_ack_i & `OR1200_TOP.iwb_err_i) begin
                        $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i and `OR1200_TOP.iwb_err_i raised at the same time, at %t\n", $time);
                end
                if ((iwb_progress == 2) && (iwb_progress_addr != `OR1200_TOP.iwb_adr_o)) begin
                        $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_adr_o changed while waiting for `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
                        #100 $finish;
                end
                if (`OR1200_TOP.iwb_ack_i | `OR1200_TOP.iwb_err_i)
                        if (iwb_progress == 2) begin
                                iwb_progress = 0;
                                iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
                        end
                        else begin
                                $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i/`OR1200_TOP.iwb_err_i raised without `OR1200_TOP.iwb_cyc_i/`OR1200_TOP.iwb_stb_i, at %t\n", $time);
                                #100 $finish;
                        end
                if ((iwb_progress == 2) && !`OR1200_TOP.iwb_stb_o) begin
                        $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o lowered without `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
/*                      #100 $finish;*/
                end
        end
 
integer dwb_progress;
reg [31:0] dwb_progress_addr;
//
// WISHBONE bus checker
//
always @(posedge `OR1200_TOP.dwb_clk_i)
        if (`OR1200_TOP.dwb_rst_i)
                dwb_progress = 0;
        else begin
                if (`OR1200_TOP.dwb_cyc_o && (dwb_progress != 2))
                        dwb_progress = 1;
                if (`OR1200_TOP.dwb_stb_o)
                        if (dwb_progress >= 1) begin
                                if (dwb_progress == 1)
                                        dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
                                dwb_progress = 2;
                        end
                        else begin
                                $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o raised without `OR1200_TOP.dwb_cyc_o, at %t\n", $time);
                                #100 $finish;
                        end
                if (`OR1200_TOP.dwb_ack_i & `OR1200_TOP.dwb_err_i) begin
                        $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i and `OR1200_TOP.dwb_err_i raised at the same time, at %t\n", $time);
                end
                if ((dwb_progress == 2) && (dwb_progress_addr != `OR1200_TOP.dwb_adr_o)) begin
                        $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_adr_o changed while waiting for `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
                        #100 $finish;
                end
                if (`OR1200_TOP.dwb_ack_i | `OR1200_TOP.dwb_err_i)
                        if (dwb_progress == 2) begin
                                dwb_progress = 0;
                                dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
                        end
                        else begin
                                $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i/`OR1200_TOP.dwb_err_i raised without `OR1200_TOP.dwb_cyc_i/`OR1200_TOP.dwb_stb_i, at %t\n", $time);
                                #100 $finish;
                        end
                if ((dwb_progress == 2) && !`OR1200_TOP.dwb_stb_o) begin
                        $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o lowered without `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
                        #100 $finish;
                end
        end
 
//
// Hooks for:
// - displaying registers
// - end of simulation
// - access to SPRs
//
always @(posedge `OR1200_TOP.or1200_cpu.or1200_ctrl.clk)
        if (!`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_freeze) begin
                #2;
                if (((`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[31:26] != `OR1200_OR32_NOP) || !`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[16])
                        && !(`OR1200_TOP.or1200_cpu.or1200_except.except_flushpipe && `OR1200_TOP.or1200_cpu.or1200_except.ex_dslot))
                        display_arch_state;
                if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0001) begin // small hack to stop simulation (l.nop 1)
                        get_gpr(3, r3);
                        $fdisplay(fgeneral, "%t: l.nop exit (%h)", $time, r3);
                        $finish;
                end
                if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0002) begin // simulation reports (l.nop 2)
                        get_gpr(3, r3);
                        $fdisplay(fgeneral, "%t: l.nop report (%h)", $time, r3);
                end
                if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0003) begin // simulation printfs (l.nop 3)
                        get_gpr(3, r3);
                        $fdisplay(fgeneral, "%t: l.nop printf (%h)", $time, r3);
                end
                if (`OR1200_TOP.or1200_cpu.or1200_sprs.sprs_op == `OR1200_ALUOP_MTSR)  // l.mtspr
                        $fdisplay(fspr, "%t: Write to SPR : [%h] <- %h", $time,
                        `OR1200_TOP.or1200_cpu.or1200_sprs.spr_addr, `OR1200_TOP.or1200_cpu.or1200_sprs.spr_dat_o);
                if (`OR1200_TOP.or1200_cpu.or1200_sprs.sprs_op == `OR1200_ALUOP_MFSR)  // l.mfspr
                        $fdisplay(fspr, "%t: Read from SPR: [%h] -> %h", $time,
                        `OR1200_TOP.or1200_cpu.or1200_sprs.spr_addr, `OR1200_TOP.or1200_cpu.or1200_sprs.to_wbmux);
        end
 
endmodule

Line No.	Rev	Author	Line
1	779	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's simulation monitor ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Simulation monitor ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - move it to bench ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	1135	lampret	`// Revision 1.2 2002/08/12 05:38:11 lampret`
48			`// Added more WISHBONE protocol checks. Removed nop.log. Added general.log and lookup.log.`
49			`//`
50	949	lampret	`// Revision 1.1 2002/03/28 19:59:55 lampret`
51			`// Added bench directory`
52			`//`
53	779	lampret	`// Revision 1.9 2002/02/01 19:56:54 lampret`
54			`// Fixed combinational loops.`
55			`//`
56			`// Revision 1.8 2002/01/28 01:25:22 lampret`
57			`// Fixed display of new 'void' nop insns.`
58			`//`
59			`// Revision 1.7 2002/01/19 14:10:39 lampret`
60			`// Fixed OR1200_XILINX_RAM32X1D.`
61			`//`
62			`// Revision 1.6 2002/01/18 07:57:56 lampret`
63			`// Added support for reading XILINX_RAM32X1D register file.`
64			`//`
65			`// Revision 1.5 2002/01/14 06:19:35 lampret`
66			`// Added debug model for testing du. Updated or1200_monitor.`
67			`//`
68			`// Revision 1.4 2002/01/03 08:40:15 lampret`
69			`// Added second clock as RISC main clock. Updated or120_monitor.`
70			`//`
71			`// Revision 1.3 2001/11/23 08:50:35 lampret`
72			`// Typos.`
73			`//`
74			`// Revision 1.2 2001/11/10 04:22:55 lampret`
75			`// Modified monitor tu support exceptions.`
76			`//`
77			`// Revision 1.1.1.1 2001/11/04 18:51:07 lampret`
78			`// First import.`
79			`//`
80			`// Revision 1.1 2001/08/20 18:17:52 damjan`
81			`// Initial revision`
82			`//`
83			`// Revision 1.1 2001/08/13 03:37:07 lampret`
84			`// Added monitor.v and timescale.v`
85			`//`
86			`// Revision 1.1 2001/07/20 00:46:03 lampret`
87			`// Development version of RTL. Libraries are missing.`
88			`//`
89			`//`
90
91			`include "or1200_defines.v"
92
93			`//`
94			`// Top of OR1200 inside test bench`
95			`//`
96			`define OR1200_TOP xess_top.i_xess_fpga.or1200_top
97
98			`//`
99			`// Enable display_arch_state task`
100			`//`
101			`define OR1200_DISPLAY_ARCH_STATE
102
103			`module or1200_monitor;`
104
105			`integer fexe;`
106			`reg [23:0] ref;`
107			`integer fspr;`
108	949	lampret	`integer fgeneral;`
109			`integer flookup;`
110	779	lampret	`integer r3;`
111	949	lampret	`integer insns;`
112	779	lampret
113			`//`
114			`// Initialization`
115			`//`
116			`initial begin`
117			`ref = 0;`
118			`fexe = $fopen("executed.log");`
119			`$timeformat (-9, 2, " ns", 12);`
120			`fspr = $fopen("sprs.log");`
121	949	lampret	`fgeneral = $fopen("general.log");`
122			`flookup = $fopen("lookup.log");`
123			`insns = 0;`
124	779	lampret	`end`
125
126			`//`
127			`// Get GPR`
128			`//`
129			`task get_gpr;`
130			`input [4:0] gpr_no;`
131			`output [31:0] gpr;`
132			`integer j;`
133			`begin`
134	1135	lampret	`ifdef OR1200_RFRAM_GENERIC
135			`for(j = 0; j < 32; j = j + 1) begin`
136			gpr[j] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[gpr_no*32+j];
137			`end`
138			`else
139	779	lampret	`ifdef OR1200_XILINX_RAM32X1D
140			gpr[0] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0.mem[gpr_no];
141			gpr[1] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1.mem[gpr_no];
142			gpr[2] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_2.mem[gpr_no];
143			gpr[3] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_3.mem[gpr_no];
144			gpr[4] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_4.mem[gpr_no];
145			gpr[5] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_5.mem[gpr_no];
146			gpr[6] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_6.mem[gpr_no];
147			gpr[7] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_7.mem[gpr_no];
148			gpr[8] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0.mem[gpr_no];
149			gpr[9] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1.mem[gpr_no];
150			gpr[10] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_2.mem[gpr_no];
151			gpr[11] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_3.mem[gpr_no];
152			gpr[12] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_4.mem[gpr_no];
153			gpr[13] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_5.mem[gpr_no];
154			gpr[14] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_6.mem[gpr_no];
155			gpr[15] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_7.mem[gpr_no];
156			gpr[16] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0.mem[gpr_no];
157			gpr[17] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1.mem[gpr_no];
158			gpr[18] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_2.mem[gpr_no];
159			gpr[19] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_3.mem[gpr_no];
160			gpr[20] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_4.mem[gpr_no];
161			gpr[21] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_5.mem[gpr_no];
162			gpr[22] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_6.mem[gpr_no];
163			gpr[23] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_7.mem[gpr_no];
164			gpr[24] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0.mem[gpr_no];
165			gpr[25] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1.mem[gpr_no];
166			gpr[26] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_2.mem[gpr_no];
167			gpr[27] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_3.mem[gpr_no];
168			gpr[28] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_4.mem[gpr_no];
169			gpr[29] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_5.mem[gpr_no];
170			gpr[30] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_6.mem[gpr_no];
171			gpr[31] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_7.mem[gpr_no];
172			`else
173			`ifdef OR1200_XILINX_RAMB4
174			`for(j = 0; j < 16; j = j + 1) begin`
175			gpr[j] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.ramb4_s16_0.mem[gpr_no*16+j];
176			`end`
177			`for(j = 0; j < 16; j = j + 1) begin`
178			gpr[j+16] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.ramb4_s16_1.mem[gpr_no*16+j];
179			`end`
180			`else
181			`ifdef OR1200_ARTISAN_SDP
182			`else
183			gpr = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[gpr_no];
184			`endif
185			`endif
186			`endif
187	1135	lampret	`endif
188	779	lampret	`end`
189			`endtask`
190
191			`//`
192			`// Write state of the OR1200 registers into a file`
193			`//`
194			`// Limitation: only a small subset of register file RAMs`
195			`// are supported`
196			`//`
197			`task display_arch_state;`
198			`reg [5:0] i;`
199			`reg [31:0] r;`
200			`integer j;`
201			`begin`
202			`ifdef OR1200_DISPLAY_ARCH_STATE
203			`ref = ref + 1;`
204	949	lampret	`$fdisplay(flookup, "Instruction %d: %t", insns, $time);`
205			$fwrite(fexe, "\nEXECUTED(%d): %h: %h", insns, `OR1200_TOP.or1200_cpu.or1200_except.wb_pc, `OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn);
206	779	lampret	`for(i = 0; i < 32; i = i + 1) begin`
207			`if (i % 4 == 0)`
208			`$fdisplay(fexe);`
209			`get_gpr(i, r);`
210			`$fwrite(fexe, "GPR%d: %h ", i, r);`
211			`end`
212			`$fdisplay(fexe);`
213			r = `OR1200_TOP.or1200_cpu.or1200_sprs.sr;
214			`$fwrite(fexe, "SR : %h ", r);`
215			r = `OR1200_TOP.or1200_cpu.or1200_sprs.epcr;
216			`$fwrite(fexe, "EPCR0: %h ", r);`
217			r = `OR1200_TOP.or1200_cpu.or1200_sprs.eear;
218			`$fwrite(fexe, "EEAR0: %h ", r);`
219			r = `OR1200_TOP.or1200_cpu.or1200_sprs.esr;
220			`$fdisplay(fexe, "ESR0 : %h", r);`
221	949	lampret	`insns = insns + 1;`
222	779	lampret	`endif
223			`end`
224			`endtask`
225
226	949	lampret	`integer iwb_progress;`
227			`reg [31:0] iwb_progress_addr;`
228	779	lampret	`//`
229	949	lampret	`// WISHBONE bus checker`
230			`//`
231			always @(posedge `OR1200_TOP.iwb_clk_i)
232			if (`OR1200_TOP.iwb_rst_i) begin
233			`iwb_progress = 0;`
234			iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
235			`end`
236			`else begin`
237			if (`OR1200_TOP.iwb_cyc_o && (iwb_progress != 2)) begin
238			`iwb_progress = 1;`
239			`end`
240			if (`OR1200_TOP.iwb_stb_o) begin
241			`if (iwb_progress >= 1) begin`
242			`if (iwb_progress == 1)`
243			iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
244			`iwb_progress = 2;`
245			`end`
246			`else begin`
247			$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o raised without `OR1200_TOP.iwb_cyc_o, at %t\n", $time);
248			`#100 $finish;`
249			`end`
250			`end`
251			if (`OR1200_TOP.iwb_ack_i & `OR1200_TOP.iwb_err_i) begin
252			$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i and `OR1200_TOP.iwb_err_i raised at the same time, at %t\n", $time);
253			`end`
254			if ((iwb_progress == 2) && (iwb_progress_addr != `OR1200_TOP.iwb_adr_o)) begin
255			$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_adr_o changed while waiting for `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
256			`#100 $finish;`
257			`end`
258			if (`OR1200_TOP.iwb_ack_i \| `OR1200_TOP.iwb_err_i)
259			`if (iwb_progress == 2) begin`
260			`iwb_progress = 0;`
261			iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
262			`end`
263			`else begin`
264			$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i/`OR1200_TOP.iwb_err_i raised without `OR1200_TOP.iwb_cyc_i/`OR1200_TOP.iwb_stb_i, at %t\n", $time);
265			`#100 $finish;`
266			`end`
267			if ((iwb_progress == 2) && !`OR1200_TOP.iwb_stb_o) begin
268			$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o lowered without `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
269			`/* #100 $finish;*/`
270			`end`
271			`end`
272
273			`integer dwb_progress;`
274			`reg [31:0] dwb_progress_addr;`
275			`//`
276			`// WISHBONE bus checker`
277			`//`
278			always @(posedge `OR1200_TOP.dwb_clk_i)
279			if (`OR1200_TOP.dwb_rst_i)
280			`dwb_progress = 0;`
281			`else begin`
282			if (`OR1200_TOP.dwb_cyc_o && (dwb_progress != 2))
283			`dwb_progress = 1;`
284			if (`OR1200_TOP.dwb_stb_o)
285			`if (dwb_progress >= 1) begin`
286			`if (dwb_progress == 1)`
287			dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
288			`dwb_progress = 2;`
289			`end`
290			`else begin`
291			$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o raised without `OR1200_TOP.dwb_cyc_o, at %t\n", $time);
292			`#100 $finish;`
293			`end`
294			if (`OR1200_TOP.dwb_ack_i & `OR1200_TOP.dwb_err_i) begin
295			$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i and `OR1200_TOP.dwb_err_i raised at the same time, at %t\n", $time);
296			`end`
297			if ((dwb_progress == 2) && (dwb_progress_addr != `OR1200_TOP.dwb_adr_o)) begin
298			$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_adr_o changed while waiting for `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
299			`#100 $finish;`
300			`end`
301			if (`OR1200_TOP.dwb_ack_i \| `OR1200_TOP.dwb_err_i)
302			`if (dwb_progress == 2) begin`
303			`dwb_progress = 0;`
304			dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
305			`end`
306			`else begin`
307			$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i/`OR1200_TOP.dwb_err_i raised without `OR1200_TOP.dwb_cyc_i/`OR1200_TOP.dwb_stb_i, at %t\n", $time);
308			`#100 $finish;`
309			`end`
310			if ((dwb_progress == 2) && !`OR1200_TOP.dwb_stb_o) begin
311			$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o lowered without `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
312			`#100 $finish;`
313			`end`
314			`end`
315
316			`//`
317	779	lampret	`// Hooks for:`
318			`// - displaying registers`
319			`// - end of simulation`
320			`// - access to SPRs`
321			`//`
322			always @(posedge `OR1200_TOP.or1200_cpu.or1200_ctrl.clk)
323			if (!`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_freeze) begin
324			`#2;`
325			if (((`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[31:26] != `OR1200_OR32_NOP) \|\| !`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[16])
326			&& !(`OR1200_TOP.or1200_cpu.or1200_except.except_flushpipe && `OR1200_TOP.or1200_cpu.or1200_except.ex_dslot))
327			`display_arch_state;`
328			if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0001) begin // small hack to stop simulation (l.nop 1)
329			`get_gpr(3, r3);`
330	949	lampret	`$fdisplay(fgeneral, "%t: l.nop exit (%h)", $time, r3);`
331	779	lampret	`$finish;`
332			`end`
333			if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0002) begin // simulation reports (l.nop 2)
334			`get_gpr(3, r3);`
335	949	lampret	`$fdisplay(fgeneral, "%t: l.nop report (%h)", $time, r3);`
336	779	lampret	`end`
337			if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0003) begin // simulation printfs (l.nop 3)
338			`get_gpr(3, r3);`
339	949	lampret	`$fdisplay(fgeneral, "%t: l.nop printf (%h)", $time, r3);`
340	779	lampret	`end`
341			if (`OR1200_TOP.or1200_cpu.or1200_sprs.sprs_op == `OR1200_ALUOP_MTSR) // l.mtspr
342			`$fdisplay(fspr, "%t: Write to SPR : [%h] <- %h", $time,`
343			`OR1200_TOP.or1200_cpu.or1200_sprs.spr_addr, `OR1200_TOP.or1200_cpu.or1200_sprs.spr_dat_o);
344			if (`OR1200_TOP.or1200_cpu.or1200_sprs.sprs_op == `OR1200_ALUOP_MFSR) // l.mfspr
345			`$fdisplay(fspr, "%t: Read from SPR: [%h] -> %h", $time,`
346			`OR1200_TOP.or1200_cpu.or1200_sprs.spr_addr, `OR1200_TOP.or1200_cpu.or1200_sprs.to_wbmux);
347			`end`
348
349			`endmodule`

Browse

Tools

Subversion Repositories or1k_old

[/] [or1k_old/] [trunk/] [orp/] [orp_soc/] [bench/] [verilog/] [or1200_monitor.v] - Blame information for rev 1135