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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  XESS SRAM interface                                         ////
////                                                              ////
////  This file is part of the OR1K test application              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Connects the SoC to SRAM. It does RMW for byte accesses     ////
////  because XSV board has WEs on a 16-bit basis.                ////
////                                                              ////
////  To Do:                                                      ////
////   - nothing really                                           ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Srot, simons@opencores.org                      ////
////      - Igor Mohor, igorm@opencores.org                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2002/08/12 05:34:06  lampret
// Added SRAM_GENERIC
//
// Revision 1.1.1.1  2002/03/21 16:55:44  lampret
// First import of the "new" XESS XSV environment.
//
//
// Revision 1.3  2002/01/23 07:50:44  lampret
// Added wb_err_o to flash and sram i/f for testing the buserr exception.
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1.1.1  2001/11/04 19:00:09  lampret
// First import.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
`define SRAM_GENERIC
 
`ifdef SRAM_GENERIC
 
module sram_top (
  wb_clk_i, wb_rst_i,
 
  wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
  wb_stb_i, wb_ack_o, wb_err_o,
 
  r_cen, r0_wen, r1_wen, r_oen, r_a, r_d_i, r_d_o, d_oe,
  l_cen, l0_wen, l1_wen, l_oen, l_a, l_d_i, l_d_o
);
 
//
// Paraneters
//
parameter               aw = 19;
 
//
// I/O Ports
//
input                   wb_clk_i;
input                   wb_rst_i;
 
//
// WB slave i/f
//
input   [31:0]           wb_dat_i;
output  [31:0]           wb_dat_o;
input   [31:0]           wb_adr_i;
input   [3:0]            wb_sel_i;
input                   wb_we_i;
input                   wb_cyc_i;
input                   wb_stb_i;
output                  wb_ack_o;
output                  wb_err_o;
 
//
// Right SRAM bank
//
output                  r_oen;
output                  r0_wen;
output                  r1_wen;
output                  r_cen;
input   [15:0]           r_d_i;
output  [15:0]           r_d_o;
output  [aw-1:0] r_a;
 
//
// Left SRAM bank
//
output                  l_oen;
output                  l0_wen;
output                  l1_wen;
output                  l_cen;
input   [15:0]           l_d_i;
output  [15:0]           l_d_o;
output  [aw-1:0] l_a;
 
//
// Common SRAM signals
//
output                  d_oe;
 
//
// Internal wires and regs
//
reg     [7:0]           mem [2097151:0];
wire    [31:0]          adr;
`ifdef SRAM_GENERIC_REGISTERED
reg                     wb_ack_o;
reg                     wb_err_o;
reg     [31:0]          wb_dat_o;
`endif
wire                    wb_err;
 
//
// Aliases and simple assignments
//
assign wb_err = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:21]);     // If Access to > 2MB (8-bit leading prefix ignored)
assign adr = {8'h00, wb_adr_i[23:2], 2'b00};
 
`ifdef SRAM_GENERIC_REGISTERED
//
// Reading from SRAM model
//
always @(posedge wb_rst_i or posedge wb_clk_i)
        if (wb_rst_i)
                wb_dat_o <= #1 32'h0000_0000;
        else begin
                wb_dat_o[7:0] <= #1 mem[adr+3];
                wb_dat_o[15:8] <= #1 mem[adr+2];
                wb_dat_o[23:16] <= #1 mem[adr+1];
                wb_dat_o[31:24] <= #1 mem[adr+0];
        end
`else
assign wb_dat_o[7:0] = mem[adr+3];
assign wb_dat_o[15:8] = mem[adr+2];
assign wb_dat_o[23:16] = mem[adr+1];
assign wb_dat_o[31:24] = mem[adr+0];
`endif
 
//
// Writing to SRAM model
//
always @(posedge wb_rst_i or posedge wb_clk_i)
        if (wb_cyc_i & wb_stb_i & wb_we_i) begin
                if (wb_sel_i[0])
                        mem[adr+3] <= #1 wb_dat_i[7:0];
                if (wb_sel_i[1])
                        mem[adr+2] <= #1 wb_dat_i[15:8];
                if (wb_sel_i[2])
                        mem[adr+1] <= #1 wb_dat_i[23:16];
                if (wb_sel_i[3])
                        mem[adr+0] <= #1 wb_dat_i[31:24];
        end
 
`ifdef SRAM_GENERIC_REGISTERED
//
// WB Acknowledge
//
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_ack_o <= #1 1'b0;
        else
                wb_ack_o <= #1 wb_cyc_i & wb_stb_i & !wb_ack_o;
`else
assign wb_ack_o = wb_cyc_i & wb_stb_i;
`endif
 
`ifdef SRAM_GENERIC_REGISTERED
//
// WB Error
//
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_err_o <= #1 1'b0;
        else
                wb_err_o <= #1 wb_err & !wb_err_o;
`else
assign wb_err_o = wb_err;
`endif
 
//
// Flash i/f monitor
//
// synopsys translate_off
integer fsram;
initial fsram = $fopen("sram.log");
always @(posedge wb_clk_i)
        if (wb_cyc_i)
                if (wb_stb_i & wb_we_i) begin
                        if (wb_sel_i[3])
                                mem[{wb_adr_i[23:2], 2'b00}+0] = wb_dat_i[31:24];
                        if (wb_sel_i[2])
                                mem[{wb_adr_i[23:2], 2'b00}+1] = wb_dat_i[23:16];
                        if (wb_sel_i[1])
                                mem[{wb_adr_i[23:2], 2'b00}+2] = wb_dat_i[15:8];
                        if (wb_sel_i[0])
                                mem[{wb_adr_i[23:2], 2'b00}+3] = wb_dat_i[7:0];
                        $fdisplay(fsram, "%t [%h] <- write %h, byte sel %b", $time, wb_adr_i, wb_dat_i, wb_sel_i);
                end else if (wb_ack_o)
                        $fdisplay(fsram, "%t [%h] -> read %h", $time, wb_adr_i, wb_dat_o);
// synopsys translate_on
 
endmodule
 
`else
 
module sram_top (
  wb_clk_i, wb_rst_i,
 
  wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
  wb_stb_i, wb_ack_o, wb_err_o,
 
  r_cen, r0_wen, r1_wen, r_oen, r_a, r_d_i, r_d_o, d_oe,
  l_cen, l0_wen, l1_wen, l_oen, l_a, l_d_i, l_d_o
);
 
//
// Paraneters
//
parameter               aw = 19;
 
//
// I/O Ports
//
input                   wb_clk_i;
input                   wb_rst_i;
 
//
// WB slave i/f
//
input   [31:0]           wb_dat_i;
output  [31:0]           wb_dat_o;
input   [31:0]           wb_adr_i;
input   [3:0]            wb_sel_i;
input                   wb_we_i;
input                   wb_cyc_i;
input                   wb_stb_i;
output                  wb_ack_o;
output                  wb_err_o;
 
//
// Right SRAM bank
//
output                  r_oen;
output                  r0_wen;
output                  r1_wen;
output                  r_cen;
input   [15:0]           r_d_i;
output  [15:0]           r_d_o;
output  [aw-1:0] r_a;
 
//
// Left SRAM bank
//
output                  l_oen;
output                  l0_wen;
output                  l1_wen;
output                  l_cen;
input   [15:0]           l_d_i;
output  [15:0]           l_d_o;
output  [aw-1:0] l_a;
 
//
// Common SRAM signals
//
output                  d_oe;
 
//
// Internal regs and wires
//
reg     [15:0]           r_data;
reg     [15:0]           l_data;
reg                     l0_wen;
wire                    l1_wen = l0_wen;
reg                     r0_wen;
wire                    r1_wen = r0_wen;
reg     [31:0]           latch_data;
reg                     ack_we;
wire                    l_oe;
wire                    r_oe;
wire                    r_ack;
reg                     Mux;
reg     [aw-1:0] LatchedAddr;
reg     [15:0]           l_read;
reg     [15:0]           r_read;
reg                     d_oe;
reg     [15:0]           l_mux;
reg     [15:0]           r_mux;
 
//
// Aliases and simple assignments
//
assign wb_dat_o = {r_d_i, l_d_i};
assign l_oen = ~l_oe;
assign r_oen = ~r_oe;
assign l_a = Mux ? LatchedAddr : wb_adr_i[aw+1:2];
assign r_a = l_a;
assign l_d_o = l_mux;
assign r_d_o = r_mux;
assign l_oe = wb_cyc_i & wb_stb_i & l0_wen;
assign r_oe = wb_cyc_i & wb_stb_i & r0_wen;
assign l_cen = ~(wb_cyc_i & wb_stb_i);
assign r_cen = l_cen;
assign wb_ack_o = (wb_cyc_i & wb_stb_i & ~wb_we_i) | ack_we;
assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[27:21]);     // If Access to > 2MB (4-bit leading prefix ignored)
 
//
// RMW mux control
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    Mux <= 1'b0;
  else
  if (ack_we)
    Mux <= #1 1'b1;
  else
    Mux <= #1 1'b0;
end
 
//
// Latch address
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    LatchedAddr <= 'h0;
  else
  if (wb_cyc_i & wb_stb_i)
    LatchedAddr <= #1 wb_adr_i[aw+1:2];
end
 
//
// Latch data from RAM (read data)
//
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    begin
      l_read <= 16'h0;
      r_read <= 16'h0;
    end
  else
  if (wb_cyc_i & wb_stb_i)
    begin
      l_read <= #1 l_d_i[15:0];
      r_read <= #1 r_d_i[15:0];
    end
end
 
//
// Mux and latch data for writing left SRAM bank (bytes 0 and 1)
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    l_mux <= 16'h0;
  else
  if (~l0_wen)
    begin
      if (wb_sel_i[0])
        l_mux[7:0]  <= #1 wb_dat_i[7:0];
      else
        l_mux[7:0]  <= #1 l_read[7:0];
      if (wb_sel_i[1])
        l_mux[15:8] <= #1 wb_dat_i[15:8];
      else
        l_mux[15:8] <= #1 l_read[15:8];
    end
  else
    l_mux[15:0]  <= #1 16'hz;
end
 
//
// Mux and latch data for writing right SRAM bank (bytes 2 and 3)
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    r_mux <= 16'h0;
  else
  if (~r0_wen)
    begin
      if (wb_sel_i[2])
        r_mux[7:0]  <= #1 wb_dat_i[23:16];
      else
        r_mux[7:0]  <= #1 r_read[7:0];
      if (wb_sel_i[3])
        r_mux[15:8]  <= #1 wb_dat_i[31:24];
      else
        r_mux[15:8]  <= #1 r_read[15:8];
    end
  else
    r_mux <= #1 16'hz;
end
 
//
// Left WE
//
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    l0_wen <= 1'b1;
  else
  if (wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[1:0]) & ~wb_ack_o)
    l0_wen <= #1 1'b0;
  else
    l0_wen <= #1 1'b1;
end
 
//
// Right WE
//
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    r0_wen <= 1'b1;
  else
  if (wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:2]) & ~wb_ack_o)
    r0_wen <= #1 1'b0;
  else
    r0_wen <= #1 1'b1;
end
 
//
// Write acknowledge
//
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    ack_we <= 1'b0;
  else
  if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)
    ack_we <= #1 1'b1;
  else
    ack_we <= #1 1'b0;
end
 
//
// Generate d_oe signal (tristate control)
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    d_oe <= 1'b0;
  else
  if (~l0_wen | ~r0_wen)
    d_oe <= 1'b1;
  else
    d_oe <= 1'b0;
end
 
//
// SRAM i/f monitor
//
// synopsys translate_off
integer fsram;
initial fsram = $fopen("sram.log");
always @(posedge wb_clk_i)
begin
  if (~l0_wen | ~r0_wen)
    $fdisplay(fsram, "%t [%h] <- write %h", $time, wb_adr_i, {r_d_o, l_d_o});
  else
  if ((l_oe | r_oe) & ~wb_we_i)
    $fdisplay(fsram, "%t [%h] -> read %h", $time, wb_adr_i, {r_d_i, l_d_i});
end
// synopsys translate_on
 
endmodule
 
`endif

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[/] [or1k_old/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [mem_if/] [sram_top.v] - Blame information for rev 959

Line No.	Rev	Author	Line
1	746	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// XESS SRAM interface ////`
4			`//// ////`
5			`//// This file is part of the OR1K test application ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Connects the SoC to SRAM. It does RMW for byte accesses ////`
10			`//// because XSV board has WEs on a 16-bit basis. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// - nothing really ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Simon Srot, simons@opencores.org ////`
17			`//// - Igor Mohor, igorm@opencores.org ////`
18			`//// ////`
19			`//////////////////////////////////////////////////////////////////////`
20			`//// ////`
21			`//// Copyright (C) 2001 Authors ////`
22			`//// ////`
23			`//// This source file may be used and distributed without ////`
24			`//// restriction provided that this copyright statement is not ////`
25			`//// removed from the file and that any derivative work contains ////`
26			`//// the original copyright notice and the associated disclaimer. ////`
27			`//// ////`
28			`//// This source file is free software; you can redistribute it ////`
29			`//// and/or modify it under the terms of the GNU Lesser General ////`
30			`//// Public License as published by the Free Software Foundation; ////`
31			`//// either version 2.1 of the License, or (at your option) any ////`
32			`//// later version. ////`
33			`//// ////`
34			`//// This source is distributed in the hope that it will be ////`
35			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
36			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
37			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
38			`//// details. ////`
39			`//// ////`
40			`//// You should have received a copy of the GNU Lesser General ////`
41			`//// Public License along with this source; if not, download it ////`
42			`//// from http://www.opencores.org/lgpl.shtml ////`
43			`//// ////`
44			`//////////////////////////////////////////////////////////////////////`
45			`//`
46			`// CVS Revision History`
47			`//`
48			`// $Log: not supported by cvs2svn $`
49	959	lampret	`// Revision 1.2 2002/08/12 05:34:06 lampret`
50			`// Added SRAM_GENERIC`
51			`//`
52	946	lampret	`// Revision 1.1.1.1 2002/03/21 16:55:44 lampret`
53			`// First import of the "new" XESS XSV environment.`
54			`//`
55			`//`
56	746	lampret	`// Revision 1.3 2002/01/23 07:50:44 lampret`
57			`// Added wb_err_o to flash and sram i/f for testing the buserr exception.`
58			`//`
59			`// Revision 1.2 2002/01/14 06:18:22 lampret`
60			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
61			`//`
62			`// Revision 1.1.1.1 2001/11/04 19:00:09 lampret`
63			`// First import.`
64			`//`
65			`//`
66
67			`// synopsys translate_off`
68			`include "timescale.v"
69			`// synopsys translate_on`
70
71	946	lampret	`define SRAM_GENERIC
72
73			`ifdef SRAM_GENERIC
74
75	746	lampret	`module sram_top (`
76			`wb_clk_i, wb_rst_i,`
77
78			`wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,`
79			`wb_stb_i, wb_ack_o, wb_err_o,`
80
81			`r_cen, r0_wen, r1_wen, r_oen, r_a, r_d_i, r_d_o, d_oe,`
82			`l_cen, l0_wen, l1_wen, l_oen, l_a, l_d_i, l_d_o`
83			`);`
84
85			`//`
86			`// Paraneters`
87			`//`
88			`parameter aw = 19;`
89
90			`//`
91			`// I/O Ports`
92			`//`
93			`input wb_clk_i;`
94			`input wb_rst_i;`
95
96			`//`
97			`// WB slave i/f`
98			`//`
99			`input [31:0] wb_dat_i;`
100			`output [31:0] wb_dat_o;`
101			`input [31:0] wb_adr_i;`
102			`input [3:0] wb_sel_i;`
103			`input wb_we_i;`
104			`input wb_cyc_i;`
105			`input wb_stb_i;`
106			`output wb_ack_o;`
107			`output wb_err_o;`
108
109			`//`
110			`// Right SRAM bank`
111			`//`
112			`output r_oen;`
113			`output r0_wen;`
114			`output r1_wen;`
115			`output r_cen;`
116			`input [15:0] r_d_i;`
117			`output [15:0] r_d_o;`
118			`output [aw-1:0] r_a;`
119
120			`//`
121			`// Left SRAM bank`
122			`//`
123			`output l_oen;`
124			`output l0_wen;`
125			`output l1_wen;`
126			`output l_cen;`
127			`input [15:0] l_d_i;`
128			`output [15:0] l_d_o;`
129			`output [aw-1:0] l_a;`
130
131			`//`
132			`// Common SRAM signals`
133			`//`
134			`output d_oe;`
135
136			`//`
137	946	lampret	`// Internal wires and regs`
138			`//`
139	959	lampret	`reg [7:0] mem [2097151:0];`
140	946	lampret	`wire [31:0] adr;`
141			`ifdef SRAM_GENERIC_REGISTERED
142			`reg wb_ack_o;`
143			`reg wb_err_o;`
144			`reg [31:0] wb_dat_o;`
145			`endif
146			`wire wb_err;`
147
148			`//`
149			`// Aliases and simple assignments`
150			`//`
151			`assign wb_err = wb_cyc_i & wb_stb_i & (\|wb_adr_i[23:21]); // If Access to > 2MB (8-bit leading prefix ignored)`
152			`assign adr = {8'h00, wb_adr_i[23:2], 2'b00};`
153
154			`ifdef SRAM_GENERIC_REGISTERED
155			`//`
156			`// Reading from SRAM model`
157			`//`
158			`always @(posedge wb_rst_i or posedge wb_clk_i)`
159			`if (wb_rst_i)`
160			`wb_dat_o <= #1 32'h0000_0000;`
161			`else begin`
162			`wb_dat_o[7:0] <= #1 mem[adr+3];`
163			`wb_dat_o[15:8] <= #1 mem[adr+2];`
164			`wb_dat_o[23:16] <= #1 mem[adr+1];`
165			`wb_dat_o[31:24] <= #1 mem[adr+0];`
166			`end`
167			`else
168			`assign wb_dat_o[7:0] = mem[adr+3];`
169			`assign wb_dat_o[15:8] = mem[adr+2];`
170			`assign wb_dat_o[23:16] = mem[adr+1];`
171			`assign wb_dat_o[31:24] = mem[adr+0];`
172			`endif
173
174			`//`
175			`// Writing to SRAM model`
176			`//`
177			`always @(posedge wb_rst_i or posedge wb_clk_i)`
178			`if (wb_cyc_i & wb_stb_i & wb_we_i) begin`
179			`if (wb_sel_i[0])`
180			`mem[adr+3] <= #1 wb_dat_i[7:0];`
181			`if (wb_sel_i[1])`
182			`mem[adr+2] <= #1 wb_dat_i[15:8];`
183			`if (wb_sel_i[2])`
184			`mem[adr+1] <= #1 wb_dat_i[23:16];`
185			`if (wb_sel_i[3])`
186			`mem[adr+0] <= #1 wb_dat_i[31:24];`
187			`end`
188
189			`ifdef SRAM_GENERIC_REGISTERED
190			`//`
191			`// WB Acknowledge`
192			`//`
193			`always @(posedge wb_clk_i or posedge wb_rst_i)`
194			`if (wb_rst_i)`
195			`wb_ack_o <= #1 1'b0;`
196			`else`
197			`wb_ack_o <= #1 wb_cyc_i & wb_stb_i & !wb_ack_o;`
198			`else
199			`assign wb_ack_o = wb_cyc_i & wb_stb_i;`
200			`endif
201
202			`ifdef SRAM_GENERIC_REGISTERED
203			`//`
204			`// WB Error`
205			`//`
206			`always @(posedge wb_clk_i or posedge wb_rst_i)`
207			`if (wb_rst_i)`
208			`wb_err_o <= #1 1'b0;`
209			`else`
210			`wb_err_o <= #1 wb_err & !wb_err_o;`
211			`else
212			`assign wb_err_o = wb_err;`
213			`endif
214
215			`//`
216			`// Flash i/f monitor`
217			`//`
218			`// synopsys translate_off`
219			`integer fsram;`
220			`initial fsram = $fopen("sram.log");`
221			`always @(posedge wb_clk_i)`
222			`if (wb_cyc_i)`
223			`if (wb_stb_i & wb_we_i) begin`
224			`if (wb_sel_i[3])`
225			`mem[{wb_adr_i[23:2], 2'b00}+0] = wb_dat_i[31:24];`
226			`if (wb_sel_i[2])`
227			`mem[{wb_adr_i[23:2], 2'b00}+1] = wb_dat_i[23:16];`
228			`if (wb_sel_i[1])`
229			`mem[{wb_adr_i[23:2], 2'b00}+2] = wb_dat_i[15:8];`
230			`if (wb_sel_i[0])`
231			`mem[{wb_adr_i[23:2], 2'b00}+3] = wb_dat_i[7:0];`
232			`$fdisplay(fsram, "%t [%h] <- write %h, byte sel %b", $time, wb_adr_i, wb_dat_i, wb_sel_i);`
233			`end else if (wb_ack_o)`
234			`$fdisplay(fsram, "%t [%h] -> read %h", $time, wb_adr_i, wb_dat_o);`
235			`// synopsys translate_on`
236
237			`endmodule`
238
239			`else
240
241			`module sram_top (`
242			`wb_clk_i, wb_rst_i,`
243
244			`wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,`
245			`wb_stb_i, wb_ack_o, wb_err_o,`
246
247			`r_cen, r0_wen, r1_wen, r_oen, r_a, r_d_i, r_d_o, d_oe,`
248			`l_cen, l0_wen, l1_wen, l_oen, l_a, l_d_i, l_d_o`
249			`);`
250
251			`//`
252			`// Paraneters`
253			`//`
254			`parameter aw = 19;`
255
256			`//`
257			`// I/O Ports`
258			`//`
259			`input wb_clk_i;`
260			`input wb_rst_i;`
261
262			`//`
263			`// WB slave i/f`
264			`//`
265			`input [31:0] wb_dat_i;`
266			`output [31:0] wb_dat_o;`
267			`input [31:0] wb_adr_i;`
268			`input [3:0] wb_sel_i;`
269			`input wb_we_i;`
270			`input wb_cyc_i;`
271			`input wb_stb_i;`
272			`output wb_ack_o;`
273			`output wb_err_o;`
274
275			`//`
276			`// Right SRAM bank`
277			`//`
278			`output r_oen;`
279			`output r0_wen;`
280			`output r1_wen;`
281			`output r_cen;`
282			`input [15:0] r_d_i;`
283			`output [15:0] r_d_o;`
284			`output [aw-1:0] r_a;`
285
286			`//`
287			`// Left SRAM bank`
288			`//`
289			`output l_oen;`
290			`output l0_wen;`
291			`output l1_wen;`
292			`output l_cen;`
293			`input [15:0] l_d_i;`
294			`output [15:0] l_d_o;`
295			`output [aw-1:0] l_a;`
296
297			`//`
298			`// Common SRAM signals`
299			`//`
300			`output d_oe;`
301
302			`//`
303	746	lampret	`// Internal regs and wires`
304			`//`
305			`reg [15:0] r_data;`
306			`reg [15:0] l_data;`
307			`reg l0_wen;`
308			`wire l1_wen = l0_wen;`
309			`reg r0_wen;`
310			`wire r1_wen = r0_wen;`
311			`reg [31:0] latch_data;`
312			`reg ack_we;`
313			`wire l_oe;`
314			`wire r_oe;`
315			`wire r_ack;`
316			`reg Mux;`
317			`reg [aw-1:0] LatchedAddr;`
318			`reg [15:0] l_read;`
319			`reg [15:0] r_read;`
320			`reg d_oe;`
321			`reg [15:0] l_mux;`
322			`reg [15:0] r_mux;`
323
324			`//`
325			`// Aliases and simple assignments`
326			`//`
327			`assign wb_dat_o = {r_d_i, l_d_i};`
328			`assign l_oen = ~l_oe;`
329			`assign r_oen = ~r_oe;`
330			`assign l_a = Mux ? LatchedAddr : wb_adr_i[aw+1:2];`
331			`assign r_a = l_a;`
332			`assign l_d_o = l_mux;`
333			`assign r_d_o = r_mux;`
334			`assign l_oe = wb_cyc_i & wb_stb_i & l0_wen;`
335			`assign r_oe = wb_cyc_i & wb_stb_i & r0_wen;`
336			`assign l_cen = ~(wb_cyc_i & wb_stb_i);`
337			`assign r_cen = l_cen;`
338			`assign wb_ack_o = (wb_cyc_i & wb_stb_i & ~wb_we_i) \| ack_we;`
339			`assign wb_err_o = wb_cyc_i & wb_stb_i & (\|wb_adr_i[27:21]); // If Access to > 2MB (4-bit leading prefix ignored)`
340
341			`//`
342			`// RMW mux control`
343			`//`
344			`always @ (negedge wb_clk_i or posedge wb_rst_i)`
345			`begin`
346			`if (wb_rst_i)`
347			`Mux <= 1'b0;`
348			`else`
349			`if (ack_we)`
350			`Mux <= #1 1'b1;`
351			`else`
352			`Mux <= #1 1'b0;`
353			`end`
354
355			`//`
356			`// Latch address`
357			`//`
358			`always @ (negedge wb_clk_i or posedge wb_rst_i)`
359			`begin`
360			`if (wb_rst_i)`
361			`LatchedAddr <= 'h0;`
362			`else`
363			`if (wb_cyc_i & wb_stb_i)`
364			`LatchedAddr <= #1 wb_adr_i[aw+1:2];`
365			`end`
366
367			`//`
368			`// Latch data from RAM (read data)`
369			`//`
370			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
371			`begin`
372			`if (wb_rst_i)`
373			`begin`
374			`l_read <= 16'h0;`
375			`r_read <= 16'h0;`
376			`end`
377			`else`
378			`if (wb_cyc_i & wb_stb_i)`
379			`begin`
380			`l_read <= #1 l_d_i[15:0];`
381			`r_read <= #1 r_d_i[15:0];`
382			`end`
383			`end`
384
385			`//`
386			`// Mux and latch data for writing left SRAM bank (bytes 0 and 1)`
387			`//`
388			`always @ (negedge wb_clk_i or posedge wb_rst_i)`
389			`begin`
390			`if (wb_rst_i)`
391			`l_mux <= 16'h0;`
392			`else`
393			`if (~l0_wen)`
394			`begin`
395			`if (wb_sel_i[0])`
396			`l_mux[7:0] <= #1 wb_dat_i[7:0];`
397			`else`
398			`l_mux[7:0] <= #1 l_read[7:0];`
399			`if (wb_sel_i[1])`
400			`l_mux[15:8] <= #1 wb_dat_i[15:8];`
401			`else`
402			`l_mux[15:8] <= #1 l_read[15:8];`
403			`end`
404			`else`
405			`l_mux[15:0] <= #1 16'hz;`
406			`end`
407
408			`//`
409			`// Mux and latch data for writing right SRAM bank (bytes 2 and 3)`
410			`//`
411			`always @ (negedge wb_clk_i or posedge wb_rst_i)`
412			`begin`
413			`if (wb_rst_i)`
414			`r_mux <= 16'h0;`
415			`else`
416			`if (~r0_wen)`
417			`begin`
418			`if (wb_sel_i[2])`
419			`r_mux[7:0] <= #1 wb_dat_i[23:16];`
420			`else`
421			`r_mux[7:0] <= #1 r_read[7:0];`
422			`if (wb_sel_i[3])`
423			`r_mux[15:8] <= #1 wb_dat_i[31:24];`
424			`else`
425			`r_mux[15:8] <= #1 r_read[15:8];`
426			`end`
427			`else`
428			`r_mux <= #1 16'hz;`
429			`end`
430
431			`//`
432			`// Left WE`
433			`//`
434			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
435			`begin`
436			`if (wb_rst_i)`
437			`l0_wen <= 1'b1;`
438			`else`
439			`if (wb_cyc_i & wb_stb_i & wb_we_i & (\|wb_sel_i[1:0]) & ~wb_ack_o)`
440			`l0_wen <= #1 1'b0;`
441			`else`
442			`l0_wen <= #1 1'b1;`
443			`end`
444
445			`//`
446			`// Right WE`
447			`//`
448			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
449			`begin`
450			`if (wb_rst_i)`
451			`r0_wen <= 1'b1;`
452			`else`
453			`if (wb_cyc_i & wb_stb_i & wb_we_i & (\|wb_sel_i[3:2]) & ~wb_ack_o)`
454			`r0_wen <= #1 1'b0;`
455			`else`
456			`r0_wen <= #1 1'b1;`
457			`end`
458
459			`//`
460			`// Write acknowledge`
461			`//`
462			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
463			`begin`
464			`if (wb_rst_i)`
465			`ack_we <= 1'b0;`
466			`else`
467			`if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)`
468			`ack_we <= #1 1'b1;`
469			`else`
470			`ack_we <= #1 1'b0;`
471			`end`
472
473			`//`
474			`// Generate d_oe signal (tristate control)`
475			`//`
476			`always @ (negedge wb_clk_i or posedge wb_rst_i)`
477			`begin`
478			`if (wb_rst_i)`
479			`d_oe <= 1'b0;`
480			`else`
481			`if (~l0_wen \| ~r0_wen)`
482			`d_oe <= 1'b1;`
483			`else`
484			`d_oe <= 1'b0;`
485			`end`
486
487			`//`
488			`// SRAM i/f monitor`
489			`//`
490			`// synopsys translate_off`
491			`integer fsram;`
492			`initial fsram = $fopen("sram.log");`
493			`always @(posedge wb_clk_i)`
494			`begin`
495			`if (~l0_wen \| ~r0_wen)`
496			`$fdisplay(fsram, "%t [%h] <- write %h", $time, wb_adr_i, {r_d_o, l_d_o});`
497			`else`
498			`if ((l_oe \| r_oe) & ~wb_we_i)`
499			`$fdisplay(fsram, "%t [%h] -> read %h", $time, wb_adr_i, {r_d_i, l_d_i});`
500			`end`
501			`// synopsys translate_on`
502
503			`endmodule`
504	946	lampret
505			`endif