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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Double-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common double-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  double-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Double-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage 2-port Sync RAM                                    ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16_S16                               ////
////                                                              ////
////  To Do:                                                      ////
////   - fix Avant!                                               ////
////   - xilinx rams need external tri-state logic                ////
////   - add additional RAMs (Altera, VS etc)                     ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5  2002/02/01 19:56:54  lampret
// Fixed combinational loops.
//
// Revision 1.4  2002/01/23 07:52:36  lampret
// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.
//
// Revision 1.3  2002/01/19 14:10:22  lampret
// Fixed OR1200_XILINX_RAM32X1D.
//
// Revision 1.2  2002/01/15 06:12:22  lampret
// Fixed module name when compiling with OR1200_XILINX_RAM32X1D
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10  2001/11/05 14:48:00  lampret
// Added missing endif
//
// Revision 1.9  2001/11/02 18:57:14  lampret
// Modified virtual silicon instantiations.
//
// Revision 1.8  2001/10/22 19:39:56  lampret
// Fixed parameters in generic sprams.
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_dpram_32x32(
        // Generic synchronous double-port RAM interface
        clk_a, rst_a, ce_a, oe_a, addr_a, do_a,
        clk_b, rst_b, ce_b, we_b, addr_b, di_b
);
 
//
// Default address and data buses width
//
parameter aw = 5;
parameter dw = 32;
 
//
// Generic synchronous double-port RAM interface
//
input                   clk_a;  // Clock
input                   rst_a;  // Reset
input                   ce_a;   // Chip enable input
input                   oe_a;   // Output enable input
input   [aw-1:0] addr_a; // address bus inputs
output  [dw-1:0] do_a;   // output data bus
input                   clk_b;  // Clock
input                   rst_b;  // Reset
input                   ce_b;   // Chip enable input
input                   we_b;   // Write enable input
input   [aw-1:0] addr_b; // address bus inputs
input   [dw-1:0] di_b;   // input data bus
 
//
// Internal wires and registers
//
 
`ifdef OR1200_ARTISAN_SDP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Double-Port RAM (ra2sh)
//
`ifdef UNUSED
art_hsdp_32x32 #(dw, 1<<aw, aw) artisan_sdp(
`else
art_hsdp_32x32 artisan_sdp(
`endif
        .qa(do_a),
        .clka(clk_a),
        .cena(~ce_a),
        .wena(1'b1),
        .aa(addr_a),
        .da(32'h00000000),
        .oena(~oe_a),
        .qb(),
        .clkb(clk_b),
        .cenb(~ce_b),
        .wenb(~we_b),
        .ab(addr_b),
        .db(di_b),
        .oenb(1'b1)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .do(do)
);
 
`else
 
`ifdef OR1200_VIRAGE_STP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 2-port R/W RAM
//
virage_stp virage_stp(
        .QA(do_a),
        .QB(),
 
        .ADRA(addr_a),
        .DA(32'h00000000),
        .WEA(1'b0),
        .OEA(oe_a),
        .MEA(ce_a),
        .CLKA(clk_a),
 
        .ADRB(addr_b),
        .DB(di_b),
        .WEB(we_b),
        .OEB(1'b1),
        .MEB(ce_b),
        .CLKB(clk_b)
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_STP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Two-port R/W SRAM
//
`ifdef UNUSED
vs_hdtp_64x32 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
vs_hdtp_64x32 vs_ssp(
`endif
        .P1CK(clk_a),
        .P1CEN(~ce_a),
        .P1WEN(1'b1),
        .P1OEN(~oe_a),
        .P1ADR({1'b0, addr_a}),
        .P1DI(32'h0000_0000),
        .P1DOUT(do_a),
 
        .P2CK(clk_b),
        .P2CEN(~ce_b),
        .P2WEN(~ce_b),
        .P2OEN(1'b1),
        .P2ADR({1'b0, addr_b}),
        .P2DI(di_b),
        .P2DOUT()
);
 
`else
 
`ifdef OR1200_XILINX_RAM32X1D
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
reg     [4:0]    addr_a_r;
 
always @(posedge clk_a or posedge rst_a)
        if (rst_a)
                addr_a_r <= #1 5'b00000;
        else if (ce_a)
                addr_a_r <= #1 addr_a;
 
//
// Block 0
//
or1200_xcv_ram32x8d xcv_ram32x8d_0 (
        .DPO(do_a[7:0]),
        .SPO(),
        .A(addr_b),
        .D(di_b[7:0]),
        .DPRA(addr_a_r),
        .WCLK(clk_b),
        .WE(we_b)
);
 
//
// Block 1
//
or1200_xcv_ram32x8d xcv_ram32x8d_1 (
        .DPO(do_a[15:8]),
        .SPO(),
        .A(addr_b),
        .D(di_b[15:8]),
        .DPRA(addr_a_r),
        .WCLK(clk_b),
        .WE(we_b)
);
 
 
//
// Block 2
//
or1200_xcv_ram32x8d xcv_ram32x8d_2 (
        .DPO(do_a[23:16]),
        .SPO(),
        .A(addr_b),
        .D(di_b[23:16]),
        .DPRA(addr_a_r),
        .WCLK(clk_b),
        .WE(we_b)
);
 
//
// Block 3
//
or1200_xcv_ram32x8d xcv_ram32x8d_3 (
        .DPO(do_a[31:24]),
        .SPO(),
        .A(addr_b),
        .D(di_b[31:24]),
        .DPRA(addr_a_r),
        .WCLK(clk_b),
        .WE(we_b)
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S16_S16 ramb4_s16_0(
        .CLKA(clk_a),
        .RSTA(rst_a),
        .ADDRA({3'b000, addr_a}),
        .DIA(16'h0000),
        .ENA(ce_a),
        .WEA(1'b0),
        .DOA(do_a[15:0]),
 
        .CLKB(clk_b),
        .RSTB(rst_b),
        .ADDRB({3'b000, addr_b}),
        .DIB(di_b[15:0]),
        .ENB(ce_b),
        .WEB(we_b),
        .DOB()
);
 
//
// Block 1
//
RAMB4_S16_S16 ramb4_s16_1(
        .CLKA(clk_a),
        .RSTA(rst_a),
        .ADDRA({3'b000, addr_a}),
        .DIA(16'h0000),
        .ENA(ce_a),
        .WEA(1'b0),
        .DOA(do_a[31:16]),
 
        .CLKB(clk_b),
        .RSTB(rst_b),
        .ADDRB({3'b000, addr_b}),
        .DIB(di_b[31:16]),
        .ENB(ce_b),
        .WEB(we_b),
        .DOB()
);
 
`else
 
//
// Generic double-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [dw-1:0] do_reg;                 // RAM data output register
 
//
// Data output drivers
//
assign do_a = (oe_a) ? do_reg : {dw{1'bz}};
 
//
// RAM read
//
always @(posedge clk_a)
        if (ce_a)
                do_reg <= #1 mem[addr_a];
 
//
// RAM write
//
always @(posedge clk_b)
        if (ce_b && we_b)
                mem[addr_b] <= #1 di_b;
 
`endif  // !OR1200_XILINX_RAMB4_S16_S16
`endif  // !OR1200_XILINX_RAM32X1D
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_STP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SDP
 
endmodule

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[/] [or1k_old/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [or1200.old/] [or1200_dpram_32x32.v] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	746	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Double-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common double-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// double-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Double-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage 2-port Sync RAM ////`
22			`//// ////`
23			`//// Supported FPGA RAMs are: ////`
24			`//// - Xilinx Virtex RAMB4_S16_S16 ////`
25			`//// ////`
26			`//// To Do: ////`
27			`//// - fix Avant! ////`
28			`//// - xilinx rams need external tri-state logic ////`
29			`//// - add additional RAMs (Altera, VS etc) ////`
30			`//// ////`
31			`//// Author(s): ////`
32			`//// - Damjan Lampret, lampret@opencores.org ////`
33			`//// ////`
34			`//////////////////////////////////////////////////////////////////////`
35			`//// ////`
36			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
37			`//// ////`
38			`//// This source file may be used and distributed without ////`
39			`//// restriction provided that this copyright statement is not ////`
40			`//// removed from the file and that any derivative work contains ////`
41			`//// the original copyright notice and the associated disclaimer. ////`
42			`//// ////`
43			`//// This source file is free software; you can redistribute it ////`
44			`//// and/or modify it under the terms of the GNU Lesser General ////`
45			`//// Public License as published by the Free Software Foundation; ////`
46			`//// either version 2.1 of the License, or (at your option) any ////`
47			`//// later version. ////`
48			`//// ////`
49			`//// This source is distributed in the hope that it will be ////`
50			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
51			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
52			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
53			`//// details. ////`
54			`//// ////`
55			`//// You should have received a copy of the GNU Lesser General ////`
56			`//// Public License along with this source; if not, download it ////`
57			`//// from http://www.opencores.org/lgpl.shtml ////`
58			`//// ////`
59			`//////////////////////////////////////////////////////////////////////`
60			`//`
61			`// CVS Revision History`
62			`//`
63			`// $Log: not supported by cvs2svn $`
64			`// Revision 1.5 2002/02/01 19:56:54 lampret`
65			`// Fixed combinational loops.`
66			`//`
67			`// Revision 1.4 2002/01/23 07:52:36 lampret`
68			`// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.`
69			`//`
70			`// Revision 1.3 2002/01/19 14:10:22 lampret`
71			`// Fixed OR1200_XILINX_RAM32X1D.`
72			`//`
73			`// Revision 1.2 2002/01/15 06:12:22 lampret`
74			`// Fixed module name when compiling with OR1200_XILINX_RAM32X1D`
75			`//`
76			`// Revision 1.1 2002/01/03 08:16:15 lampret`
77			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
78			`//`
79			`// Revision 1.10 2001/11/05 14:48:00 lampret`
80			`// Added missing endif`
81			`//`
82			`// Revision 1.9 2001/11/02 18:57:14 lampret`
83			`// Modified virtual silicon instantiations.`
84			`//`
85			`// Revision 1.8 2001/10/22 19:39:56 lampret`
86			`// Fixed parameters in generic sprams.`
87			`//`
88			`// Revision 1.7 2001/10/21 17:57:16 lampret`
89			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
90			`//`
91			`// Revision 1.6 2001/10/14 13:12:09 lampret`
92			`// MP3 version.`
93			`//`
94			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
95			`// no message`
96			`//`
97			`// Revision 1.1 2001/08/09 13:39:33 lampret`
98			`// Major clean-up.`
99			`//`
100			`// Revision 1.2 2001/07/30 05:38:02 lampret`
101			`// Adding empty directories required by HDL coding guidelines`
102			`//`
103			`//`
104
105			`// synopsys translate_off`
106			`include "timescale.v"
107			`// synopsys translate_on`
108			`include "or1200_defines.v"
109
110			`module or1200_dpram_32x32(`
111			`// Generic synchronous double-port RAM interface`
112			`clk_a, rst_a, ce_a, oe_a, addr_a, do_a,`
113			`clk_b, rst_b, ce_b, we_b, addr_b, di_b`
114			`);`
115
116			`//`
117			`// Default address and data buses width`
118			`//`
119			`parameter aw = 5;`
120			`parameter dw = 32;`
121
122			`//`
123			`// Generic synchronous double-port RAM interface`
124			`//`
125			`input clk_a; // Clock`
126			`input rst_a; // Reset`
127			`input ce_a; // Chip enable input`
128			`input oe_a; // Output enable input`
129			`input [aw-1:0] addr_a; // address bus inputs`
130			`output [dw-1:0] do_a; // output data bus`
131			`input clk_b; // Clock`
132			`input rst_b; // Reset`
133			`input ce_b; // Chip enable input`
134			`input we_b; // Write enable input`
135			`input [aw-1:0] addr_b; // address bus inputs`
136			`input [dw-1:0] di_b; // input data bus`
137
138			`//`
139			`// Internal wires and registers`
140			`//`
141
142			`ifdef OR1200_ARTISAN_SDP
143
144			`//`
145			`// Instantiation of ASIC memory:`
146			`//`
147			`// Artisan Synchronous Double-Port RAM (ra2sh)`
148			`//`
149			`ifdef UNUSED
150			`art_hsdp_32x32 #(dw, 1<<aw, aw) artisan_sdp(`
151			`else
152			`art_hsdp_32x32 artisan_sdp(`
153			`endif
154			`.qa(do_a),`
155			`.clka(clk_a),`
156			`.cena(~ce_a),`
157			`.wena(1'b1),`
158			`.aa(addr_a),`
159			`.da(32'h00000000),`
160			`.oena(~oe_a),`
161			`.qb(),`
162			`.clkb(clk_b),`
163			`.cenb(~ce_b),`
164			`.wenb(~we_b),`
165			`.ab(addr_b),`
166			`.db(di_b),`
167			`.oenb(1'b1)`
168			`);`
169
170			`else
171
172			`ifdef OR1200_AVANT_ATP
173
174			`//`
175			`// Instantiation of ASIC memory:`
176			`//`
177			`// Avant! Asynchronous Two-Port RAM`
178			`//`
179			`avant_atp avant_atp(`
180			`.web(~we),`
181			`.reb(),`
182			`.oeb(~oe),`
183			`.rcsb(),`
184			`.wcsb(),`
185			`.ra(addr),`
186			`.wa(addr),`
187			`.di(di),`
188			`.do(do)`
189			`);`
190
191			`else
192
193			`ifdef OR1200_VIRAGE_STP
194
195			`//`
196			`// Instantiation of ASIC memory:`
197			`//`
198			`// Virage Synchronous 2-port R/W RAM`
199			`//`
200			`virage_stp virage_stp(`
201			`.QA(do_a),`
202			`.QB(),`
203
204			`.ADRA(addr_a),`
205			`.DA(32'h00000000),`
206			`.WEA(1'b0),`
207			`.OEA(oe_a),`
208			`.MEA(ce_a),`
209			`.CLKA(clk_a),`
210
211			`.ADRB(addr_b),`
212			`.DB(di_b),`
213			`.WEB(we_b),`
214			`.OEB(1'b1),`
215			`.MEB(ce_b),`
216			`.CLKB(clk_b)`
217			`);`
218
219			`else
220
221			`ifdef OR1200_VIRTUALSILICON_STP
222
223			`//`
224			`// Instantiation of ASIC memory:`
225			`//`
226			`// Virtual Silicon Two-port R/W SRAM`
227			`//`
228			`ifdef UNUSED
229			`vs_hdtp_64x32 #(1<<aw, aw-1, dw-1) vs_ssp(`
230			`else
231			`vs_hdtp_64x32 vs_ssp(`
232			`endif
233			`.P1CK(clk_a),`
234			`.P1CEN(~ce_a),`
235			`.P1WEN(1'b1),`
236			`.P1OEN(~oe_a),`
237			`.P1ADR({1'b0, addr_a}),`
238			`.P1DI(32'h0000_0000),`
239			`.P1DOUT(do_a),`
240
241			`.P2CK(clk_b),`
242			`.P2CEN(~ce_b),`
243			`.P2WEN(~ce_b),`
244			`.P2OEN(1'b1),`
245			`.P2ADR({1'b0, addr_b}),`
246			`.P2DI(di_b),`
247			`.P2DOUT()`
248			`);`
249
250			`else
251
252			`ifdef OR1200_XILINX_RAM32X1D
253
254			`//`
255			`// Instantiation of FPGA memory:`
256			`//`
257			`// Virtex/Spartan2`
258			`//`
259
260			`reg [4:0] addr_a_r;`
261
262			`always @(posedge clk_a or posedge rst_a)`
263			`if (rst_a)`
264			`addr_a_r <= #1 5'b00000;`
265			`else if (ce_a)`
266			`addr_a_r <= #1 addr_a;`
267
268			`//`
269			`// Block 0`
270			`//`
271			`or1200_xcv_ram32x8d xcv_ram32x8d_0 (`
272			`.DPO(do_a[7:0]),`
273			`.SPO(),`
274			`.A(addr_b),`
275			`.D(di_b[7:0]),`
276			`.DPRA(addr_a_r),`
277			`.WCLK(clk_b),`
278			`.WE(we_b)`
279			`);`
280
281			`//`
282			`// Block 1`
283			`//`
284			`or1200_xcv_ram32x8d xcv_ram32x8d_1 (`
285			`.DPO(do_a[15:8]),`
286			`.SPO(),`
287			`.A(addr_b),`
288			`.D(di_b[15:8]),`
289			`.DPRA(addr_a_r),`
290			`.WCLK(clk_b),`
291			`.WE(we_b)`
292			`);`
293
294
295			`//`
296			`// Block 2`
297			`//`
298			`or1200_xcv_ram32x8d xcv_ram32x8d_2 (`
299			`.DPO(do_a[23:16]),`
300			`.SPO(),`
301			`.A(addr_b),`
302			`.D(di_b[23:16]),`
303			`.DPRA(addr_a_r),`
304			`.WCLK(clk_b),`
305			`.WE(we_b)`
306			`);`
307
308			`//`
309			`// Block 3`
310			`//`
311			`or1200_xcv_ram32x8d xcv_ram32x8d_3 (`
312			`.DPO(do_a[31:24]),`
313			`.SPO(),`
314			`.A(addr_b),`
315			`.D(di_b[31:24]),`
316			`.DPRA(addr_a_r),`
317			`.WCLK(clk_b),`
318			`.WE(we_b)`
319			`);`
320
321			`else
322
323			`ifdef OR1200_XILINX_RAMB4
324
325			`//`
326			`// Instantiation of FPGA memory:`
327			`//`
328			`// Virtex/Spartan2`
329			`//`
330
331			`//`
332			`// Block 0`
333			`//`
334			`RAMB4_S16_S16 ramb4_s16_0(`
335			`.CLKA(clk_a),`
336			`.RSTA(rst_a),`
337			`.ADDRA({3'b000, addr_a}),`
338			`.DIA(16'h0000),`
339			`.ENA(ce_a),`
340			`.WEA(1'b0),`
341			`.DOA(do_a[15:0]),`
342
343			`.CLKB(clk_b),`
344			`.RSTB(rst_b),`
345			`.ADDRB({3'b000, addr_b}),`
346			`.DIB(di_b[15:0]),`
347			`.ENB(ce_b),`
348			`.WEB(we_b),`
349			`.DOB()`
350			`);`
351
352			`//`
353			`// Block 1`
354			`//`
355			`RAMB4_S16_S16 ramb4_s16_1(`
356			`.CLKA(clk_a),`
357			`.RSTA(rst_a),`
358			`.ADDRA({3'b000, addr_a}),`
359			`.DIA(16'h0000),`
360			`.ENA(ce_a),`
361			`.WEA(1'b0),`
362			`.DOA(do_a[31:16]),`
363
364			`.CLKB(clk_b),`
365			`.RSTB(rst_b),`
366			`.ADDRB({3'b000, addr_b}),`
367			`.DIB(di_b[31:16]),`
368			`.ENB(ce_b),`
369			`.WEB(we_b),`
370			`.DOB()`
371			`);`
372
373			`else
374
375			`//`
376			`// Generic double-port synchronous RAM model`
377			`//`
378
379			`//`
380			`// Generic RAM's registers and wires`
381			`//`
382			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
383			`reg [dw-1:0] do_reg; // RAM data output register`
384
385			`//`
386			`// Data output drivers`
387			`//`
388			`assign do_a = (oe_a) ? do_reg : {dw{1'bz}};`
389
390			`//`
391			`// RAM read`
392			`//`
393			`always @(posedge clk_a)`
394			`if (ce_a)`
395			`do_reg <= #1 mem[addr_a];`
396
397			`//`
398			`// RAM write`
399			`//`
400			`always @(posedge clk_b)`
401			`if (ce_b && we_b)`
402			`mem[addr_b] <= #1 di_b;`
403
404			`endif // !OR1200_XILINX_RAMB4_S16_S16
405			`endif // !OR1200_XILINX_RAM32X1D
406			`endif // !OR1200_VIRTUALSILICON_SSP
407			`endif // !OR1200_VIRAGE_STP
408			`endif // !OR1200_AVANT_ATP
409			`endif // !OR1200_ARTISAN_SDP
410
411			`endmodule`