URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] [or1k_old/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [or1200.old/] [or1200_mem2reg.v] - Blame information for rev 1782

Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's mem2reg alignment                                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Two versions of Memory to register data alignment.          ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/19 23:28:46  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_mem2reg(addr, lsu_op, memdata, regdata);
 
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
input   [1:0]                    addr;
input   [`OR1200_LSUOP_WIDTH-1:0]        lsu_op;
input   [width-1:0]              memdata;
output  [width-1:0]              regdata;
 
 
//
// Faster implementation of mem2reg
//
`ifdef OR1200_MEM2REG_FAST
 
`define OR1200_M2R_BYTE0 4'b0000
`define OR1200_M2R_BYTE1 4'b0001
`define OR1200_M2R_BYTE2 4'b0010
`define OR1200_M2R_BYTE3 4'b0011
`define OR1200_M2R_EXTB0 4'b0100
`define OR1200_M2R_EXTB1 4'b0101
`define OR1200_M2R_EXTB2 4'b0110
`define OR1200_M2R_EXTB3 4'b0111
`define OR1200_M2R_ZERO  4'b0000
 
reg     [7:0]                    regdata_hh;
reg     [7:0]                    regdata_hl;
reg     [7:0]                    regdata_lh;
reg     [7:0]                    regdata_ll;
reg     [width-1:0]              aligned;
reg     [3:0]                    sel_byte0, sel_byte1,
                                sel_byte2, sel_byte3;
 
assign regdata = {regdata_hh, regdata_hl, regdata_lh, regdata_ll};
 
//
// Byte select 0
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})       // synopsys parallel_case
                {3'b01x, 2'b00}:                        // lbz/lbs 0
                        sel_byte0 = `OR1200_M2R_BYTE3;  // take byte 3
                {3'b01x, 2'b01},                        // lbz/lbs 1
                {3'b10x, 2'b00}:                        // lhz/lhs 0
                        sel_byte0 = `OR1200_M2R_BYTE2;  // take byte 2
                {3'b01x, 2'b10}:                        // lbz/lbs 2
                        sel_byte0 = `OR1200_M2R_BYTE1;  // take byte 1
                default:                                // all other cases
                        sel_byte0 = `OR1200_M2R_BYTE0;  // take byte 0
        endcase
end
 
//
// Byte select 1
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})       // synopsys parallel_case
                {3'b010, 2'bxx}:                        // lbz
                        sel_byte1 = `OR1200_M2R_ZERO;   // zero extend
                {3'b011, 2'b00}:                        // lbs 0
                        sel_byte1 = `OR1200_M2R_EXTB3;  // sign extend from byte 3
                {3'b011, 2'b01}:                        // lbs 1
                        sel_byte1 = `OR1200_M2R_EXTB2;  // sign extend from byte 2
                {3'b011, 2'b10}:                        // lbs 2
                        sel_byte1 = `OR1200_M2R_EXTB1;  // sign extend from byte 1
                {3'b011, 2'b11}:                        // lbs 3
                        sel_byte1 = `OR1200_M2R_EXTB0;  // sign extend from byte 0
                {3'b10x, 2'b00}:                        // lhz/lhs 0
                        sel_byte1 = `OR1200_M2R_BYTE3;  // take byte 3
                default:                                // all other cases
                        sel_byte1 = `OR1200_M2R_BYTE1;  // take byte 1
        endcase
end
 
//
// Byte select 2
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})       // synopsys parallel_case
                {3'b010, 2'bxx},                        // lbz
                {3'b100, 2'bxx}:                        // lhz
                        sel_byte2 = `OR1200_M2R_ZERO;   // zero extend
                {3'b011, 2'b00},                        // lbs 0
                {3'b101, 2'b00}:                        // lhs 0
                        sel_byte2 = `OR1200_M2R_EXTB3;  // sign extend from byte 3
                {3'b011, 2'b01}:                        // lbs 1
                        sel_byte2 = `OR1200_M2R_EXTB2;  // sign extend from byte 2
                {3'b011, 2'b10},                        // lbs 2
                {3'b101, 2'b10}:                        // lhs 0
                        sel_byte2 = `OR1200_M2R_EXTB1;  // sign extend from byte 1
                {3'b011, 2'b11}:                        // lbs 3
                        sel_byte2 = `OR1200_M2R_EXTB0;  // sign extend from byte 0
                default:                                // all other cases
                        sel_byte2 = `OR1200_M2R_BYTE2;  // take byte 2
        endcase
end
 
//
// Byte select 3
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})       // synopsys parallel_case
                {3'b010, 2'bxx},                        // lbz
                {3'b100, 2'bxx}:                        // lhz
                        sel_byte3 = `OR1200_M2R_ZERO;   // zero extend
                {3'b011, 2'b00},                        // lbs 0
                {3'b101, 2'b00}:                        // lhs 0
                        sel_byte3 = `OR1200_M2R_EXTB3;  // sign extend from byte 3
                {3'b011, 2'b01}:                        // lbs 1
                        sel_byte3 = `OR1200_M2R_EXTB2;  // sign extend from byte 2
                {3'b011, 2'b10},                        // lbs 2
                {3'b101, 2'b10}:                        // lhs 0
                        sel_byte3 = `OR1200_M2R_EXTB1;  // sign extend from byte 1
                {3'b011, 2'b11}:                        // lbs 3
                        sel_byte3 = `OR1200_M2R_EXTB0;  // sign extend from byte 0
                default:                                // all other cases
                        sel_byte3 = `OR1200_M2R_BYTE3;  // take byte 3
        endcase
end
 
//
// Byte 0
//
always @(sel_byte0 or memdata) begin
        case(sel_byte0) // synopsys full_case parallel_case infer_mux
                `OR1200_M2R_BYTE0: begin
                                regdata_ll = memdata[7:0];
                        end
                `OR1200_M2R_BYTE1: begin
                                regdata_ll = memdata[15:8];
                        end
                `OR1200_M2R_BYTE2: begin
                                regdata_ll = memdata[23:16];
                        end
                `OR1200_M2R_BYTE3: begin
                                regdata_ll = memdata[31:24];
                        end
        endcase
end
 
//
// Byte 1
//
always @(sel_byte1 or memdata) begin
        case(sel_byte1) // synopsys full_case parallel_case infer_mux
                `OR1200_M2R_ZERO: begin
                                regdata_lh = 8'h00;
                        end
                `OR1200_M2R_BYTE1: begin
                                regdata_lh = memdata[15:8];
                        end
                `OR1200_M2R_BYTE3: begin
                                regdata_lh = memdata[31:24];
                        end
                `OR1200_M2R_EXTB0: begin
                                regdata_lh = {8{memdata[7]}};
                        end
                `OR1200_M2R_EXTB1: begin
                                regdata_lh = {8{memdata[15]}};
                        end
                `OR1200_M2R_EXTB2: begin
                                regdata_lh = {8{memdata[23]}};
                        end
                `OR1200_M2R_EXTB3: begin
                                regdata_lh = {8{memdata[31]}};
                        end
        endcase
end
 
//
// Byte 2
//
always @(sel_byte2 or memdata) begin
        case(sel_byte2) // synopsys full_case parallel_case infer_mux
                `OR1200_M2R_ZERO: begin
                                regdata_hl = 8'h00;
                        end
                `OR1200_M2R_BYTE2: begin
                                regdata_hl = memdata[23:16];
                        end
                `OR1200_M2R_EXTB0: begin
                                regdata_hl = {8{memdata[7]}};
                        end
                `OR1200_M2R_EXTB1: begin
                                regdata_hl = {8{memdata[15]}};
                        end
                `OR1200_M2R_EXTB2: begin
                                regdata_hl = {8{memdata[23]}};
                        end
                `OR1200_M2R_EXTB3: begin
                                regdata_hl = {8{memdata[31]}};
                        end
        endcase
end
 
//
// Byte 3
//
always @(sel_byte3 or memdata) begin
        case(sel_byte3) // synopsys full_case parallel_case infer_mux
                `OR1200_M2R_ZERO: begin
                                regdata_hh = 8'h00;
                        end
                `OR1200_M2R_BYTE3: begin
                                regdata_hh = memdata[31:24];
                        end
                `OR1200_M2R_EXTB0: begin
                                regdata_hh = {8{memdata[7]}};
                        end
                `OR1200_M2R_EXTB1: begin
                                regdata_hh = {8{memdata[15]}};
                        end
                `OR1200_M2R_EXTB2: begin
                                regdata_hh = {8{memdata[23]}};
                        end
                `OR1200_M2R_EXTB3: begin
                                regdata_hh = {8{memdata[31]}};
                        end
        endcase
end
 
`else
 
//
// Slow implementation of mem2reg
//
 
reg     [width-1:0]              regdata;
reg     [width-1:0]              aligned;
 
//
// Alignment
//
always @(addr or memdata) begin
        case(addr) // synopsys infer_mux
                2'b00:
                        aligned = memdata;
                2'b01:
                        aligned = {memdata[23:0], 8'b0};
                2'b10:
                        aligned = {memdata[15:0], 16'b0};
                2'b11:
                        aligned = {memdata[7:0], 24'b0};
        endcase
end
 
//
// Bytes
//
always @(lsu_op or aligned) begin
        case(lsu_op) // synopsys infer_mux
                `OR1200_LSUOP_LBZ: begin
                                regdata[7:0] = aligned[31:24];
                                regdata[31:8] = 24'b0;
                        end
                `OR1200_LSUOP_LBS: begin
                                regdata[7:0] = aligned[31:24];
                                regdata[31:8] = {24{aligned[31]}};
                        end
                `OR1200_LSUOP_LHZ: begin
                                regdata[15:0] = aligned[31:16];
                                regdata[31:16] = 16'b0;
                        end
                `OR1200_LSUOP_LHS: begin
                                regdata[15:0] = aligned[31:16];
                                regdata[31:16] = {16{aligned[31]}};
                        end
                default:
                                regdata = aligned;
        endcase
end
 
`endif
 
endmodule

Browse

Tools

Subversion Repositories or1k_old

[/] [or1k_old/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [or1200.old/] [or1200_mem2reg.v] - Blame information for rev 1782

Line No.	Rev	Author	Line
1	746	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's mem2reg alignment ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Two versions of Memory to register data alignment. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.2 2002/01/14 06:18:22 lampret`
48			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
49			`//`
50			`// Revision 1.1 2002/01/03 08:16:15 lampret`
51			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
52			`//`
53			`// Revision 1.9 2001/10/21 17:57:16 lampret`
54			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
55			`//`
56			`// Revision 1.8 2001/10/19 23:28:46 lampret`
57			`// Fixed some synthesis warnings. Configured with caches and MMUs.`
58			`//`
59			`// Revision 1.7 2001/10/14 13:12:09 lampret`
60			`// MP3 version.`
61			`//`
62			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
63			`// no message`
64			`//`
65			`// Revision 1.2 2001/08/09 13:39:33 lampret`
66			`// Major clean-up.`
67			`//`
68			`// Revision 1.1 2001/07/20 00:46:03 lampret`
69			`// Development version of RTL. Libraries are missing.`
70			`//`
71			`//`
72
73			`// synopsys translate_off`
74			`include "timescale.v"
75			`// synopsys translate_on`
76			`include "or1200_defines.v"
77
78			`module or1200_mem2reg(addr, lsu_op, memdata, regdata);`
79
80			parameter width = `OR1200_OPERAND_WIDTH;
81
82			`//`
83			`// I/O`
84			`//`
85			`input [1:0] addr;`
86			input [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
87			`input [width-1:0] memdata;`
88			`output [width-1:0] regdata;`
89
90
91			`//`
92			`// Faster implementation of mem2reg`
93			`//`
94			`ifdef OR1200_MEM2REG_FAST
95
96			`define OR1200_M2R_BYTE0 4'b0000
97			`define OR1200_M2R_BYTE1 4'b0001
98			`define OR1200_M2R_BYTE2 4'b0010
99			`define OR1200_M2R_BYTE3 4'b0011
100			`define OR1200_M2R_EXTB0 4'b0100
101			`define OR1200_M2R_EXTB1 4'b0101
102			`define OR1200_M2R_EXTB2 4'b0110
103			`define OR1200_M2R_EXTB3 4'b0111
104			`define OR1200_M2R_ZERO 4'b0000
105
106			`reg [7:0] regdata_hh;`
107			`reg [7:0] regdata_hl;`
108			`reg [7:0] regdata_lh;`
109			`reg [7:0] regdata_ll;`
110			`reg [width-1:0] aligned;`
111			`reg [3:0] sel_byte0, sel_byte1,`
112			`sel_byte2, sel_byte3;`
113
114			`assign regdata = {regdata_hh, regdata_hl, regdata_lh, regdata_ll};`
115
116			`//`
117			`// Byte select 0`
118			`//`
119			`always @(addr or lsu_op) begin`
120			`casex({lsu_op[2:0], addr}) // synopsys parallel_case`
121			`{3'b01x, 2'b00}: // lbz/lbs 0`
122			sel_byte0 = `OR1200_M2R_BYTE3; // take byte 3
123			`{3'b01x, 2'b01}, // lbz/lbs 1`
124			`{3'b10x, 2'b00}: // lhz/lhs 0`
125			sel_byte0 = `OR1200_M2R_BYTE2; // take byte 2
126			`{3'b01x, 2'b10}: // lbz/lbs 2`
127			sel_byte0 = `OR1200_M2R_BYTE1; // take byte 1
128			`default: // all other cases`
129			sel_byte0 = `OR1200_M2R_BYTE0; // take byte 0
130			`endcase`
131			`end`
132
133			`//`
134			`// Byte select 1`
135			`//`
136			`always @(addr or lsu_op) begin`
137			`casex({lsu_op[2:0], addr}) // synopsys parallel_case`
138			`{3'b010, 2'bxx}: // lbz`
139			sel_byte1 = `OR1200_M2R_ZERO; // zero extend
140			`{3'b011, 2'b00}: // lbs 0`
141			sel_byte1 = `OR1200_M2R_EXTB3; // sign extend from byte 3
142			`{3'b011, 2'b01}: // lbs 1`
143			sel_byte1 = `OR1200_M2R_EXTB2; // sign extend from byte 2
144			`{3'b011, 2'b10}: // lbs 2`
145			sel_byte1 = `OR1200_M2R_EXTB1; // sign extend from byte 1
146			`{3'b011, 2'b11}: // lbs 3`
147			sel_byte1 = `OR1200_M2R_EXTB0; // sign extend from byte 0
148			`{3'b10x, 2'b00}: // lhz/lhs 0`
149			sel_byte1 = `OR1200_M2R_BYTE3; // take byte 3
150			`default: // all other cases`
151			sel_byte1 = `OR1200_M2R_BYTE1; // take byte 1
152			`endcase`
153			`end`
154
155			`//`
156			`// Byte select 2`
157			`//`
158			`always @(addr or lsu_op) begin`
159			`casex({lsu_op[2:0], addr}) // synopsys parallel_case`
160			`{3'b010, 2'bxx}, // lbz`
161			`{3'b100, 2'bxx}: // lhz`
162			sel_byte2 = `OR1200_M2R_ZERO; // zero extend
163			`{3'b011, 2'b00}, // lbs 0`
164			`{3'b101, 2'b00}: // lhs 0`
165			sel_byte2 = `OR1200_M2R_EXTB3; // sign extend from byte 3
166			`{3'b011, 2'b01}: // lbs 1`
167			sel_byte2 = `OR1200_M2R_EXTB2; // sign extend from byte 2
168			`{3'b011, 2'b10}, // lbs 2`
169			`{3'b101, 2'b10}: // lhs 0`
170			sel_byte2 = `OR1200_M2R_EXTB1; // sign extend from byte 1
171			`{3'b011, 2'b11}: // lbs 3`
172			sel_byte2 = `OR1200_M2R_EXTB0; // sign extend from byte 0
173			`default: // all other cases`
174			sel_byte2 = `OR1200_M2R_BYTE2; // take byte 2
175			`endcase`
176			`end`
177
178			`//`
179			`// Byte select 3`
180			`//`
181			`always @(addr or lsu_op) begin`
182			`casex({lsu_op[2:0], addr}) // synopsys parallel_case`
183			`{3'b010, 2'bxx}, // lbz`
184			`{3'b100, 2'bxx}: // lhz`
185			sel_byte3 = `OR1200_M2R_ZERO; // zero extend
186			`{3'b011, 2'b00}, // lbs 0`
187			`{3'b101, 2'b00}: // lhs 0`
188			sel_byte3 = `OR1200_M2R_EXTB3; // sign extend from byte 3
189			`{3'b011, 2'b01}: // lbs 1`
190			sel_byte3 = `OR1200_M2R_EXTB2; // sign extend from byte 2
191			`{3'b011, 2'b10}, // lbs 2`
192			`{3'b101, 2'b10}: // lhs 0`
193			sel_byte3 = `OR1200_M2R_EXTB1; // sign extend from byte 1
194			`{3'b011, 2'b11}: // lbs 3`
195			sel_byte3 = `OR1200_M2R_EXTB0; // sign extend from byte 0
196			`default: // all other cases`
197			sel_byte3 = `OR1200_M2R_BYTE3; // take byte 3
198			`endcase`
199			`end`
200
201			`//`
202			`// Byte 0`
203			`//`
204			`always @(sel_byte0 or memdata) begin`
205			`case(sel_byte0) // synopsys full_case parallel_case infer_mux`
206			`OR1200_M2R_BYTE0: begin
207			`regdata_ll = memdata[7:0];`
208			`end`
209			`OR1200_M2R_BYTE1: begin
210			`regdata_ll = memdata[15:8];`
211			`end`
212			`OR1200_M2R_BYTE2: begin
213			`regdata_ll = memdata[23:16];`
214			`end`
215			`OR1200_M2R_BYTE3: begin
216			`regdata_ll = memdata[31:24];`
217			`end`
218			`endcase`
219			`end`
220
221			`//`
222			`// Byte 1`
223			`//`
224			`always @(sel_byte1 or memdata) begin`
225			`case(sel_byte1) // synopsys full_case parallel_case infer_mux`
226			`OR1200_M2R_ZERO: begin
227			`regdata_lh = 8'h00;`
228			`end`
229			`OR1200_M2R_BYTE1: begin
230			`regdata_lh = memdata[15:8];`
231			`end`
232			`OR1200_M2R_BYTE3: begin
233			`regdata_lh = memdata[31:24];`
234			`end`
235			`OR1200_M2R_EXTB0: begin
236			`regdata_lh = {8{memdata[7]}};`
237			`end`
238			`OR1200_M2R_EXTB1: begin
239			`regdata_lh = {8{memdata[15]}};`
240			`end`
241			`OR1200_M2R_EXTB2: begin
242			`regdata_lh = {8{memdata[23]}};`
243			`end`
244			`OR1200_M2R_EXTB3: begin
245			`regdata_lh = {8{memdata[31]}};`
246			`end`
247			`endcase`
248			`end`
249
250			`//`
251			`// Byte 2`
252			`//`
253			`always @(sel_byte2 or memdata) begin`
254			`case(sel_byte2) // synopsys full_case parallel_case infer_mux`
255			`OR1200_M2R_ZERO: begin
256			`regdata_hl = 8'h00;`
257			`end`
258			`OR1200_M2R_BYTE2: begin
259			`regdata_hl = memdata[23:16];`
260			`end`
261			`OR1200_M2R_EXTB0: begin
262			`regdata_hl = {8{memdata[7]}};`
263			`end`
264			`OR1200_M2R_EXTB1: begin
265			`regdata_hl = {8{memdata[15]}};`
266			`end`
267			`OR1200_M2R_EXTB2: begin
268			`regdata_hl = {8{memdata[23]}};`
269			`end`
270			`OR1200_M2R_EXTB3: begin
271			`regdata_hl = {8{memdata[31]}};`
272			`end`
273			`endcase`
274			`end`
275
276			`//`
277			`// Byte 3`
278			`//`
279			`always @(sel_byte3 or memdata) begin`
280			`case(sel_byte3) // synopsys full_case parallel_case infer_mux`
281			`OR1200_M2R_ZERO: begin
282			`regdata_hh = 8'h00;`
283			`end`
284			`OR1200_M2R_BYTE3: begin
285			`regdata_hh = memdata[31:24];`
286			`end`
287			`OR1200_M2R_EXTB0: begin
288			`regdata_hh = {8{memdata[7]}};`
289			`end`
290			`OR1200_M2R_EXTB1: begin
291			`regdata_hh = {8{memdata[15]}};`
292			`end`
293			`OR1200_M2R_EXTB2: begin
294			`regdata_hh = {8{memdata[23]}};`
295			`end`
296			`OR1200_M2R_EXTB3: begin
297			`regdata_hh = {8{memdata[31]}};`
298			`end`
299			`endcase`
300			`end`
301
302			`else
303
304			`//`
305			`// Slow implementation of mem2reg`
306			`//`
307
308			`reg [width-1:0] regdata;`
309			`reg [width-1:0] aligned;`
310
311			`//`
312			`// Alignment`
313			`//`
314			`always @(addr or memdata) begin`
315			`case(addr) // synopsys infer_mux`
316			`2'b00:`
317			`aligned = memdata;`
318			`2'b01:`
319			`aligned = {memdata[23:0], 8'b0};`
320			`2'b10:`
321			`aligned = {memdata[15:0], 16'b0};`
322			`2'b11:`
323			`aligned = {memdata[7:0], 24'b0};`
324			`endcase`
325			`end`
326
327			`//`
328			`// Bytes`
329			`//`
330			`always @(lsu_op or aligned) begin`
331			`case(lsu_op) // synopsys infer_mux`
332			`OR1200_LSUOP_LBZ: begin
333			`regdata[7:0] = aligned[31:24];`
334			`regdata[31:8] = 24'b0;`
335			`end`
336			`OR1200_LSUOP_LBS: begin
337			`regdata[7:0] = aligned[31:24];`
338			`regdata[31:8] = {24{aligned[31]}};`
339			`end`
340			`OR1200_LSUOP_LHZ: begin
341			`regdata[15:0] = aligned[31:16];`
342			`regdata[31:16] = 16'b0;`
343			`end`
344			`OR1200_LSUOP_LHS: begin
345			`regdata[15:0] = aligned[31:16];`
346			`regdata[31:16] = {16{aligned[31]}};`
347			`end`
348			`default:`
349			`regdata = aligned;`
350			`endcase`
351			`end`
352
353			`endif
354
355			`endmodule`