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[/] [or1k_old/] [trunk/] [orp/] [orp_soc/] [sw/] [except/] [except_test_s.S] - Blame information for rev 969

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/* Support file for c based tests */
 
#include "spr_defs.h"
#include "board.h"
#include "mc.h"
 
        .global _except_basic
        .global _lo_dmmu_en
        .global _lo_immu_en
        .global _call
        .global _call_with_int
        .global _load_acc_32
        .global _load_acc_16
        .global _store_acc_32
        .global _store_acc_16
        .global _load_b_acc_32
        .global _trap
        .global _b_trap
        .global _range
        .global _b_range
        .global _int_trigger
        .global _int_loop
        .global _jump_back
 
        .section .vectors
        .extern _reset_support
        .extern _c_reset
        .extern _excpt_buserr
        .extern _excpt_dpfault
        .extern _excpt_ipfault
        .extern _excpt_tick
        .extern _excpt_align
        .extern _excpt_illinsn
        .extern _excpt_int
        .extern _excpt_dtlbmiss
        .extern _excpt_itlbmiss
        .extern _excpt_range
        .extern _excpt_syscall
        .extern _excpt_break
        .extern _excpt_trap
 
        .org    0x200
_buserr_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_buserr)
        l.ori   r10,r10,lo(_excpt_buserr)
        l.lwz   r10,0x0(r10)
        l.jr    r10
        l.nop
 
        .org    0x300
_dpfault_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_dpfault)
        l.ori   r10,r10,lo(_excpt_dpfault)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x400
_ipfault_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_ipfault)
        l.ori   r10,r10,lo(_excpt_ipfault)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x500
_tick_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_tick)
        l.ori   r10,r10,lo(_excpt_tick)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x600
_align_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_align)
        l.ori   r10,r10,lo(_excpt_align)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x700
_illinsn_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_illinsn)
        l.ori   r10,r10,lo(_excpt_illinsn)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x800
_int_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_int)
        l.ori   r10,r10,lo(_excpt_int)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x900
_dtlbmiss_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_dtlbmiss)
        l.ori   r10,r10,lo(_excpt_dtlbmiss)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0xa00
_itlbmiss_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_itlbmiss)
        l.ori   r10,r10,lo(_excpt_itlbmiss)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0xb00
_range_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_range)
        l.ori   r10,r10,lo(_excpt_range)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0xc00
_syscall_vector:
        l.addi  r3,r3,4
 
        l.mfspr r4,r0,SPR_SR
        l.andi  r4,r4,7
        l.add   r6,r0,r4
 
        l.mfspr r4,r0,SPR_EPCR_BASE
        l.movhi r5,hi(_sys1)
        l.ori r5,r5,lo(_sys1)
        l.sub r5,r4,r5
 
        l.mfspr r4,r0,SPR_ESR_BASE  /* ESR - set supvisor mode */
        l.ori r4,r4,SPR_SR_SM
        l.mtspr r0,r4,SPR_ESR_BASE
 
        l.movhi r4,hi(_sys2)
        l.ori r4,r4,lo(_sys2)
        l.mtspr r0,r4,SPR_EPCR_BASE
 
        l.rfe
        l.addi  r3,r3,8
 
        .org    0xd00
_break_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_break)
        l.ori   r10,r10,lo(_excpt_break)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0xe00
_trap_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_trap)
        l.ori   r10,r10,lo(_excpt_trap)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
store_regs:
        l.sw    0x00(r1),r3
        l.sw    0x04(r1),r4
        l.sw    0x08(r1),r5
        l.sw    0x0c(r1),r6
        l.sw    0x10(r1),r7
        l.sw    0x14(r1),r8
        l.sw    0x1c(r1),r10
        l.sw    0x20(r1),r11
        l.sw    0x24(r1),r12
        l.sw    0x28(r1),r13
        l.sw    0x2c(r1),r14
        l.sw    0x30(r1),r15
        l.sw    0x34(r1),r16
        l.sw    0x38(r1),r17
        l.sw    0x3c(r1),r18
        l.sw    0x40(r1),r19
        l.sw    0x44(r1),r20
        l.sw    0x48(r1),r21
        l.sw    0x4c(r1),r22
        l.sw    0x50(r1),r23
        l.sw    0x54(r1),r24
        l.sw    0x58(r1),r25
        l.sw    0x5c(r1),r26
        l.sw    0x60(r1),r27
        l.sw    0x64(r1),r28
        l.sw    0x68(r1),r29
        l.sw    0x6c(r1),r30
        l.sw    0x70(r1),r31
        l.jr    r9
        l.nop
 
end_except:
        l.lwz   r3,0x00(r1)
        l.lwz   r4,0x04(r1)
        l.lwz   r5,0x08(r1)
        l.lwz   r6,0x0c(r1)
        l.lwz   r7,0x10(r1)
        l.lwz   r8,0x14(r1)
        l.lwz   r9,0x18(r1)
        l.lwz   r10,0x1c(r1)
        l.lwz   r11,0x20(r1)
        l.lwz   r12,0x24(r1)
        l.lwz   r13,0x28(r1)
        l.lwz   r14,0x2c(r1)
        l.lwz   r15,0x30(r1)
        l.lwz   r16,0x34(r1)
        l.lwz   r17,0x38(r1)
        l.lwz   r18,0x3c(r1)
        l.lwz   r19,0x40(r1)
        l.lwz   r20,0x44(r1)
        l.lwz   r21,0x48(r1)
        l.lwz   r22,0x4c(r1)
        l.lwz   r23,0x50(r1)
        l.lwz   r24,0x54(r1)
        l.lwz   r25,0x58(r1)
        l.lwz   r26,0x5c(r1)
        l.lwz   r27,0x60(r1)
        l.lwz   r28,0x64(r1)
        l.lwz   r29,0x68(r1)
        l.lwz   r30,0x6c(r1)
        l.lwz   r31,0x70(r1)
        l.addi  r1,r1,116
        l.mtspr r0,r9,SPR_EPCR_BASE
        l.rfe
        l.nop
 
  .section .text
 
_except_basic:
_sys1:
        l.addi  r3,r0,-2  /* Enable exceptiom recognition and external interrupt,set user mode */
        l.mfspr r4,r0,SPR_SR
        l.and   r4,r4,r3
        l.ori   r4,r4,(SPR_SR_IEE|SPR_SR_TEE)
        l.mtspr r0,r4,SPR_SR
 
        l.addi  r3,r0,0
        l.sys   1
        l.addi  r3,r3,2
 
_sys2:
        l.addi  r11,r0,0
 
        l.mfspr r4,r0,SPR_SR  /* Check SR */
        l.andi  r4,r4,(SPR_SR_IEE|SPR_SR_TEE|SPR_SR_SM)
        l.sfeqi r4,(SPR_SR_IEE|SPR_SR_TEE|SPR_SR_SM)
        l.bf    1f
        l.nop
        l.addi  r11,r11,1
1:
        l.sfeqi r3,4          /* Check if l.sys or l.rfe has delay slot */
        l.bf    1f
        l.nop
        l.addi  r11,r11,2
1:
        l.sfeqi r5,0x1c       /* Check the EPCR */
        l.bf    1f
        l.nop
        l.addi  r11,r11,4
1:
        l.sfeqi r6,SPR_SR_SM  /* Check the SR when exception is taken */
        l.bf    1f
        l.nop
        l.addi  r11,r11,8
1:
        l.jr    r9
        l.nop
 
_lo_dmmu_en:
        l.mfspr r3,r0,SPR_SR
        l.ori   r3,r3,SPR_SR_DME
        l.mtspr r0,r3,SPR_ESR_BASE
        l.mtspr r0,r9,SPR_EPCR_BASE
        l.rfe
        l.nop
 
_lo_immu_en:
        l.mfspr r3,r0,SPR_SR
        l.ori   r3,r3,SPR_SR_IME
        l.mtspr r0,r3,SPR_ESR_BASE
        l.mtspr r0,r9,SPR_EPCR_BASE
        l.rfe
        l.nop
 
_call:
        l.addi  r11,r0,0
        l.jr    r3
        l.nop
 
_call_with_int:
        l.mfspr r8,r0,SPR_SR
        l.ori   r8,r8,SPR_SR_TEE
        l.mtspr r0,r8,SPR_ESR_BASE
        l.mtspr r0,r3,SPR_EPCR_BASE
        l.rfe
 
_load_acc_32:
        l.movhi r11,hi(0x12345678)
        l.ori   r11,r11,lo(0x12345678)
        l.lwz   r11,0(r4)
        l.jr    r9
        l.nop
 
_load_acc_16:
        l.movhi r11,hi(0x12345678)
        l.ori   r11,r11,lo(0x12345678)
        l.lhz   r11,0(r4)
        l.jr    r9
        l.nop
 
_store_acc_32:
        l.movhi r3,hi(0x12345678)
        l.ori   r3,r3,lo(0x12345678)
        l.sw    0(r4),r3
        l.jr    r9
        l.nop
 
_store_acc_16:
        l.movhi r3,hi(0x12345678)
        l.ori   r3,r3,lo(0x12345678)
        l.sh    0(r4),r3
        l.jr    r9
        l.nop
 
_load_b_acc_32:
        l.movhi r11,hi(0x12345678)
        l.ori   r11,r11,lo(0x12345678)
        l.jr    r9
        l.lwz   r11,0(r4)
 
_b_trap:
        l.jr    r9
_trap:
        l.trap  1
        l.jr    r9
        l.nop
 
_b_range:
        l.jr    r9
_range:
        l.addi  r3,r0,-1
        l.jr    r9
        l.nop
 
_int_trigger:
        l.addi  r11,r0,0
        l.mfspr r3,r0,SPR_SR
        l.ori   r3,r3,SPR_SR_TEE
        l.mtspr r0,r3,SPR_SR
        l.addi  r11,r11,1
 
_int_loop:
        l.j     _int_loop
        l.lwz   r5,0(r4);
 
_jump_back:
        l.addi  r11,r0,0
        l.jr    r9
        l.addi  r11,r11,1
 

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[/] [or1k_old/] [trunk/] [orp/] [orp_soc/] [sw/] [except/] [except_test_s.S] - Blame information for rev 969

Line No.	Rev	Author	Line
1	969	lampret	`/* Support file for c based tests */`
2
3			`#include "spr_defs.h"`
4			`#include "board.h"`
5			`#include "mc.h"`
6
7			`.global _except_basic`
8			`.global _lo_dmmu_en`
9			`.global _lo_immu_en`
10			`.global _call`
11			`.global _call_with_int`
12			`.global _load_acc_32`
13			`.global _load_acc_16`
14			`.global _store_acc_32`
15			`.global _store_acc_16`
16			`.global _load_b_acc_32`
17			`.global _trap`
18			`.global _b_trap`
19			`.global _range`
20			`.global _b_range`
21			`.global _int_trigger`
22			`.global _int_loop`
23			`.global _jump_back`
24
25			`.section .vectors`
26			`.extern _reset_support`
27			`.extern _c_reset`
28			`.extern _excpt_buserr`
29			`.extern _excpt_dpfault`
30			`.extern _excpt_ipfault`
31			`.extern _excpt_tick`
32			`.extern _excpt_align`
33			`.extern _excpt_illinsn`
34			`.extern _excpt_int`
35			`.extern _excpt_dtlbmiss`
36			`.extern _excpt_itlbmiss`
37			`.extern _excpt_range`
38			`.extern _excpt_syscall`
39			`.extern _excpt_break`
40			`.extern _excpt_trap`
41
42			`.org 0x200`
43			`_buserr_vector:`
44			`l.addi r1,r1,-116`
45			`l.sw 0x18(r1),r9`
46			`l.jal store_regs`
47			`l.nop`
48
49			`l.mfspr r3,r0,SPR_EPCR_BASE`
50			`l.movhi r4,hi(_except_pc)`
51			`l.ori r4,r4,lo(_except_pc)`
52			`l.sw 0(r4),r3`
53
54			`l.mfspr r3,r0,SPR_EEAR_BASE`
55			`l.movhi r4,hi(_except_ea)`
56			`l.ori r4,r4,lo(_except_ea)`
57			`l.sw 0(r4),r3`
58
59			`l.movhi r9,hi(end_except)`
60			`l.ori r9,r9,lo(end_except)`
61			`l.movhi r10,hi(_excpt_buserr)`
62			`l.ori r10,r10,lo(_excpt_buserr)`
63			`l.lwz r10,0x0(r10)`
64			`l.jr r10`
65			`l.nop`
66
67			`.org 0x300`
68			`_dpfault_vector:`
69			`l.addi r1,r1,-116`
70			`l.sw 0x18(r1),r9`
71			`l.jal store_regs`
72			`l.nop`
73
74			`l.mfspr r3,r0,SPR_EPCR_BASE`
75			`l.movhi r4,hi(_except_pc)`
76			`l.ori r4,r4,lo(_except_pc)`
77			`l.sw 0(r4),r3`
78
79			`l.mfspr r3,r0,SPR_EEAR_BASE`
80			`l.movhi r4,hi(_except_ea)`
81			`l.ori r4,r4,lo(_except_ea)`
82			`l.sw 0(r4),r3`
83
84			`l.movhi r9,hi(end_except)`
85			`l.ori r9,r9,lo(end_except)`
86			`l.movhi r10,hi(_excpt_dpfault)`
87			`l.ori r10,r10,lo(_excpt_dpfault)`
88			`l.lwz r10,0(r10)`
89			`l.jr r10`
90			`l.nop`
91
92			`.org 0x400`
93			`_ipfault_vector:`
94			`l.addi r1,r1,-116`
95			`l.sw 0x18(r1),r9`
96			`l.jal store_regs`
97			`l.nop`
98
99			`l.mfspr r3,r0,SPR_EPCR_BASE`
100			`l.movhi r4,hi(_except_pc)`
101			`l.ori r4,r4,lo(_except_pc)`
102			`l.sw 0(r4),r3`
103
104			`l.mfspr r3,r0,SPR_EEAR_BASE`
105			`l.movhi r4,hi(_except_ea)`
106			`l.ori r4,r4,lo(_except_ea)`
107			`l.sw 0(r4),r3`
108
109			`l.movhi r9,hi(end_except)`
110			`l.ori r9,r9,lo(end_except)`
111			`l.movhi r10,hi(_excpt_ipfault)`
112			`l.ori r10,r10,lo(_excpt_ipfault)`
113			`l.lwz r10,0(r10)`
114			`l.jr r10`
115			`l.nop`
116
117			`.org 0x500`
118			`_tick_vector:`
119			`l.addi r1,r1,-116`
120			`l.sw 0x18(r1),r9`
121			`l.jal store_regs`
122			`l.nop`
123
124			`l.mfspr r3,r0,SPR_EPCR_BASE`
125			`l.movhi r4,hi(_except_pc)`
126			`l.ori r4,r4,lo(_except_pc)`
127			`l.sw 0(r4),r3`
128
129			`l.mfspr r3,r0,SPR_EEAR_BASE`
130			`l.movhi r4,hi(_except_ea)`
131			`l.ori r4,r4,lo(_except_ea)`
132			`l.sw 0(r4),r3`
133
134			`l.movhi r9,hi(end_except)`
135			`l.ori r9,r9,lo(end_except)`
136			`l.movhi r10,hi(_excpt_tick)`
137			`l.ori r10,r10,lo(_excpt_tick)`
138			`l.lwz r10,0(r10)`
139			`l.jr r10`
140			`l.nop`
141
142			`.org 0x600`
143			`_align_vector:`
144			`l.addi r1,r1,-116`
145			`l.sw 0x18(r1),r9`
146			`l.jal store_regs`
147			`l.nop`
148
149			`l.mfspr r3,r0,SPR_EPCR_BASE`
150			`l.movhi r4,hi(_except_pc)`
151			`l.ori r4,r4,lo(_except_pc)`
152			`l.sw 0(r4),r3`
153
154			`l.mfspr r3,r0,SPR_EEAR_BASE`
155			`l.movhi r4,hi(_except_ea)`
156			`l.ori r4,r4,lo(_except_ea)`
157			`l.sw 0(r4),r3`
158
159			`l.movhi r9,hi(end_except)`
160			`l.ori r9,r9,lo(end_except)`
161			`l.movhi r10,hi(_excpt_align)`
162			`l.ori r10,r10,lo(_excpt_align)`
163			`l.lwz r10,0(r10)`
164			`l.jr r10`
165			`l.nop`
166
167			`.org 0x700`
168			`_illinsn_vector:`
169			`l.addi r1,r1,-116`
170			`l.sw 0x18(r1),r9`
171			`l.jal store_regs`
172			`l.nop`
173
174			`l.mfspr r3,r0,SPR_EPCR_BASE`
175			`l.movhi r4,hi(_except_pc)`
176			`l.ori r4,r4,lo(_except_pc)`
177			`l.sw 0(r4),r3`
178
179			`l.mfspr r3,r0,SPR_EEAR_BASE`
180			`l.movhi r4,hi(_except_ea)`
181			`l.ori r4,r4,lo(_except_ea)`
182			`l.sw 0(r4),r3`
183
184			`l.movhi r9,hi(end_except)`
185			`l.ori r9,r9,lo(end_except)`
186			`l.movhi r10,hi(_excpt_illinsn)`
187			`l.ori r10,r10,lo(_excpt_illinsn)`
188			`l.lwz r10,0(r10)`
189			`l.jr r10`
190			`l.nop`
191
192			`.org 0x800`
193			`_int_vector:`
194			`l.addi r1,r1,-116`
195			`l.sw 0x18(r1),r9`
196			`l.jal store_regs`
197			`l.nop`
198
199			`l.mfspr r3,r0,SPR_EPCR_BASE`
200			`l.movhi r4,hi(_except_pc)`
201			`l.ori r4,r4,lo(_except_pc)`
202			`l.sw 0(r4),r3`
203
204			`l.mfspr r3,r0,SPR_EEAR_BASE`
205			`l.movhi r4,hi(_except_ea)`
206			`l.ori r4,r4,lo(_except_ea)`
207			`l.sw 0(r4),r3`
208
209			`l.movhi r9,hi(end_except)`
210			`l.ori r9,r9,lo(end_except)`
211			`l.movhi r10,hi(_excpt_int)`
212			`l.ori r10,r10,lo(_excpt_int)`
213			`l.lwz r10,0(r10)`
214			`l.jr r10`
215			`l.nop`
216
217			`.org 0x900`
218			`_dtlbmiss_vector:`
219			`l.addi r1,r1,-116`
220			`l.sw 0x18(r1),r9`
221			`l.jal store_regs`
222			`l.nop`
223
224			`l.mfspr r3,r0,SPR_EPCR_BASE`
225			`l.movhi r4,hi(_except_pc)`
226			`l.ori r4,r4,lo(_except_pc)`
227			`l.sw 0(r4),r3`
228
229			`l.mfspr r3,r0,SPR_EEAR_BASE`
230			`l.movhi r4,hi(_except_ea)`
231			`l.ori r4,r4,lo(_except_ea)`
232			`l.sw 0(r4),r3`
233
234			`l.movhi r9,hi(end_except)`
235			`l.ori r9,r9,lo(end_except)`
236			`l.movhi r10,hi(_excpt_dtlbmiss)`
237			`l.ori r10,r10,lo(_excpt_dtlbmiss)`
238			`l.lwz r10,0(r10)`
239			`l.jr r10`
240			`l.nop`
241
242			`.org 0xa00`
243			`_itlbmiss_vector:`
244			`l.addi r1,r1,-116`
245			`l.sw 0x18(r1),r9`
246			`l.jal store_regs`
247			`l.nop`
248
249			`l.mfspr r3,r0,SPR_EPCR_BASE`
250			`l.movhi r4,hi(_except_pc)`
251			`l.ori r4,r4,lo(_except_pc)`
252			`l.sw 0(r4),r3`
253
254			`l.mfspr r3,r0,SPR_EEAR_BASE`
255			`l.movhi r4,hi(_except_ea)`
256			`l.ori r4,r4,lo(_except_ea)`
257			`l.sw 0(r4),r3`
258
259			`l.movhi r9,hi(end_except)`
260			`l.ori r9,r9,lo(end_except)`
261			`l.movhi r10,hi(_excpt_itlbmiss)`
262			`l.ori r10,r10,lo(_excpt_itlbmiss)`
263			`l.lwz r10,0(r10)`
264			`l.jr r10`
265			`l.nop`
266
267			`.org 0xb00`
268			`_range_vector:`
269			`l.addi r1,r1,-116`
270			`l.sw 0x18(r1),r9`
271			`l.jal store_regs`
272			`l.nop`
273
274			`l.mfspr r3,r0,SPR_EPCR_BASE`
275			`l.movhi r4,hi(_except_pc)`
276			`l.ori r4,r4,lo(_except_pc)`
277			`l.sw 0(r4),r3`
278
279			`l.mfspr r3,r0,SPR_EEAR_BASE`
280			`l.movhi r4,hi(_except_ea)`
281			`l.ori r4,r4,lo(_except_ea)`
282			`l.sw 0(r4),r3`
283
284			`l.movhi r9,hi(end_except)`
285			`l.ori r9,r9,lo(end_except)`
286			`l.movhi r10,hi(_excpt_range)`
287			`l.ori r10,r10,lo(_excpt_range)`
288			`l.lwz r10,0(r10)`
289			`l.jr r10`
290			`l.nop`
291
292			`.org 0xc00`
293			`_syscall_vector:`
294			`l.addi r3,r3,4`
295
296			`l.mfspr r4,r0,SPR_SR`
297			`l.andi r4,r4,7`
298			`l.add r6,r0,r4`
299
300			`l.mfspr r4,r0,SPR_EPCR_BASE`
301			`l.movhi r5,hi(_sys1)`
302			`l.ori r5,r5,lo(_sys1)`
303			`l.sub r5,r4,r5`
304
305			`l.mfspr r4,r0,SPR_ESR_BASE /* ESR - set supvisor mode */`
306			`l.ori r4,r4,SPR_SR_SM`
307			`l.mtspr r0,r4,SPR_ESR_BASE`
308
309			`l.movhi r4,hi(_sys2)`
310			`l.ori r4,r4,lo(_sys2)`
311			`l.mtspr r0,r4,SPR_EPCR_BASE`
312
313			`l.rfe`
314			`l.addi r3,r3,8`
315
316			`.org 0xd00`
317			`_break_vector:`
318			`l.addi r1,r1,-116`
319			`l.sw 0x18(r1),r9`
320			`l.jal store_regs`
321			`l.nop`
322
323			`l.mfspr r3,r0,SPR_EPCR_BASE`
324			`l.movhi r4,hi(_except_pc)`
325			`l.ori r4,r4,lo(_except_pc)`
326			`l.sw 0(r4),r3`
327
328			`l.mfspr r3,r0,SPR_EEAR_BASE`
329			`l.movhi r4,hi(_except_ea)`
330			`l.ori r4,r4,lo(_except_ea)`
331			`l.sw 0(r4),r3`
332
333			`l.movhi r9,hi(end_except)`
334			`l.ori r9,r9,lo(end_except)`
335			`l.movhi r10,hi(_excpt_break)`
336			`l.ori r10,r10,lo(_excpt_break)`
337			`l.lwz r10,0(r10)`
338			`l.jr r10`
339			`l.nop`
340
341			`.org 0xe00`
342			`_trap_vector:`
343			`l.addi r1,r1,-116`
344			`l.sw 0x18(r1),r9`
345			`l.jal store_regs`
346			`l.nop`
347
348			`l.mfspr r3,r0,SPR_EPCR_BASE`
349			`l.movhi r4,hi(_except_pc)`
350			`l.ori r4,r4,lo(_except_pc)`
351			`l.sw 0(r4),r3`
352
353			`l.mfspr r3,r0,SPR_EEAR_BASE`
354			`l.movhi r4,hi(_except_ea)`
355			`l.ori r4,r4,lo(_except_ea)`
356			`l.sw 0(r4),r3`
357
358			`l.movhi r9,hi(end_except)`
359			`l.ori r9,r9,lo(end_except)`
360			`l.movhi r10,hi(_excpt_trap)`
361			`l.ori r10,r10,lo(_excpt_trap)`
362			`l.lwz r10,0(r10)`
363			`l.jr r10`
364			`l.nop`
365
366			`store_regs:`
367			`l.sw 0x00(r1),r3`
368			`l.sw 0x04(r1),r4`
369			`l.sw 0x08(r1),r5`
370			`l.sw 0x0c(r1),r6`
371			`l.sw 0x10(r1),r7`
372			`l.sw 0x14(r1),r8`
373			`l.sw 0x1c(r1),r10`
374			`l.sw 0x20(r1),r11`
375			`l.sw 0x24(r1),r12`
376			`l.sw 0x28(r1),r13`
377			`l.sw 0x2c(r1),r14`
378			`l.sw 0x30(r1),r15`
379			`l.sw 0x34(r1),r16`
380			`l.sw 0x38(r1),r17`
381			`l.sw 0x3c(r1),r18`
382			`l.sw 0x40(r1),r19`
383			`l.sw 0x44(r1),r20`
384			`l.sw 0x48(r1),r21`
385			`l.sw 0x4c(r1),r22`
386			`l.sw 0x50(r1),r23`
387			`l.sw 0x54(r1),r24`
388			`l.sw 0x58(r1),r25`
389			`l.sw 0x5c(r1),r26`
390			`l.sw 0x60(r1),r27`
391			`l.sw 0x64(r1),r28`
392			`l.sw 0x68(r1),r29`
393			`l.sw 0x6c(r1),r30`
394			`l.sw 0x70(r1),r31`
395			`l.jr r9`
396			`l.nop`
397
398			`end_except:`
399			`l.lwz r3,0x00(r1)`
400			`l.lwz r4,0x04(r1)`
401			`l.lwz r5,0x08(r1)`
402			`l.lwz r6,0x0c(r1)`
403			`l.lwz r7,0x10(r1)`
404			`l.lwz r8,0x14(r1)`
405			`l.lwz r9,0x18(r1)`
406			`l.lwz r10,0x1c(r1)`
407			`l.lwz r11,0x20(r1)`
408			`l.lwz r12,0x24(r1)`
409			`l.lwz r13,0x28(r1)`
410			`l.lwz r14,0x2c(r1)`
411			`l.lwz r15,0x30(r1)`
412			`l.lwz r16,0x34(r1)`
413			`l.lwz r17,0x38(r1)`
414			`l.lwz r18,0x3c(r1)`
415			`l.lwz r19,0x40(r1)`
416			`l.lwz r20,0x44(r1)`
417			`l.lwz r21,0x48(r1)`
418			`l.lwz r22,0x4c(r1)`
419			`l.lwz r23,0x50(r1)`
420			`l.lwz r24,0x54(r1)`
421			`l.lwz r25,0x58(r1)`
422			`l.lwz r26,0x5c(r1)`
423			`l.lwz r27,0x60(r1)`
424			`l.lwz r28,0x64(r1)`
425			`l.lwz r29,0x68(r1)`
426			`l.lwz r30,0x6c(r1)`
427			`l.lwz r31,0x70(r1)`
428			`l.addi r1,r1,116`
429			`l.mtspr r0,r9,SPR_EPCR_BASE`
430			`l.rfe`
431			`l.nop`
432
433			`.section .text`
434
435			`_except_basic:`
436			`_sys1:`
437			`l.addi r3,r0,-2 /* Enable exceptiom recognition and external interrupt,set user mode */`
438			`l.mfspr r4,r0,SPR_SR`
439			`l.and r4,r4,r3`
440			`l.ori r4,r4,(SPR_SR_IEE\|SPR_SR_TEE)`
441			`l.mtspr r0,r4,SPR_SR`
442
443			`l.addi r3,r0,0`
444			`l.sys 1`
445			`l.addi r3,r3,2`
446
447			`_sys2:`
448			`l.addi r11,r0,0`
449
450			`l.mfspr r4,r0,SPR_SR /* Check SR */`
451			`l.andi r4,r4,(SPR_SR_IEE\|SPR_SR_TEE\|SPR_SR_SM)`
452			`l.sfeqi r4,(SPR_SR_IEE\|SPR_SR_TEE\|SPR_SR_SM)`
453			`l.bf 1f`
454			`l.nop`
455			`l.addi r11,r11,1`
456			`1:`
457			`l.sfeqi r3,4 /* Check if l.sys or l.rfe has delay slot */`
458			`l.bf 1f`
459			`l.nop`
460			`l.addi r11,r11,2`
461			`1:`
462			`l.sfeqi r5,0x1c /* Check the EPCR */`
463			`l.bf 1f`
464			`l.nop`
465			`l.addi r11,r11,4`
466			`1:`
467			`l.sfeqi r6,SPR_SR_SM /* Check the SR when exception is taken */`
468			`l.bf 1f`
469			`l.nop`
470			`l.addi r11,r11,8`
471			`1:`
472			`l.jr r9`
473			`l.nop`
474
475			`_lo_dmmu_en:`
476			`l.mfspr r3,r0,SPR_SR`
477			`l.ori r3,r3,SPR_SR_DME`
478			`l.mtspr r0,r3,SPR_ESR_BASE`
479			`l.mtspr r0,r9,SPR_EPCR_BASE`
480			`l.rfe`
481			`l.nop`
482
483			`_lo_immu_en:`
484			`l.mfspr r3,r0,SPR_SR`
485			`l.ori r3,r3,SPR_SR_IME`
486			`l.mtspr r0,r3,SPR_ESR_BASE`
487			`l.mtspr r0,r9,SPR_EPCR_BASE`
488			`l.rfe`
489			`l.nop`
490
491			`_call:`
492			`l.addi r11,r0,0`
493			`l.jr r3`
494			`l.nop`
495
496			`_call_with_int:`
497			`l.mfspr r8,r0,SPR_SR`
498			`l.ori r8,r8,SPR_SR_TEE`
499			`l.mtspr r0,r8,SPR_ESR_BASE`
500			`l.mtspr r0,r3,SPR_EPCR_BASE`
501			`l.rfe`
502
503			`_load_acc_32:`
504			`l.movhi r11,hi(0x12345678)`
505			`l.ori r11,r11,lo(0x12345678)`
506			`l.lwz r11,0(r4)`
507			`l.jr r9`
508			`l.nop`
509
510			`_load_acc_16:`
511			`l.movhi r11,hi(0x12345678)`
512			`l.ori r11,r11,lo(0x12345678)`
513			`l.lhz r11,0(r4)`
514			`l.jr r9`
515			`l.nop`
516
517			`_store_acc_32:`
518			`l.movhi r3,hi(0x12345678)`
519			`l.ori r3,r3,lo(0x12345678)`
520			`l.sw 0(r4),r3`
521			`l.jr r9`
522			`l.nop`
523
524			`_store_acc_16:`
525			`l.movhi r3,hi(0x12345678)`
526			`l.ori r3,r3,lo(0x12345678)`
527			`l.sh 0(r4),r3`
528			`l.jr r9`
529			`l.nop`
530
531			`_load_b_acc_32:`
532			`l.movhi r11,hi(0x12345678)`
533			`l.ori r11,r11,lo(0x12345678)`
534			`l.jr r9`
535			`l.lwz r11,0(r4)`
536
537			`_b_trap:`
538			`l.jr r9`
539			`_trap:`
540			`l.trap 1`
541			`l.jr r9`
542			`l.nop`
543
544			`_b_range:`
545			`l.jr r9`
546			`_range:`
547			`l.addi r3,r0,-1`
548			`l.jr r9`
549			`l.nop`
550
551			`_int_trigger:`
552			`l.addi r11,r0,0`
553			`l.mfspr r3,r0,SPR_SR`
554			`l.ori r3,r3,SPR_SR_TEE`
555			`l.mtspr r0,r3,SPR_SR`
556			`l.addi r11,r11,1`
557
558			`_int_loop:`
559			`l.j _int_loop`
560			`l.lwz r5,0(r4);`
561
562			`_jump_back:`
563			`l.addi r11,r0,0`
564			`l.jr r9`
565			`l.addi r11,r11,1`
566