OpenCores
URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] [or1k_old/] [trunk/] [orp/] [orp_soc/] [sw.old/] [int_test/] [int_test.S] - Blame information for rev 1765

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 782 lampret 
/* Within the test we'll use following global variables:
2 
 
3 
   r16 interrupt counter
4 
   r17 current tick timer comparison counter
5 
   r18 sanity counter
6 
   r19 loop counter
7 
   r20 temp value of SR reg
8 
   r21 temp value of TTMR reg.
9 
   r23 RAM_START
10 
 
11 
   r25-r31 used by int handler
12 
 
13 
   The test do the following:
14 
   We set up the tick timer to trigger once and then we trigger interrupts incrementally
15 
   on every cycle in the specified test program; on interrupt handler we check if data computed
16 
   so far exactly matches precalculated values. If interrupt has returned incorreclty, we can
17 
   detect this using assertion routine at the end.
18 
*/
19 
 
20 
#include "../support/spr_defs.h"
21 
#define  RAM_START 0x80080000
22 
 
23 
.org 0x100
24 
  l.nop
25 
  l.j     _main
26 
  l.nop
27 
 
28 
.org 0x500
29 
#
30 
# Interrupt handler
31 
#
32 
 
33 
  l.addi  r31,r3,0
34 
# get interrupted program pc
35 
  l.mfspr r25,r0,SPR_EPCR_BASE
36 
 
37 
# calculate instruction address
38 
  l.movhi r26,hi(_ie_start)
39 
  l.ori   r26,r26,lo(_ie_start)
40 
  l.addi  r3,r25,0    #print insn index
41 
  l.nop   2
42 
  l.sub   r25,r25,r26
43 
  l.addi  r3,r25,0    #print insn index
44 
  l.nop   2
45 
 
46 
  l.addi  r3,r31,0    # restore r3
47 
  l.sfeqi r25, 0x00
48 
  l.bf    _i00
49 
  l.sfeqi r25, 0x04
50 
  l.bf    _i04
51 
  l.sfeqi r25, 0x08
52 
  l.bf    _i08
53 
  l.sfeqi r25, 0x0c
54 
  l.bf    _i0c
55 
  l.sfeqi r25, 0x10
56 
  l.bf    _i10
57 
  l.sfeqi r25, 0x14
58 
  l.bf    _i14
59 
  l.sfeqi r25, 0x18
60 
  l.bf    _i18
61 
  l.sfeqi r25, 0x1c
62 
  l.bf    _i1c
63 
  l.sfeqi r25, 0x20
64 
  l.bf    _i20
65 
  l.sfeqi r25, 0x24
66 
  l.bf    _i24
67 
  l.sfeqi r25, 0x28
68 
  l.bf    _i28
69 
  l.sfeqi r25, 0x2c
70 
  l.bf    _i2c
71 
  l.sfeqi r25, 0x30
72 
  l.bf    _i30
73 
  l.sfeqi r25, 0x34
74 
  l.bf    _i34
75 
  l.sfeqi r25, 0x38
76 
  l.bf    _i38
77 
  l.nop
78 
 
79 
# value not defined
80 
_die:
81 
  l.nop   2             #print r3
82 
 
83 
  l.addi  r3,r0,0xeeee
84 
  l.nop   2
85 
  l.addi  r3,r0,1
86 
  l.nop   1
87 
1:
88 
  l.j     1b
89 
  l.nop
90 
 
91 
.section  .text
92 
_main:
93 
        l.nop
94 
        l.nop
95 
 
96 
#
97 
# set tick counter to initial 3 cycles
98 
#
99 
  l.addi r16,r0,0
100 
  l.addi r17,r0,1
101 
  l.addi r18,r0,0
102 
  l.addi r19,r0,0
103 
  l.addi r22,r0,0
104 
 
105 
  l.movhi r23,hi(RAM_START)
106 
  l.ori   r23,r23,lo(RAM_START)
107 
 
108 
#
109 
# unmask all ints
110 
#
111 
        l.movhi r5,0xffff
112 
        l.ori   r5,r5,0xffff
113 
        l.mtspr r0,r5,SPR_PICMR         # set PICMR
114 
 
115 
# Set r20 to hold enable exceptions and interrupts
116 
        l.mfspr r20,r0,SPR_SR
117 
        l.ori r20,r20,SPR_SR_SUPV|SPR_SR_EXR|SPR_SR_EIR|SPR_SR_F
118 
 
119 
# Set r21 to hold value of TTMR
120 
        l.movhi r5,hi(SPR_TTMR_SR | SPR_TTMR_IE)
121 
        l.add  r21,r5,r17
122 
 
123 
#
124 
# MAIN LOOP
125 
#
126 
_main_loop:
127 
# reinitialize memory and registers
128 
  l.addi  r3,r0,0xaaaa
129 
  l.addi  r9,r0,0xbbbb
130 
  l.sw    0(r23),r3
131 
  l.sw    4(r23),r9
132 
  l.sw    8(r23),r3
133 
 
134 
# Reinitializes tick timer
135 
  l.addi  r17,r17,1
136 
  l.mtspr r0,r0,SPR_TTCR                # set TTCR
137 
  l.mtspr r0,r21,SPR_TTMR               # set TTMR
138 
  l.mtspr r0,r0,SPR_TTCR                # set TTCR
139 
        l.addi  r21,r21,1
140 
 
141 
# Enable exceptions and interrupts
142 
        l.mtspr r0,r20,SPR_SR   # set SR
143 
 
144 
##### TEST CODE #####
145 
_ie_start:
146 
  l.movhi r3,0x1234         #00
147 
  l.sw    0(r23),r3         #04
148 
  l.movhi r3,hi(RAM_START)  #08
149 
  l.lwz   r3,0(r3)          #0c
150 
  l.movhi r3,hi(RAM_START)  #10
151 
  l.addi  r3,r3,4           #14
152 
  l.j     1f                #18
153 
  l.lwz   r3,0(r3)          #1c
154 
  l.addi  r3,r3,1           #20
155 
1:
156 
  l.sfeqi r3,0xdead         #24
157 
  l.jal   2f                #28
158 
  l.addi  r3,r0,0x5678      #2c
159 
 
160 
_return_addr:
161 
2:
162 
  l.bf    _die              #30
163 
  l.sw    8(r23),r3         #34
164 
_ie_end:
165 
  l.nop                     #38
166 
##### END OF TEST CODE #####
167 
 
168 
# do some testing
169 
 
170 
  l.j     _main_loop
171 
  l.nop
172 
 
173 
_i00:
174 
  l.sfeqi r3,0xaaaa
175 
  l.bnf   _die
176 
  l.nop
177 
  l.j     _resume
178 
  l.nop
179 
_i04:
180 
  l.movhi  r26,0x1234
181 
  l.sfeq   r3,r26
182 
  l.bnf   _die
183 
  l.nop
184 
  l.lwz   r26,0(r23)
185 
  l.sfeqi r26,0xaaaa
186 
  l.bnf   _die
187 
  l.nop
188 
  l.j     _resume
189 
  l.nop
190 
_i08:
191 
  l.movhi r26,0x1234
192 
  l.sfeq  r3,r26
193 
  l.bnf   _die
194 
  l.nop
195 
  l.lwz   r27,0(r23)
196 
  l.sfeq  r27,r26
197 
  l.bnf   _die
198 
  l.nop
199 
  l.j     _resume
200 
  l.nop
201 
_i0c:
202 
  l.sfeq  r3,r23
203 
  l.bnf   _die
204 
  l.nop
205 
  l.j     _resume
206 
  l.nop
207 
_i10:
208 
  l.movhi r26,0x1234
209 
  l.sfeq  r26,r3
210 
  l.bnf   _die
211 
  l.nop
212 
  l.j     _resume
213 
  l.nop
214 
_i14:
215 
  l.sfeq  r3,r23
216 
  l.bnf   _die
217 
  l.nop
218 
  l.j     _resume
219 
  l.nop
220 
_i18:
221 
  l.addi  r26,r23,4
222 
  l.sfeq  r3,r26
223 
  l.bnf   _die
224 
  l.nop
225 
  l.j     _resume
226 
  l.nop
227 
_i1c:
228 
  l.j     _die
229 
  l.nop
230 
_i20:
231 
  l.j     _die
232 
  l.nop
233 
_i24:
234 
  l.mfspr r26,r0,SPR_ESR_BASE
235 
  l.addi  r30,r3,0
236 
  l.addi  r3,r26,0
237 
  l.nop   2
238 
  l.addi  r3,r30,0
239 
  l.andi  r26,r26,SPR_SR_F
240 
  l.sfeq  r26,r0
241 
  l.bf   _die
242 
  l.nop
243 
  l.sfeqi  r3,0xbbbb
244 
  l.bnf   _die
245 
  l.nop
246 
  l.j     _resume
247 
  l.nop
248 
_i28:
249 
  l.mfspr r26,r0,SPR_ESR_BASE
250 
  l.addi  r30,r3,0
251 
  l.addi  r3,r26,0
252 
  l.nop   2
253 
  l.addi  r3,r30,0
254 
  l.andi  r26,r26,SPR_SR_F
255 
  l.sfeq  r26,r0
256 
  l.bnf    _die
257 
  l.nop
258 
  l.sfeqi  r22,1
259 
  l.bf     _resume
260 
  l.addi   r22,r0,1
261 
  l.sfeqi  r9,0xbbbb
262 
  l.bnf   _die
263 
  l.nop
264 
  l.j     _resume
265 
  l.nop
266 
_i2c:
267 
  l.movhi  r26,hi(_return_addr)
268 
  l.ori    r26,r26,lo(_return_addr)
269 
  l.sfeq   r9,r26
270 
  l.bnf   _die
271 
  l.nop
272 
  l.sfeqi  r3,0xbbbb
273 
  l.bnf   _die
274 
  l.nop
275 
  l.j     _resume
276 
  l.nop
277 
_i30:
278 
  l.sfeqi  r3,0x5678
279 
  l.bnf   _die
280 
  l.nop
281 
  l.j     _resume
282 
  l.nop
283 
_i34:
284 
  l.sfeqi  r3,0x5678
285 
  l.bnf   _die
286 
  l.nop
287 
  l.lwz    r26,8(r23)
288 
  l.sfeqi  r26,0xaaaa
289 
  l.bnf   _die
290 
  l.nop
291 
  l.j     _resume
292 
  l.nop
293 
_i38:
294 
  l.lwz    r26,8(r23)
295 
  l.sfeqi  r26,0x5678
296 
  l.bnf   _die
297 
  l.nop
298 
#
299 
# mark finished ok
300 
#
301 
  l.movhi r3,hi(0xdeaddead)
302 
  l.ori   r3,r3,lo(0xdeaddead)
303 
  l.nop   2
304 
  l.addi  r3,r0,0
305 
  l.nop   1
306 
_ok:
307 
  l.j     _ok
308 
  l.nop
309 
 
310 
_resume:
311 
  l.mfspr  r27,r0,SPR_ESR_BASE
312 
  l.addi   r26,r0,SPR_SR_EIR|SPR_SR_EXR
313 
  l.addi   r28,r0,-1
314 
  l.xor    r26,r26,r28
315 
  l.and    r26,r26,r27
316 
  l.mtspr  r0,r26,SPR_ESR_BASE
317 
 
318 
  l.rfe
319 
  l.addi    r3,r3,5         # should not be executed

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.