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[/] [or1k_old/] [trunk/] [orp/] [orp_soc/] [sw.old/] [mmu/] [dmmu.S] - Blame information for rev 1782

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Line No. Rev Author Line
1 782 lampret 
/* Basic instruction set test */
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#include "../support/spr_defs.h"
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.global _main
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.global _buserr_except
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.global _dpf_except
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.global _ipf_except
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.global _lpint_except
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.global _align_except
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.global _illegal_except
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.global _hpint_except
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.global _dtlbmiss_except
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.global _itlbmiss_except
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.global _range_except
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.global _syscall_except
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.global _res1_except
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.global _trap_except
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.global _res2_except
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_buserr_except:
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_ipf_except:
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_lpint_except:
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_align_except:
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_illegal_except:
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_hpint_except:
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_itlbmiss_except:
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_range_except:
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_syscall_except:
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_res1_except:
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_trap_except:
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_res2_except:
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        l.nop
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        l.ori   r3,r0,0xeeee
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        l.jal   _report
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        l.nop
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        l.jal   _exit
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        l.nop
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_dpf_except:
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        l.addi  r14,r0,64
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        l.movhi r5,hi(0x80000000|SPR_DTLBMR_V)
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        l.ori   r5,r5,lo(0x80000000|SPR_DTLBMR_V)
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        l.mtspr r0,r5,SPR_DTLBMR_BASE(0)
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        l.movhi r5,hi(0x80100000|SPR_DTLBTR_SWE|SPR_DTLBTR_SRE)
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        l.ori   r5,r5,lo(0x80100000|SPR_DTLBTR_SWE|SPR_DTLBTR_SRE)
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        l.mtspr r0,r5,SPR_DTLBTR_BASE(0)
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        l.rfe
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        l.nop
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_dtlbmiss_except:
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        // Valid entry, but no load/store access
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        l.addi  r13,r0,128
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        l.movhi r5,hi(0x80000000|SPR_DTLBMR_V)
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        l.ori   r5,r5,lo(0x80000000|SPR_DTLBMR_V)
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        l.mtspr r0,r5,SPR_DTLBMR_BASE(0)
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        l.ori   r5,r0,0
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        l.mtspr r0,r5,SPR_DTLBTR_BASE(0)
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        l.rfe
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        l.nop
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//
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// r4, r5       - used by exception handlers
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// r7, r8       - used by main for setting TLB
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// r10          - data pointer to magic words
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// r11          - accumulator of magic words
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// r12          - for loading/storing magic words
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// r13, r14     - used ONLY by exception handlers for magic words
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_main:
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        l.nop
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        l.addi  r11,r0,1
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        l.addi  r12,r0,1024
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        l.movhi r10,hi(0x80100000)
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        l.ori   r10,r10,lo(0x80100000)
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        l.sw    0(r10),r12
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        l.addi  r12,r0,1
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        l.movhi r10,hi(0x80000000)
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        l.ori   r10,r10,lo(0x80000000)
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        l.sw    0(r10),r12
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        // Invalidate entry
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        l.movhi r7,hi(0x80010000)
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        l.mtspr r0,r7,SPR_DTLBMR_BASE(0)
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        l.ori   r7,r0,0
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        l.mtspr r0,r7,SPR_DTLBTR_BASE(0)
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        // Enable DMMU
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        l.ori   r8,r0,SPR_SR_DME
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        l.mfspr r7,r0,SPR_SR
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        l.or    r7,r7,r8
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        l.mtspr r0,r7,SPR_SR
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        // Invoke DTLB miss and DPF exceptions
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        l.sw    32(r10),r7
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        // Magic word read
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        l.add   r12,r0,r0
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        l.lwz   r12,0(r10)
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        l.add   r11,r11,r12
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        l.add   r11,r11,r13
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        l.add   r11,r11,r14
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        // Set cache inhibit (CI) bit
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        l.movhi r5,hi(0x80100000|SPR_DTLBTR_SWE|SPR_DTLBTR_SRE)
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        l.ori   r5,r5,lo(0x80100000|SPR_DTLBTR_SWE|SPR_DTLBTR_SRE)
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        l.mtspr r0,r5,SPR_DTLBTR_BASE(0)
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        // Read from external memory (must be checked manually)
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        l.lwz   r12,32(r10)
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        // Exit
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        l.nop
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        l.movhi r12,hi(0xdeadda6c)
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        l.ori   r12,r12,lo(0xdeadda6c)
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        l.xor   r3,r11,r12
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        l.jal   _report
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        l.nop
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        l.jal   _exit
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        l.nop
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        l.nop
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