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/* sim.cfg -- Simulator configuration script file
   Copyright (C) 2001, Marko Mlinar, markom@opencores.org
 
This file includes a lot of help about configurations and default one
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
 
/* INTRODUCTION
 
   The or1ksim have various parameters, which can be set in configuration
   files.  Multiple configurations may be used and switched between at
   or1ksim startup.
   By default, or1ksim loads condfiguration file from './sim.cfg' and if not
   found it checks '~/.or1k/sim.cfg'. If even this file is not found or
   all parameters are not defined, default configuration is used.
   Users should not rely on default configuration, but rather redefine all
   critical settings, since default configuration may differ in newer
   versions of the or1ksim.
   If multiple configurations are used, user can switch between them by
   supplying -f  option when starting simulator.
 
   This file may contain (standard C) only comments - no // support.
 
   Like normal configuration file, this file is divided in sections,
   where each section is described in detail also.
 
   Some section also have subsections. One example of such subsection is
   block:
 
   device 
     instance specific parameters...
   enddevice
 
   which creates a device instance.
*/
 
 
/* MEMORY SECTION
 
   This section specifies how is initial memory generated and which blocks
   it consist of.
 
   type = random/unknown/pattern
      specifies the initial memory values. 'random' parameter generate
      random memory using seed 'random_seed' parameter. 'pattern' parameter
      fills memory with 'pattern' parameter and 'unknown' does not specify
      how memory should be generated - the fastest option.
 
   random_seed = 
      random seed for randomizer, used if type = random
 
   pattern = 
      pattern to fill memory, used if type = pattern
 
   nmemories = 
      number of memory instances connected
 
   instance specific:
     baseaddr = 
        memory start address
 
     size = 
        memory size
 
     name = ""
        memory block name
 
     ce = 
        chip enable index of the memory instance
 
     delayr = 
        cycles, required for read access, -1 if instance does not support reading
 
     delayw = 
        cycles, required for write access, -1 if instance does not support writing
 
     16550 = 0/1
        0, if this device is uart 16450 and 1, if it is 16550
 
     log = ""
        filename, where to log memory accesses to, no log, if log command is not specified
*/
 
section memory
  /*random_seed = 12345
  type = random*/
  pattern = 0x00
  type = unknown /* Fastest */
 
  nmemories = 3
  device 0
    name = "Flash"
    ce = 0
    baseaddr = 0x00000000
    size = 0x00200000
    delayr = 10
    delayw = -1
  enddevice
 
  device 1
    name = "RAM1"
    ce = 1
    baseaddr = 0x40000000
    size = 0x00200000
    delayr = 2
    delayw = 4
  enddevice
 
  device 2
    name = "RAM2"
    ce = 2
    baseaddr = 0x80000000
    size = 0x00200000
    delayr = 2
    delayw = 4
  enddevice
 
end
 
 
/* IMMU SECTION
 
    This section configures Instruction Memory Menangement Unit
 
    enabled = 0/1
       whether IMMU is enabled
       (NOTE: UPR bit is set)
 
    nsets = 
       number of ITLB sets; must be power of two
 
    nways = 
       number of ITLB ways
 
    pagesize = 
       instruction page size; must be power of two
 
    entrysize = 
       instruction entry size in bytes
 
    ustates = 
       number of ITLB usage states (2, 3, 4 etc., max is 4)
*/
 
section immu
  enabled = 0
  nsets = 32
  nways = 1
  pagesize = 8192
end
 
 
/* DMMU SECTION
 
    This section configures Data Memory Menangement Unit
 
    enabled = 0/1
       whether DMMU is enabled
       (NOTE: UPR bit is set)
 
    nsets = 
       number of DTLB sets; must be power of two
 
    nways = 
       number of DTLB ways
 
    pagesize = 
       data page size; must be power of two
 
    entrysize = 
       data entry size in bytes
 
    ustates = 
       number of DTLB usage states (2, 3, 4 etc., max is 4)
*/
 
section dmmu
  enabled = 0
  nsets = 32
  nways = 1
  pagesize = 8192
end
 
 
/* IC SECTION
 
    This section configures Instruction Cache
 
    enabled = 0/1
       whether IC is enabled
       (NOTE: UPR bit is set)
 
    nsets = 
       number of IC sets; must be power of two
 
    nways = 
       number of IC ways
 
    blocksize = 
       IC block size in bytes; must be power of two
 
    ustates = 
       number of IC usage states (2, 3, 4 etc., max is 4)
*/
 
section ic
  enabled = 0
  nsets = 512
  nways = 1
  blocksize = 16
end
 
 
/* DC SECTION
 
    This section configures Data Cache
 
    enabled = 0/1
       whether DC is enabled
       (NOTE: UPR bit is set)
 
    nsets = 
       number of DC sets; must be power of two
 
    nways = 
       number of DC ways
 
    blocksize = 
       DC block size in bytes; must be power of two
 
    ustates = 
       number of DC usage states (2, 3, 4 etc., max is 4)
*/
 
section dc
  enabled = 0
  nsets = 512
  nways = 1
  blocksize = 16
end
 
/* SIM SECTION
 
  This section specifies how should sim behave.
 
  verbose = 0/1
      whether to print out extra messages
 
  debug = 0-9
      = 0 disabled debug messages
      1-9 level of sim debug information, greater the number more verbose is
          the output
 
  profile = 0/1
      whether to generate profiling file 'sim.profile'
 
  prof_fn = ""
      filename, where to generate profiling info, used
      only if 'profile' is set
 
  history = 0/1
      whether instruction execution flow is tracked for
      display by simulator hist command. Useful for
      back-trace debugging.
 
  iprompt = 0/1
      whether we strart in interactive prompt
 
  exe_log = 0/1
      whether execution log should be generated
 
  exe_log_fn = ""
      where to put execution log in, used only if 'exe_log'
      is set
 
  clkcycle = [ps|ns|us|ms]
      specifies time measurement for one cycle
*/
 
section sim
  /* verbose = 1 */
  debug = 0
  profile = 0
  prof_fn = "sim.profile"
 
  history = 1
  /* iprompt = 0 */
  exe_log = 1
  exe_log_fn = "executed.log"
  clkcycle = 4ns
end
 
 
/* SECTION VAPI
 
    This section configures Verification API, used for Advanced
    Core Verification.
 
    enabled = 0/1
        whether to start VAPI server
 
    server_port = 
        TCP/IP port to start VAPI server on
 
    log_enabled = 0/1
       whether logging of VAPI requests is enabled
 
    vapi_fn = 
       specifies filename where to log into, if log_enabled is selected
*/
 
section VAPI
  enabled = 0
  server_port = 9998
  log_enabled = 0
  vapi_log_fn = "vapi.log"
end
 
 
/* CPU SECTION
 
   This section specifies various CPU parameters.
 
   ver = 
   rev = 
      specifies version and revision of the CPU used
 
   upr = 
      changes the upr register
 
   superscalar = 0/1
      whether CPU is scalar or superscalar
      (modify cpu/or32/execute.c to tune superscalar model)
 
   hazards = 0/1
      whether data hazards are tracked in superscalar CPU
      and displayed by the simulator r command
 
   dependstats = 0/1
      whether inter-instruction dependencies are calculated
      and displayed by simulator stats command.
 
   slp = 0/1
      calculation of subroutine level parallelism. Displayed
      by simulator stats command.
 
   btic = 0/1
      enable branch target instruction cache model
 
   bpb = 0/1
      enable branch prediction buffer model
 
      parameters for CPU analysis
*/
 
section cpu
  ver = 0x1200
  rev = 0x0001
  /* upr = */
  superscalar = 0
  hazards = 0
  dependstats = 0
  slp = 0
  btic = 0
  bpb = 0
end
 
 
/* DEBUG SECTION
 
   This sections specifies how debug unit should behave.
 
   enabled = 0/1
      whether debug unit is enabled
 
   gdb_enabled = 0/1
      whether to start gdb server at 'server_port' port
 
   server_port = 
      TCP/IP port to start gdb server on, used only if gdb_enabled
      is set
 
section debug
  enabled = 0
  gdb_enabled = 0
  server_port = 9999
end
 
 
/* MC SECTION
 
   This section configures the memory controller
 
   enabled = 0/1
      whether memory controller is enabled
 
   baseaddr = 
      address of first MC register
 
   POC = 
      Power On Configuration register
*/
 
section mc
  enabled = 0
  baseaddr = 0xa0000000
  POC = 0x00000008                 /* Power on configuration register */
end
 
 
/* UART SECTION
 
   This section configures UARTs
 
   enabled = 0/1
      whether uarts are enabled
 
   nuarts = 
      make specified number of instances, configure each
      instance within device - enddevice construct.
 
   instance specific:
     baseaddr = 
        address of first UART register for this device
 
     rx_file = ""
        filename, where to read data from
 
     tx_file = ""
        filename, where to write data to
 
     irq = 
        irq number for this device
 
     16550 = 0/1
        0, if this device is uart 16450 and 1, if it is 16550
 
     jitter = 
        in msecs... time to block, -1 to disable it
 
     vapi_id = 
        VAPI id of this instance
*/
 
section uart
  enabled = 0
  nuarts = 1
 
  device 0
    baseaddr = 0x80000000
    irq = 2
    rxfile = "/tmp/uart0.rx"
    txfile = "/tmp/uart0.tx"
    jitter = -1                     /* async behaviour */
  enddevice
end
 
 
/* DMA SECTION
 
   This section configures DMAs
 
   enabled = 0/1
      whether DMAs are enabled
 
   ndmas = 
      make specified number of instances, configure each
      instance within device - enddevice construct.
 
   instance specific:
     baseaddr = 
        address of first DMA register for this device
 
     irq = 
        irq number for this device
 
     vapi_id = 
        VAPI id of this instance
*/
 
section dma
  enabled = 0
  ndmas = 1
 
  device 0
    baseaddr = 0x90000000
    irq = 4
  enddevice
end
 
 
/* ETHERNET SECTION
 
   This section configures ethernets
 
   enabled = 0/1
      whether ethernets are enabled
 
   nethernets = 
      make specified number of instances, configure each
      instance within device - enddevice construct.
 
   instance specific:
     baseaddr = 
        address of first ethernet register for this device
 
     dma = 
        which controller is this ethernet "connected" to
 
     rx_channel = 
        DMA channel used for RX
 
     tx_channel = 
        DMA channel used for TX
 
     rx_file = ""
        filename, where to read data from
 
     tx_file = ""
        filename, where to write data to
 
     vapi_id = 
        VAPI id of this instance
*/
 
section ethernet
  enabled = 0
  nethernets = 1
 
  device 0
    baseaddr = 0x88000000
    dma = 0
    tx_channel = 0
    rx_channel = 1
    rxfile = "/tmp/eth0.rx"
    txfile = "/tmp/eth0.tx"
  enddevice
end
 
/* TICK TIMER SECTION
 
    This section configures tick timer
 
    enabled = 0/1
      whether tick timer is enabled
 
    irq = 
      irq number
*/
 
section tick
  enabled = 0
  irq = 3
end

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[/] [or1k_old/] [trunk/] [orp/] [orp_soc/] [sw.old/] [sim.cfg] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	782	lampret	`/* sim.cfg -- Simulator configuration script file`
2			`Copyright (C) 2001, Marko Mlinar, markom@opencores.org`
3
4			`This file includes a lot of help about configurations and default one`
5
6			`This file is part of OpenRISC 1000 Architectural Simulator.`
7
8			`This program is free software; you can redistribute it and/or modify`
9			`it under the terms of the GNU General Public License as published by`
10			`the Free Software Foundation; either version 2 of the License, or`
11			`(at your option) any later version.`
12
13			`This program is distributed in the hope that it will be useful,`
14			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`GNU General Public License for more details.`
17
18			`You should have received a copy of the GNU General Public License`
19			`along with this program; if not, write to the Free Software`
20			`Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */`
21
22
23			`/* INTRODUCTION`
24
25			`The or1ksim have various parameters, which can be set in configuration`
26			`files. Multiple configurations may be used and switched between at`
27			`or1ksim startup.`
28			`By default, or1ksim loads condfiguration file from './sim.cfg' and if not`
29			`found it checks '~/.or1k/sim.cfg'. If even this file is not found or`
30			`all parameters are not defined, default configuration is used.`
31			`Users should not rely on default configuration, but rather redefine all`
32			`critical settings, since default configuration may differ in newer`
33			`versions of the or1ksim.`
34			`If multiple configurations are used, user can switch between them by`
35			`supplying -f option when starting simulator.`
36
37			`This file may contain (standard C) only comments - no // support.`
38
39			`Like normal configuration file, this file is divided in sections,`
40			`where each section is described in detail also.`
41
42			`Some section also have subsections. One example of such subsection is`
43			`block:`
44
45			`device`
46			`instance specific parameters...`
47			`enddevice`
48
49			`which creates a device instance.`
50			`*/`
51
52
53			`/* MEMORY SECTION`
54
55			`This section specifies how is initial memory generated and which blocks`
56			`it consist of.`
57
58			`type = random/unknown/pattern`
59			`specifies the initial memory values. 'random' parameter generate`
60			`random memory using seed 'random_seed' parameter. 'pattern' parameter`
61			`fills memory with 'pattern' parameter and 'unknown' does not specify`
62			`how memory should be generated - the fastest option.`
63
64			`random_seed =`
65			`random seed for randomizer, used if type = random`
66
67			`pattern =`
68			`pattern to fill memory, used if type = pattern`
69
70			`nmemories =`
71			`number of memory instances connected`
72
73			`instance specific:`
74			`baseaddr =`
75			`memory start address`
76
77			`size =`
78			`memory size`
79
80			`name = ""`
81			`memory block name`
82
83			`ce =`
84			`chip enable index of the memory instance`
85
86			`delayr =`
87			`cycles, required for read access, -1 if instance does not support reading`
88
89			`delayw =`
90			`cycles, required for write access, -1 if instance does not support writing`
91
92			`16550 = 0/1`
93			`0, if this device is uart 16450 and 1, if it is 16550`
94
95			`log = ""`
96			`filename, where to log memory accesses to, no log, if log command is not specified`
97			`*/`
98
99			`section memory`
100			`/*random_seed = 12345`
101			`type = random*/`
102			`pattern = 0x00`
103			`type = unknown /* Fastest */`
104
105			`nmemories = 3`
106			`device 0`
107			`name = "Flash"`
108			`ce = 0`
109			`baseaddr = 0x00000000`
110			`size = 0x00200000`
111			`delayr = 10`
112			`delayw = -1`
113			`enddevice`
114
115			`device 1`
116			`name = "RAM1"`
117			`ce = 1`
118			`baseaddr = 0x40000000`
119			`size = 0x00200000`
120			`delayr = 2`
121			`delayw = 4`
122			`enddevice`
123
124			`device 2`
125			`name = "RAM2"`
126			`ce = 2`
127			`baseaddr = 0x80000000`
128			`size = 0x00200000`
129			`delayr = 2`
130			`delayw = 4`
131			`enddevice`
132
133			`end`
134
135
136			`/* IMMU SECTION`
137
138			`This section configures Instruction Memory Menangement Unit`
139
140			`enabled = 0/1`
141			`whether IMMU is enabled`
142			`(NOTE: UPR bit is set)`
143
144			`nsets =`
145			`number of ITLB sets; must be power of two`
146
147			`nways =`
148			`number of ITLB ways`
149
150			`pagesize =`
151			`instruction page size; must be power of two`
152
153			`entrysize =`
154			`instruction entry size in bytes`
155
156			`ustates =`
157			`number of ITLB usage states (2, 3, 4 etc., max is 4)`
158			`*/`
159
160			`section immu`
161			`enabled = 0`
162			`nsets = 32`
163			`nways = 1`
164			`pagesize = 8192`
165			`end`
166
167
168			`/* DMMU SECTION`
169
170			`This section configures Data Memory Menangement Unit`
171
172			`enabled = 0/1`
173			`whether DMMU is enabled`
174			`(NOTE: UPR bit is set)`
175
176			`nsets =`
177			`number of DTLB sets; must be power of two`
178
179			`nways =`
180			`number of DTLB ways`
181
182			`pagesize =`
183			`data page size; must be power of two`
184
185			`entrysize =`
186			`data entry size in bytes`
187
188			`ustates =`
189			`number of DTLB usage states (2, 3, 4 etc., max is 4)`
190			`*/`
191
192			`section dmmu`
193			`enabled = 0`
194			`nsets = 32`
195			`nways = 1`
196			`pagesize = 8192`
197			`end`
198
199
200			`/* IC SECTION`
201
202			`This section configures Instruction Cache`
203
204			`enabled = 0/1`
205			`whether IC is enabled`
206			`(NOTE: UPR bit is set)`
207
208			`nsets =`
209			`number of IC sets; must be power of two`
210
211			`nways =`
212			`number of IC ways`
213
214			`blocksize =`
215			`IC block size in bytes; must be power of two`
216
217			`ustates =`
218			`number of IC usage states (2, 3, 4 etc., max is 4)`
219			`*/`
220
221			`section ic`
222			`enabled = 0`
223			`nsets = 512`
224			`nways = 1`
225			`blocksize = 16`
226			`end`
227
228
229			`/* DC SECTION`
230
231			`This section configures Data Cache`
232
233			`enabled = 0/1`
234			`whether DC is enabled`
235			`(NOTE: UPR bit is set)`
236
237			`nsets =`
238			`number of DC sets; must be power of two`
239
240			`nways =`
241			`number of DC ways`
242
243			`blocksize =`
244			`DC block size in bytes; must be power of two`
245
246			`ustates =`
247			`number of DC usage states (2, 3, 4 etc., max is 4)`
248			`*/`
249
250			`section dc`
251			`enabled = 0`
252			`nsets = 512`
253			`nways = 1`
254			`blocksize = 16`
255			`end`
256
257			`/* SIM SECTION`
258
259			`This section specifies how should sim behave.`
260
261			`verbose = 0/1`
262			`whether to print out extra messages`
263
264			`debug = 0-9`
265			`= 0 disabled debug messages`
266			`1-9 level of sim debug information, greater the number more verbose is`
267			`the output`
268
269			`profile = 0/1`
270			`whether to generate profiling file 'sim.profile'`
271
272			`prof_fn = ""`
273			`filename, where to generate profiling info, used`
274			`only if 'profile' is set`
275
276			`history = 0/1`
277			`whether instruction execution flow is tracked for`
278			`display by simulator hist command. Useful for`
279			`back-trace debugging.`
280
281			`iprompt = 0/1`
282			`whether we strart in interactive prompt`
283
284			`exe_log = 0/1`
285			`whether execution log should be generated`
286
287			`exe_log_fn = ""`
288			`where to put execution log in, used only if 'exe_log'`
289			`is set`
290
291			`clkcycle = [ps\|ns\|us\|ms]`
292			`specifies time measurement for one cycle`
293			`*/`
294
295			`section sim`
296			`/* verbose = 1 */`
297			`debug = 0`
298			`profile = 0`
299			`prof_fn = "sim.profile"`
300
301			`history = 1`
302			`/* iprompt = 0 */`
303			`exe_log = 1`
304			`exe_log_fn = "executed.log"`
305			`clkcycle = 4ns`
306			`end`
307
308
309			`/* SECTION VAPI`
310
311			`This section configures Verification API, used for Advanced`
312			`Core Verification.`
313
314			`enabled = 0/1`
315			`whether to start VAPI server`
316
317			`server_port =`
318			`TCP/IP port to start VAPI server on`
319
320			`log_enabled = 0/1`
321			`whether logging of VAPI requests is enabled`
322
323			`vapi_fn =`
324			`specifies filename where to log into, if log_enabled is selected`
325			`*/`
326
327			`section VAPI`
328			`enabled = 0`
329			`server_port = 9998`
330			`log_enabled = 0`
331			`vapi_log_fn = "vapi.log"`
332			`end`
333
334
335			`/* CPU SECTION`
336
337			`This section specifies various CPU parameters.`
338
339			`ver =`
340			`rev =`
341			`specifies version and revision of the CPU used`
342
343			`upr =`
344			`changes the upr register`
345
346			`superscalar = 0/1`
347			`whether CPU is scalar or superscalar`
348			`(modify cpu/or32/execute.c to tune superscalar model)`
349
350			`hazards = 0/1`
351			`whether data hazards are tracked in superscalar CPU`
352			`and displayed by the simulator r command`
353
354			`dependstats = 0/1`
355			`whether inter-instruction dependencies are calculated`
356			`and displayed by simulator stats command.`
357
358			`slp = 0/1`
359			`calculation of subroutine level parallelism. Displayed`
360			`by simulator stats command.`
361
362			`btic = 0/1`
363			`enable branch target instruction cache model`
364
365			`bpb = 0/1`
366			`enable branch prediction buffer model`
367
368			`parameters for CPU analysis`
369			`*/`
370
371			`section cpu`
372			`ver = 0x1200`
373			`rev = 0x0001`
374			`/* upr = */`
375			`superscalar = 0`
376			`hazards = 0`
377			`dependstats = 0`
378			`slp = 0`
379			`btic = 0`
380			`bpb = 0`
381			`end`
382
383
384			`/* DEBUG SECTION`
385
386			`This sections specifies how debug unit should behave.`
387
388			`enabled = 0/1`
389			`whether debug unit is enabled`
390
391			`gdb_enabled = 0/1`
392			`whether to start gdb server at 'server_port' port`
393
394			`server_port =`
395			`TCP/IP port to start gdb server on, used only if gdb_enabled`
396			`is set`
397
398			`section debug`
399			`enabled = 0`
400			`gdb_enabled = 0`
401			`server_port = 9999`
402			`end`
403
404
405			`/* MC SECTION`
406
407			`This section configures the memory controller`
408
409			`enabled = 0/1`
410			`whether memory controller is enabled`
411
412			`baseaddr =`
413			`address of first MC register`
414
415			`POC =`
416			`Power On Configuration register`
417			`*/`
418
419			`section mc`
420			`enabled = 0`
421			`baseaddr = 0xa0000000`
422			`POC = 0x00000008 /* Power on configuration register */`
423			`end`
424
425
426			`/* UART SECTION`
427
428			`This section configures UARTs`
429
430			`enabled = 0/1`
431			`whether uarts are enabled`
432
433			`nuarts =`
434			`make specified number of instances, configure each`
435			`instance within device - enddevice construct.`
436
437			`instance specific:`
438			`baseaddr =`
439			`address of first UART register for this device`
440
441			`rx_file = ""`
442			`filename, where to read data from`
443
444			`tx_file = ""`
445			`filename, where to write data to`
446
447			`irq =`
448			`irq number for this device`
449
450			`16550 = 0/1`
451			`0, if this device is uart 16450 and 1, if it is 16550`
452
453			`jitter =`
454			`in msecs... time to block, -1 to disable it`
455
456			`vapi_id =`
457			`VAPI id of this instance`
458			`*/`
459
460			`section uart`
461			`enabled = 0`
462			`nuarts = 1`
463
464			`device 0`
465			`baseaddr = 0x80000000`
466			`irq = 2`
467			`rxfile = "/tmp/uart0.rx"`
468			`txfile = "/tmp/uart0.tx"`
469			`jitter = -1 /* async behaviour */`
470			`enddevice`
471			`end`
472
473
474			`/* DMA SECTION`
475
476			`This section configures DMAs`
477
478			`enabled = 0/1`
479			`whether DMAs are enabled`
480
481			`ndmas =`
482			`make specified number of instances, configure each`
483			`instance within device - enddevice construct.`
484
485			`instance specific:`
486			`baseaddr =`
487			`address of first DMA register for this device`
488
489			`irq =`
490			`irq number for this device`
491
492			`vapi_id =`
493			`VAPI id of this instance`
494			`*/`
495
496			`section dma`
497			`enabled = 0`
498			`ndmas = 1`
499
500			`device 0`
501			`baseaddr = 0x90000000`
502			`irq = 4`
503			`enddevice`
504			`end`
505
506
507			`/* ETHERNET SECTION`
508
509			`This section configures ethernets`
510
511			`enabled = 0/1`
512			`whether ethernets are enabled`
513
514			`nethernets =`
515			`make specified number of instances, configure each`
516			`instance within device - enddevice construct.`
517
518			`instance specific:`
519			`baseaddr =`
520			`address of first ethernet register for this device`
521
522			`dma =`
523			`which controller is this ethernet "connected" to`
524
525			`rx_channel =`
526			`DMA channel used for RX`
527
528			`tx_channel =`
529			`DMA channel used for TX`
530
531			`rx_file = ""`
532			`filename, where to read data from`
533
534			`tx_file = ""`
535			`filename, where to write data to`
536
537			`vapi_id =`
538			`VAPI id of this instance`
539			`*/`
540
541			`section ethernet`
542			`enabled = 0`
543			`nethernets = 1`
544
545			`device 0`
546			`baseaddr = 0x88000000`
547			`dma = 0`
548			`tx_channel = 0`
549			`rx_channel = 1`
550			`rxfile = "/tmp/eth0.rx"`
551			`txfile = "/tmp/eth0.tx"`
552			`enddevice`
553			`end`
554
555			`/* TICK TIMER SECTION`
556
557			`This section configures tick timer`
558
559			`enabled = 0/1`
560			`whether tick timer is enabled`
561
562			`irq =`
563			`irq number`
564			`*/`
565
566			`section tick`
567			`enabled = 0`
568			`irq = 3`
569			`end`