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[/] [or1k_old/] [trunk/] [orpmon/] [reset.S] - Blame information for rev 1000

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Line No. Rev Author Line
1 809 simons 
#include "spr_defs.h"
2 
#include "board.h"
3 
#include "mc.h"
4 
 
5 
 
6 
 
7 
        .extern _reset_support
8 
        .extern _eth_int
9 
        .extern _src_beg
10 
        .extern _dst_beg
11 
        .extern _dst_end
12 
        .extern _c_reset
13 
        .extern _int_main
14 833 simons 
        .extern _tick_interrupt
15 820 markom 
        .extern _crc32
16 816 markom 
 
17 
        /* Used by global.src_addr for default value */
18 
        .extern _src_addr
19 809 simons 
 
20 817 simons 
        .global _align
21 820 markom 
        .global _calc_mycrc32
22 822 markom 
        .global _mycrc32
23 
        .global _mysize
24 809 simons 
 
25 817 simons 
        .section .stack, "aw", @nobits
26 
.space  STACK_SIZE
27 809 simons 
_stack:
28 834 simons 
        .section .crc
29 820 markom 
_mycrc32:
30 833 simons 
        .word   0xcccccccc
31 820 markom 
_mysize:
32 
        .word 0xdddddddd
33 809 simons 
 
34 829 markom 
.if SELF_CHECK
35 820 markom 
_calc_mycrc32:
36 833 simons 
        l.addi  r3,r0,0
37 820 markom 
        l.movhi r4,hi(_calc_mycrc32)
38 
        l.ori   r4,r4,lo(_calc_mycrc32)
39 
        l.movhi r5,hi(_mysize)
40 
        l.ori   r5,r5,lo(_mysize)
41 
        l.lwz   r5,0(r5)
42 822 markom 
        l.addi  r1,r1,-4
43 833 simons 
        l.sw    0(r1),r9
44 820 markom 
 
45 
        /* unsigned long crc32 (unsigned long crc, const unsigned char *buf, unsigned long len); */
46 833 simons 
        l.jal           _crc32
47 
        l.nop
48 
 
49 
        l.movhi r3,hi(_mycrc32)
50 820 markom 
        l.ori   r3,r3,lo(_mycrc32)
51 
        l.lwz   r3,0(r3)
52 
 
53 833 simons 
        l.xor     r11,r3,r11
54 822 markom 
        l.lwz   r9,0(r1)
55 
        l.jr    r9
56 
        l.addi  r1,r1,4
57 829 markom 
.endif
58 
 
59 833 simons 
        .org 0x100
60 809 simons 
.if IN_FLASH
61 
        .section .reset, "ax"
62 
.else
63 817 simons 
        .section .vectors, "ax"
64 809 simons 
.endif
65 
 
66 
_reset:
67 
.if IN_FLASH
68 817 simons 
        l.movhi r3,hi(MC_BASE_ADDR)
69 809 simons 
        l.ori   r3,r3,MC_BA_MASK
70 
        l.addi  r5,r0,0x00
71 
        l.sw    0(r3),r5
72 
.endif
73 1000 simons 
        l.addi  r3,r0,SPR_SR_SM
74 
        l.mtspr r0,r3,SPR_SR
75 833 simons 
        l.movhi r3,hi(_start)
76 
        l.ori   r3,r3,lo(_start)
77 829 markom 
        l.jr    r3
78 833 simons 
        l.nop
79 809 simons 
 
80 
.if IN_FLASH
81 
        .section .vectors, "ax"
82 833 simons 
        .org 0x500
83 
.else
84 
        .org (0x500 - 0x100 + _reset)
85 
.endif
86 
 
87 987 simons 
        l.addi  r1,r1,-128
88 
        l.sw    0x4(r1),r2
89 
        l.movhi r2,hi(_tick)
90 
        l.ori   r2,r2,lo(_tick)
91 
        l.jr    r2
92 833 simons 
        l.nop
93 
 
94 
.if IN_FLASH
95 
        .section .vectors, "ax"
96 824 markom 
        .org 0x600
97 
.else
98 
        .org (0x600 - 0x100 + _reset)
99 809 simons 
.endif
100 
 
101 987 simons 
        l.addi  r1,r1,-128
102 
        l.sw    0x08(r1),r2
103 
        l.movhi r2,hi(_align)
104 
        l.ori   r2,r2,lo(_align)
105 
        l.jr    r2
106 817 simons 
        l.nop
107 
 
108 824 markom 
.if IN_FLASH
109 817 simons 
        .org 0x800
110 824 markom 
.else
111 
        .org (0x800 - 0x100 + _reset)
112 
.endif
113 817 simons 
 
114 987 simons 
        l.addi  r1,r1,-128
115 
        l.sw    0x4(r1),r2
116 
        l.movhi r2,hi(_int_wrapper)
117 
        l.ori   r2,r2,lo(_int_wrapper)
118 
        l.jr    r2
119 809 simons 
        l.nop
120 
 
121 
        .section .text
122 833 simons 
_start:
123 809 simons 
.if IN_FLASH
124 
        l.jal   _init_mc
125 
        l.nop
126 
 
127 
        /* Wait for SDRAM */
128 833 simons 
        l.addi  r3,r0,0x1000
129 809 simons 
1:      l.sfeqi r3,0
130 
        l.bnf   1b
131 
        l.addi  r3,r3,-1
132 
.endif
133 817 simons 
        /* Copy form flash to sram */
134 809 simons 
.if IN_FLASH
135 
        l.movhi r3,hi(_src_beg)
136 
        l.ori   r3,r3,lo(_src_beg)
137 
        l.movhi r4,hi(_vec_start)
138 
        l.ori   r4,r4,lo(_vec_start)
139 
        l.movhi r5,hi(_vec_end)
140 
        l.ori   r5,r5,lo(_vec_end)
141 
        l.sub   r5,r5,r4
142 
        l.sfeqi r5,0
143 
        l.bf    2f
144 
        l.nop
145 
1:      l.lwz   r6,0(r3)
146 
        l.sw    0(r4),r6
147 
        l.addi  r3,r3,4
148 
        l.addi  r4,r4,4
149 
        l.addi  r5,r5,-4
150 
        l.sfgtsi r5,0
151 817 simons 
        l.bf    1b
152 809 simons 
        l.nop
153 
2:
154 
        l.movhi r4,hi(_dst_beg)
155 
        l.ori   r4,r4,lo(_dst_beg)
156 
        l.movhi r5,hi(_dst_end)
157 
        l.ori   r5,r5,lo(_dst_end)
158 
1:      l.sfgeu r4,r5
159 
        l.bf    1f
160 
        l.nop
161 
        l.lwz   r8,0(r3)
162 
        l.sw    0(r4),r8
163 
        l.addi  r3,r3,4
164 
        l.bnf   1b
165 
        l.addi  r4,r4,4
166 
1:
167 
        l.addi  r3,r0,0
168 
        l.addi  r4,r0,0
169 
3:
170 
.endif
171 
 
172 
.if IC_ENABLE
173 833 simons 
        l.jal   _ic_enable
174 
        l.nop
175 809 simons 
.endif
176 
 
177 
.if DC_ENABLE
178 833 simons 
        l.jal   _dc_enable
179 
        l.nop
180 809 simons 
.endif
181 
 
182 
        l.movhi r1,hi(_stack-4)
183 858 markom 
        l.ori   r1,r1,lo(_stack-4)
184 833 simons 
        l.addi  r2,r0,-3
185 
        l.and   r1,r1,r2
186 809 simons 
 
187 
        l.movhi r2,hi(_main)
188 
        l.ori   r2,r2,lo(_main)
189 
        l.jr    r2
190 
        l.addi  r2,r0,0
191 
 
192 
_ic_enable:
193 
 
194 
        /* Flush IC */
195 
        l.addi  r10,r0,0
196 
        l.addi  r11,r0,IC_SIZE
197 
1:
198 
        l.mtspr r0,r10,SPR_ICBIR
199 
        l.sfne  r10,r11
200 
        l.bf    1b
201 
        l.addi  r10,r10,16
202 
 
203 
        /* Enable IC */
204 1000 simons 
        l.mfspr r10,r0,SPR_SR
205 
        l.ori   r10,r10,(SPR_SR_ICE|SPR_SR_SM)
206 809 simons 
        l.mtspr r0,r10,SPR_SR
207 
        l.nop
208 
        l.nop
209 
        l.nop
210 
        l.nop
211 
        l.nop
212 
 
213 833 simons 
        l.jr    r9
214 
        l.nop
215 809 simons 
 
216 
_dc_enable:
217 
 
218 
        /* Flush DC */
219 
        l.addi  r10,r0,0
220 
        l.addi  r11,r0,DC_SIZE
221 
1:
222 
        l.mtspr r0,r10,SPR_DCBIR
223 
        l.sfne  r10,r11
224 
        l.bf    1b
225 
        l.addi  r10,r10,16
226 
 
227 
        /* Enable DC */
228 1000 simons 
        l.mfspr r10,r0,SPR_SR
229 
        l.ori   r10,r10,(SPR_SR_DCE|SPR_SR_SM)
230 809 simons 
        l.mtspr r0,r10,SPR_SR
231 
 
232 833 simons 
        l.jr    r9
233 
        l.nop
234 809 simons 
 
235 
.if IN_FLASH
236 
_init_mc:
237 
 
238 817 simons 
        l.movhi r3,hi(MC_BASE_ADDR)
239 
        l.ori   r3,r3,lo(MC_BASE_ADDR)
240 809 simons 
 
241 
        l.addi  r4,r3,MC_CSC(0)
242 817 simons 
        l.movhi r5,hi(FLASH_BASE_ADDR)
243 987 simons 
        l.srai  r5,r5,6
244 809 simons 
        l.ori   r5,r5,0x0025
245 
        l.sw    0(r4),r5
246 
 
247 
        l.addi  r4,r3,MC_TMS(0)
248 
        l.movhi r5,hi(FLASH_TMS_VAL)
249 
        l.ori   r5,r5,lo(FLASH_TMS_VAL)
250 
        l.sw    0(r4),r5
251 
 
252 
        l.addi  r4,r3,MC_BA_MASK
253 
        l.addi  r5,r0,MC_MASK_VAL
254 
        l.sw    0(r4),r5
255 
 
256 
        l.addi  r4,r3,MC_CSR
257 
        l.movhi r5,hi(MC_CSR_VAL)
258 
        l.ori   r5,r5,lo(MC_CSR_VAL)
259 
        l.sw    0(r4),r5
260 
 
261 
        l.addi  r4,r3,MC_TMS(1)
262 
        l.movhi r5,hi(SDRAM_TMS_VAL)
263 
        l.ori   r5,r5,lo(SDRAM_TMS_VAL)
264 
        l.sw    0(r4),r5
265 
 
266 
        l.addi  r4,r3,MC_CSC(1)
267 817 simons 
        l.movhi r5,hi(SDRAM_BASE_ADDR)
268 987 simons 
        l.srai  r5,r5,6
269 809 simons 
        l.ori   r5,r5,0x0411
270 
        l.sw    0(r4),r5
271 
 
272 833 simons 
#ifdef ETH_DATA_BASE
273 
        l.addi  r4,r3,MC_CSC(2)
274 
        l.movhi r5,hi(ETH_DATA_BASE)
275 987 simons 
        l.srai  r5,r5,6
276 833 simons 
        l.ori   r5,r5,0x0005
277 
        l.sw    0(r4),r5
278 
 
279 
        l.addi  r4,r3,MC_TMS(2)
280 
        l.movhi r5,0xffff
281 
        l.ori   r5,r5,0xffff
282 
        l.sw    0(r4),r5
283 
#endif
284 
 
285 809 simons 
        l.jr    r9
286 
        l.nop
287 
.endif
288 
 
289 833 simons 
_tick:
290 
        l.sw    0x8(r1),r4
291 
        l.sw    0xc(r1),r5
292 
        l.sw    0x10(r1),r6
293 
        l.sw    0x14(r1),r7
294 
        l.sw    0x18(r1),r8
295 
        l.sw    0x1c(r1),r9
296 
        l.sw    0x20(r1),r10
297 
        l.sw    0x24(r1),r11
298 
        l.sw    0x28(r1),r12
299 
        l.sw    0x2c(r1),r13
300 
        l.sw    0x30(r1),r14
301 
        l.sw    0x34(r1),r15
302 
        l.sw    0x38(r1),r16
303 
        l.sw    0x3c(r1),r17
304 
        l.sw    0x40(r1),r18
305 
        l.sw    0x44(r1),r19
306 
        l.sw    0x48(r1),r20
307 
        l.sw    0x4c(r1),r21
308 
        l.sw    0x50(r1),r22
309 
        l.sw    0x54(r1),r23
310 
        l.sw    0x58(r1),r24
311 
        l.sw    0x5c(r1),r25
312 
        l.sw    0x60(r1),r26
313 
        l.sw    0x64(r1),r27
314 
        l.sw    0x68(r1),r28
315 
        l.sw    0x6c(r1),r29
316 
        l.sw    0x70(r1),r30
317 
        l.sw    0x74(r1),r31
318 
        l.sw    0x78(r1),r3
319 
 
320 
        l.movhi r3,hi(_tick_interrupt)
321 
        l.ori   r3,r3,lo(_tick_interrupt)
322 
        l.jalr  r3
323 
        l.nop
324 
 
325 
        l.lwz   r2,0x4(r1)
326 
        l.lwz   r4,0x8(r1)
327 
        l.lwz   r5,0xc(r1)
328 
        l.lwz   r6,0x10(r1)
329 
        l.lwz   r7,0x14(r1)
330 
        l.lwz   r8,0x18(r1)
331 
        l.lwz   r9,0x1c(r1)
332 
        l.lwz   r10,0x20(r1)
333 
        l.lwz   r11,0x24(r1)
334 
        l.lwz   r12,0x28(r1)
335 
        l.lwz   r13,0x2c(r1)
336 
        l.lwz   r14,0x30(r1)
337 
        l.lwz   r15,0x34(r1)
338 
        l.lwz   r16,0x38(r1)
339 
        l.lwz   r17,0x3c(r1)
340 
        l.lwz   r18,0x40(r1)
341 
        l.lwz   r19,0x44(r1)
342 
        l.lwz   r20,0x48(r1)
343 
        l.lwz   r21,0x4c(r1)
344 
        l.lwz   r22,0x50(r1)
345 
        l.lwz   r23,0x54(r1)
346 
        l.lwz   r24,0x58(r1)
347 
        l.lwz   r25,0x5c(r1)
348 
        l.lwz   r26,0x60(r1)
349 
        l.lwz   r27,0x64(r1)
350 
        l.lwz   r28,0x68(r1)
351 
        l.lwz   r29,0x6c(r1)
352 
        l.lwz   r30,0x70(r1)
353 
        l.mfspr r31,r0,0x40
354 
        l.lwz   r31,0x74(r1)
355 
        l.lwz   r3,0x78(r1)
356 
 
357 
        l.addi  r1,r1,128
358 
        l.rfe
359 
        l.nop
360 
 
361 809 simons 
_int_wrapper:
362 
        l.sw    0x8(r1),r4
363 
        l.sw    0xc(r1),r5
364 
        l.sw    0x10(r1),r6
365 
        l.sw    0x14(r1),r7
366 
        l.sw    0x18(r1),r8
367 
        l.sw    0x1c(r1),r9
368 
        l.sw    0x20(r1),r10
369 
        l.sw    0x24(r1),r11
370 
        l.sw    0x28(r1),r12
371 
        l.sw    0x2c(r1),r13
372 
        l.sw    0x30(r1),r14
373 
        l.sw    0x34(r1),r15
374 
        l.sw    0x38(r1),r16
375 
        l.sw    0x3c(r1),r17
376 
        l.sw    0x40(r1),r18
377 
        l.sw    0x44(r1),r19
378 
        l.sw    0x48(r1),r20
379 
        l.sw    0x4c(r1),r21
380 
        l.sw    0x50(r1),r22
381 
        l.sw    0x54(r1),r23
382 
        l.sw    0x58(r1),r24
383 
        l.sw    0x5c(r1),r25
384 
        l.sw    0x60(r1),r26
385 
        l.sw    0x64(r1),r27
386 
        l.sw    0x68(r1),r28
387 
        l.sw    0x6c(r1),r29
388 
        l.sw    0x70(r1),r30
389 
        l.sw    0x74(r1),r31
390 
        l.sw    0x78(r1),r3
391 
 
392 855 markom 
        l.movhi r3,hi(_int_main)
393 
        l.ori   r3,r3,lo(_int_main)
394 809 simons 
        l.jalr  r3
395 
        l.nop
396 
 
397 
        l.lwz   r2,0x4(r1)
398 
        l.lwz   r4,0x8(r1)
399 
        l.lwz   r5,0xc(r1)
400 
        l.lwz   r6,0x10(r1)
401 
        l.lwz   r7,0x14(r1)
402 
        l.lwz   r8,0x18(r1)
403 
        l.lwz   r9,0x1c(r1)
404 
        l.lwz   r10,0x20(r1)
405 
        l.lwz   r11,0x24(r1)
406 
        l.lwz   r12,0x28(r1)
407 
        l.lwz   r13,0x2c(r1)
408 
        l.lwz   r14,0x30(r1)
409 
        l.lwz   r15,0x34(r1)
410 
        l.lwz   r16,0x38(r1)
411 
        l.lwz   r17,0x3c(r1)
412 
        l.lwz   r18,0x40(r1)
413 
        l.lwz   r19,0x44(r1)
414 
        l.lwz   r20,0x48(r1)
415 
        l.lwz   r21,0x4c(r1)
416 
        l.lwz   r22,0x50(r1)
417 
        l.lwz   r23,0x54(r1)
418 
        l.lwz   r24,0x58(r1)
419 
        l.lwz   r25,0x5c(r1)
420 
        l.lwz   r26,0x60(r1)
421 
        l.lwz   r27,0x64(r1)
422 
        l.lwz   r28,0x68(r1)
423 
        l.lwz   r29,0x6c(r1)
424 
        l.lwz   r30,0x70(r1)
425 
        l.lwz   r31,0x74(r1)
426 833 simons 
        l.lwz   r3,0x78(r1)
427 809 simons 
 
428 
        l.mtspr r0,r0,SPR_PICSR
429 
 
430 
        l.addi  r1,r1,128
431 
        l.rfe
432 
        l.nop
433 
 
434 817 simons 
_align:
435 
        l.sw    0x0c(r1),r3
436 
        l.sw    0x10(r1),r4
437 
        l.sw    0x14(r1),r5
438 
        l.sw    0x18(r1),r6
439 
        l.sw    0x1c(r1),r7
440 
        l.sw    0x20(r1),r8
441 
        l.sw    0x24(r1),r9
442 
        l.sw    0x28(r1),r10
443 
        l.sw    0x2c(r1),r11
444 
        l.sw    0x30(r1),r12
445 
        l.sw    0x34(r1),r13
446 
        l.sw    0x38(r1),r14
447 
        l.sw    0x3c(r1),r15
448 
        l.sw    0x40(r1),r16
449 
        l.sw    0x44(r1),r17
450 
        l.sw    0x48(r1),r18
451 
        l.sw    0x4c(r1),r19
452 
        l.sw    0x50(r1),r20
453 
        l.sw    0x54(r1),r21
454 
        l.sw    0x58(r1),r22
455 
        l.sw    0x5c(r1),r23
456 
        l.sw    0x60(r1),r24
457 
        l.sw    0x64(r1),r25
458 
        l.sw    0x68(r1),r26
459 
        l.sw    0x6c(r1),r27
460 
        l.sw    0x70(r1),r28
461 
        l.sw    0x74(r1),r29
462 
        l.sw    0x78(r1),r30
463 
        l.sw    0x7c(r1),r31
464 
 
465 
        l.mfspr r2,r0,SPR_EEAR_BASE /* Load the efective addres */
466 
        l.mfspr r5,r0,SPR_EPCR_BASE /* Load the insn address */
467 
 
468 833 simons 
        l.lwz   r3,0(r5)    /* Load insn */
469 817 simons 
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
470 
 
471 
        l.sfeqi r4,0x00     /* Check if the load/store insn is in delay slot */
472 833 simons 
        l.bf    jmp
473 817 simons 
        l.sfeqi r4,0x01
474 833 simons 
        l.bf    jmp
475 817 simons 
        l.sfeqi r4,0x03
476 833 simons 
        l.bf    jmp
477 817 simons 
        l.sfeqi r4,0x04
478 833 simons 
        l.bf    jmp
479 817 simons 
        l.sfeqi r4,0x11
480 833 simons 
        l.bf    jr
481 817 simons 
        l.sfeqi r4,0x12
482 833 simons 
        l.bf    jr
483 817 simons 
        l.nop
484 833 simons 
        l.j     1f
485 817 simons 
        l.addi  r5,r5,4     /* Increment PC to get return insn address */
486 
 
487 
jmp:
488 
        l.slli  r4,r3,6     /* Get the signed extended jump length */
489 
        l.srai  r4,r4,4
490 
 
491 833 simons 
        l.lwz   r3,4(r5)      /* Load the real load/store insn */
492 817 simons 
 
493 833 simons 
        l.add   r5,r5,r4      /* Calculate jump target address */
494 817 simons 
 
495 833 simons 
        l.j     1f
496 817 simons 
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
497 
 
498 
jr:
499 
        l.slli  r4,r3,9     /* Shift to get the reg nb */
500 
        l.andi  r4,r4,0x7c
501 
 
502 833 simons 
        l.lwz   r3,4(r5)    /* Load the real load/store insn */
503 817 simons 
 
504 833 simons 
        l.add   r4,r4,r1    /* Load the jump register value from the stack */
505 
        l.lwz   r5,0(r4)
506 817 simons 
 
507 
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
508 
 
509 
 
510 
1:      l.mtspr r0,r5,SPR_EPCR_BASE
511 
 
512 
        l.sfeqi r4,0x26
513 833 simons 
        l.bf    lhs
514 817 simons 
        l.sfeqi r4,0x25
515 833 simons 
        l.bf    lhz
516 817 simons 
        l.sfeqi r4,0x22
517 833 simons 
        l.bf    lws
518 817 simons 
        l.sfeqi r4,0x21
519 833 simons 
        l.bf    lwz
520 817 simons 
        l.sfeqi r4,0x37
521 833 simons 
        l.bf    sh
522 817 simons 
        l.sfeqi r4,0x35
523 833 simons 
        l.bf    sw
524 817 simons 
        l.nop
525 
 
526 833 simons 
1:      l.j     1b      /* I don't know what to do */
527 817 simons 
        l.nop
528 
 
529 833 simons 
lhs:    l.lbs   r5,0(r2)
530 817 simons 
        l.slli  r5,r5,8
531 833 simons 
        l.lbz   r6,1(r2)
532 
        l.or    r5,r5,r6
533 817 simons 
        l.srli  r4,r3,19
534 
        l.andi  r4,r4,0x7c
535 833 simons 
        l.add   r4,r4,r1
536 
        l.j     align_end
537 
        l.sw    0(r4),r5
538 817 simons 
 
539 833 simons 
lhz:    l.lbz   r5,0(r2)
540 817 simons 
        l.slli  r5,r5,8
541 833 simons 
        l.lbz   r6,1(r2)
542 
        l.or    r5,r5,r6
543 817 simons 
        l.srli  r4,r3,19
544 
        l.andi  r4,r4,0x7c
545 833 simons 
        l.add   r4,r4,r1
546 
        l.j     align_end
547 
        l.sw    0(r4),r5
548 817 simons 
 
549 833 simons 
lws:    l.lbs   r5,0(r2)
550 817 simons 
        l.slli  r5,r5,24
551 833 simons 
        l.lbz   r6,1(r2)
552 817 simons 
        l.slli  r6,r6,16
553 833 simons 
        l.or    r5,r5,r6
554 
        l.lbz   r6,2(r2)
555 817 simons 
        l.slli  r6,r6,8
556 833 simons 
        l.or    r5,r5,r6
557 
        l.lbz   r6,3(r2)
558 
        l.or    r5,r5,r6
559 817 simons 
        l.srli  r4,r3,19
560 
        l.andi  r4,r4,0x7c
561 833 simons 
        l.add   r4,r4,r1
562 
        l.j     align_end
563 
        l.sw    0(r4),r5
564 817 simons 
 
565 833 simons 
lwz:    l.lbz   r5,0(r2)
566 817 simons 
        l.slli  r5,r5,24
567 833 simons 
        l.lbz   r6,1(r2)
568 817 simons 
        l.slli  r6,r6,16
569 833 simons 
        l.or    r5,r5,r6
570 
        l.lbz   r6,2(r2)
571 817 simons 
        l.slli  r6,r6,8
572 833 simons 
        l.or    r5,r5,r6
573 
        l.lbz   r6,3(r2)
574 
        l.or    r5,r5,r6
575 817 simons 
        l.srli  r4,r3,19
576 
        l.andi  r4,r4,0x7c
577 833 simons 
        l.add   r4,r4,r1
578 
        l.j     align_end
579 
        l.sw    0(r4),r5
580 817 simons 
 
581 
sh:
582 
        l.srli  r4,r3,9
583 
        l.andi  r4,r4,0x7c
584 833 simons 
        l.add   r4,r4,r1
585 
        l.lwz   r5,0(r4)
586 
        l.sb    1(r2),r5
587 
        l.srli  r5,r5,8
588 
        l.j     align_end
589 
        l.sb    0(r2),r5
590 817 simons 
 
591 
sw:
592 
        l.srli  r4,r3,9
593 
        l.andi  r4,r4,0x7c
594 833 simons 
        l.add   r4,r4,r1
595 
        l.lwz   r5,0(r4)
596 
        l.sb    3(r2),r5
597 
        l.srli  r5,r5,8
598 
        l.sb    2(r2),r5
599 
        l.srli  r5,r5,8
600 
        l.sb    1(r2),r5
601 
        l.srli  r5,r5,8
602 
        l.j     align_end
603 
        l.sb    0(r2),r5
604 817 simons 
 
605 
align_end:
606 
        l.lwz   r2,0x08(r1)
607 
        l.lwz   r3,0x0c(r1)
608 
        l.lwz   r4,0x10(r1)
609 
        l.lwz   r5,0x14(r1)
610 
        l.lwz   r6,0x18(r1)
611 
        l.lwz   r7,0x1c(r1)
612 
        l.lwz   r8,0x20(r1)
613 
        l.lwz   r9,0x24(r1)
614 
        l.lwz   r10,0x28(r1)
615 
        l.lwz   r11,0x2c(r1)
616 
        l.lwz   r12,0x30(r1)
617 
        l.lwz   r13,0x34(r1)
618 
        l.lwz   r14,0x38(r1)
619 
        l.lwz   r15,0x3c(r1)
620 
        l.lwz   r16,0x40(r1)
621 
        l.lwz   r17,0x44(r1)
622 
        l.lwz   r18,0x48(r1)
623 
        l.lwz   r19,0x4c(r1)
624 
        l.lwz   r20,0x50(r1)
625 
        l.lwz   r21,0x54(r1)
626 
        l.lwz   r22,0x58(r1)
627 
        l.lwz   r23,0x5c(r1)
628 
        l.lwz   r24,0x60(r1)
629 
        l.lwz   r25,0x64(r1)
630 
        l.lwz   r26,0x68(r1)
631 
        l.lwz   r27,0x6c(r1)
632 
        l.lwz   r28,0x70(r1)
633 
        l.lwz   r29,0x74(r1)
634 
        l.lwz   r30,0x78(r1)
635 833 simons 
        l.mfspr r31,r0,0x40
636 817 simons 
        l.lwz   r31,0x7c(r1)
637 
        l.addi  r1,r1,128
638 
        l.rfe

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