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[/] [or1k_old/] [trunk/] [orpmon/] [reset.S] - Blame information for rev 822

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1 809 simons 
#include "spr_defs.h"
2 
#include "board.h"
3 
#include "mc.h"
4 
 
5 
 
6 
 
7 
        .extern _reset_support
8 
        .extern _eth_int
9 
        .extern _src_beg
10 
        .extern _dst_beg
11 
        .extern _dst_end
12 
        .extern _c_reset
13 
        .extern _int_main
14 820 markom 
        .extern _crc32
15 816 markom 
 
16 
        /* Used by global.src_addr for default value */
17 
        .extern _src_addr
18 809 simons 
 
19 
        .global _lolev_ie
20 
        .global _lolev_idis
21 817 simons 
        .global _align
22 820 markom 
        .global _calc_mycrc32
23 822 markom 
        .global _mycrc32
24 
        .global _mysize
25 809 simons 
 
26 817 simons 
        .section .stack, "aw", @nobits
27 
.space  STACK_SIZE
28 809 simons 
_stack:
29 820 markom 
                                .section .crc
30 
_mycrc32:
31 
        .word   0xcccccccc
32 
_mysize:
33 
        .word 0xdddddddd
34 809 simons 
 
35 820 markom 
_calc_mycrc32:
36 
                                l.addi  r3,r0,0
37 
        l.movhi r4,hi(_calc_mycrc32)
38 
        l.ori   r4,r4,lo(_calc_mycrc32)
39 
        l.movhi r5,hi(_mysize)
40 
        l.ori   r5,r5,lo(_mysize)
41 
        l.lwz   r5,0(r5)
42 822 markom 
        l.addi  r1,r1,-4
43 
                                l.sw    0(r1),r9
44 820 markom 
 
45 
        /* unsigned long crc32 (unsigned long crc, const unsigned char *buf, unsigned long len); */
46 
                                l.jal           _crc32
47 
                                l.nop
48 
 
49 
                                l.movhi r3,hi(_mycrc32)
50 
        l.ori   r3,r3,lo(_mycrc32)
51 
        l.lwz   r3,0(r3)
52 
 
53 822 markom 
        l.xor     r11,r3,r11
54 
        l.lwz   r9,0(r1)
55 
        l.jr    r9
56 
        l.addi  r1,r1,4
57 
 
58 820 markom 
                                .org 0x100
59 
 
60 809 simons 
.if IN_FLASH
61 
        .section .reset, "ax"
62 
.else
63 817 simons 
        .section .vectors, "ax"
64 809 simons 
.endif
65 
 
66 
_reset:
67 
.if IN_FLASH
68 817 simons 
        l.movhi r3,hi(MC_BASE_ADDR)
69 809 simons 
        l.ori   r3,r3,MC_BA_MASK
70 
        l.addi  r5,r0,0x00
71 
        l.sw    0(r3),r5
72 
.endif
73 817 simons 
        l.movhi r3,hi(_start)
74 809 simons 
        l.ori   r3,r3,lo(_start)
75 
        l.jr    r3
76 
        l.nop
77 
 
78 
.if IN_FLASH
79 
        .section .vectors, "ax"
80 
.endif
81 817 simons 
        .org 0x600
82 809 simons 
 
83 817 simons 
        l.j     _align
84 
        l.nop
85 
 
86 
        .org 0x800
87 
 
88 809 simons 
        l.j     _int_wrapper
89 
        l.nop
90 
 
91 
        .section .text
92 822 markom 
        l.nop
93 809 simons 
_start:
94 
.if IN_FLASH
95 
        l.jal   _init_mc
96 
        l.nop
97 
 
98 
        /* Wait for SDRAM */
99 
        l.addi  r3,r0,0x0000  /* igor zmanjsal iz 0x7fff na 0x0000 */
100 
1:      l.sfeqi r3,0
101 
        l.bnf   1b
102 
        l.addi  r3,r3,-1
103 
.endif
104 817 simons 
        /* Copy form flash to sram */
105 809 simons 
.if IN_FLASH
106 
        l.movhi r3,hi(_src_beg)
107 
        l.ori   r3,r3,lo(_src_beg)
108 
        l.movhi r4,hi(_vec_start)
109 
        l.ori   r4,r4,lo(_vec_start)
110 
        l.movhi r5,hi(_vec_end)
111 
        l.ori   r5,r5,lo(_vec_end)
112 
        l.sub   r5,r5,r4
113 
        l.sfeqi r5,0
114 
        l.bf    2f
115 
        l.nop
116 
1:      l.lwz   r6,0(r3)
117 
        l.sw    0(r4),r6
118 
        l.addi  r3,r3,4
119 
        l.addi  r4,r4,4
120 
        l.addi  r5,r5,-4
121 
        l.sfgtsi r5,0
122 817 simons 
        l.bf    1b
123 809 simons 
        l.nop
124 
2:
125 
        l.movhi r4,hi(_dst_beg)
126 
        l.ori   r4,r4,lo(_dst_beg)
127 
        l.movhi r5,hi(_dst_end)
128 
        l.ori   r5,r5,lo(_dst_end)
129 
1:      l.sfgeu r4,r5
130 
        l.bf    1f
131 
        l.nop
132 
        l.lwz   r8,0(r3)
133 
        l.sw    0(r4),r8
134 
        l.addi  r3,r3,4
135 
        l.bnf   1b
136 
        l.addi  r4,r4,4
137 
1:
138 
        l.addi  r3,r0,0
139 
        l.addi  r4,r0,0
140 
3:
141 
.endif
142 
 
143 
.if IC_ENABLE
144 817 simons 
  l.jal _ic_enable
145 
  l.nop
146 809 simons 
.endif
147 
 
148 
.if DC_ENABLE
149 817 simons 
  l.jal _dc_enable
150 
  l.nop
151 809 simons 
.endif
152 
 
153 
        l.movhi r1,hi(_stack-4)
154 
        l.addi  r1,r1,lo(_stack-4)
155 817 simons 
  l.addi  r2,r0,-3
156 
  l.and r1,r1,r2
157 809 simons 
 
158 
        l.movhi r2,hi(_main)
159 
        l.ori   r2,r2,lo(_main)
160 
        l.jr    r2
161 
        l.addi  r2,r0,0
162 
 
163 
_ic_enable:
164 
 
165 
        /* Flush IC */
166 
        l.addi  r10,r0,0
167 
        l.addi  r11,r0,IC_SIZE
168 
1:
169 
        l.mtspr r0,r10,SPR_ICBIR
170 
        l.sfne  r10,r11
171 
        l.bf    1b
172 
        l.addi  r10,r10,16
173 
 
174 
        /* Enable IC */
175 
        l.addi  r10,r0,(SPR_SR_ICE|SPR_SR_SM)
176 
        l.mtspr r0,r10,SPR_SR
177 
        l.nop
178 
        l.nop
179 
        l.nop
180 
        l.nop
181 
        l.nop
182 
 
183 817 simons 
  l.jr  r9
184 
  l.nop
185 809 simons 
 
186 
_dc_enable:
187 
 
188 
        /* Flush DC */
189 
        l.addi  r10,r0,0
190 
        l.addi  r11,r0,DC_SIZE
191 
1:
192 
        l.mtspr r0,r10,SPR_DCBIR
193 
        l.sfne  r10,r11
194 
        l.bf    1b
195 
        l.addi  r10,r10,16
196 
 
197 
        /* Enable DC */
198 
        l.addi  r10,r0,(SPR_SR_DCE|SPR_SR_SM)
199 
        l.mtspr r0,r10,SPR_SR
200 
 
201 817 simons 
  l.jr  r9
202 
  l.nop
203 809 simons 
 
204 
.if IN_FLASH
205 
_init_mc:
206 
 
207 817 simons 
        l.movhi r3,hi(MC_BASE_ADDR)
208 
        l.ori   r3,r3,lo(MC_BASE_ADDR)
209 809 simons 
 
210 
        l.addi  r4,r3,MC_CSC(0)
211 817 simons 
        l.movhi r5,hi(FLASH_BASE_ADDR)
212 809 simons 
        l.srai  r5,r5,5
213 
        l.ori   r5,r5,0x0025
214 
        l.sw    0(r4),r5
215 
 
216 
        l.addi  r4,r3,MC_TMS(0)
217 
        l.movhi r5,hi(FLASH_TMS_VAL)
218 
        l.ori   r5,r5,lo(FLASH_TMS_VAL)
219 
        l.sw    0(r4),r5
220 
 
221 
        l.addi  r4,r3,MC_BA_MASK
222 
        l.addi  r5,r0,MC_MASK_VAL
223 
        l.sw    0(r4),r5
224 
 
225 
        l.addi  r4,r3,MC_CSR
226 
        l.movhi r5,hi(MC_CSR_VAL)
227 
        l.ori   r5,r5,lo(MC_CSR_VAL)
228 
        l.sw    0(r4),r5
229 
 
230 
        l.addi  r4,r3,MC_TMS(1)
231 
        l.movhi r5,hi(SDRAM_TMS_VAL)
232 
        l.ori   r5,r5,lo(SDRAM_TMS_VAL)
233 
        l.sw    0(r4),r5
234 
 
235 
        l.addi  r4,r3,MC_CSC(1)
236 817 simons 
        l.movhi r5,hi(SDRAM_BASE_ADDR)
237 809 simons 
        l.srai  r5,r5,5
238 
        l.ori   r5,r5,0x0411
239 
        l.sw    0(r4),r5
240 
 
241 
        l.jr    r9
242 
        l.nop
243 
.endif
244 
 
245 
_int_wrapper:
246 
        l.addi  r1,r1,-128
247 
 
248 
        l.sw    0x4(r1),r2
249 
        l.sw    0x8(r1),r4
250 
        l.sw    0xc(r1),r5
251 
        l.sw    0x10(r1),r6
252 
        l.sw    0x14(r1),r7
253 
        l.sw    0x18(r1),r8
254 
        l.sw    0x1c(r1),r9
255 
        l.sw    0x20(r1),r10
256 
        l.sw    0x24(r1),r11
257 
        l.sw    0x28(r1),r12
258 
        l.sw    0x2c(r1),r13
259 
        l.sw    0x30(r1),r14
260 
        l.sw    0x34(r1),r15
261 
        l.sw    0x38(r1),r16
262 
        l.sw    0x3c(r1),r17
263 
        l.sw    0x40(r1),r18
264 
        l.sw    0x44(r1),r19
265 
        l.sw    0x48(r1),r20
266 
        l.sw    0x4c(r1),r21
267 
        l.sw    0x50(r1),r22
268 
        l.sw    0x54(r1),r23
269 
        l.sw    0x58(r1),r24
270 
        l.sw    0x5c(r1),r25
271 
        l.sw    0x60(r1),r26
272 
        l.sw    0x64(r1),r27
273 
        l.sw    0x68(r1),r28
274 
        l.sw    0x6c(r1),r29
275 
        l.sw    0x70(r1),r30
276 
        l.sw    0x74(r1),r31
277 
        l.sw    0x78(r1),r3
278 
 
279 
        l.movhi r3,hi(_eth_int)
280 
        l.ori   r3,r3,lo(_eth_int)
281 
        l.jalr  r3
282 
        l.nop
283 
 
284 
        l.lwz   r2,0x4(r1)
285 
        l.lwz   r4,0x8(r1)
286 
        l.lwz   r5,0xc(r1)
287 
        l.lwz   r6,0x10(r1)
288 
        l.lwz   r7,0x14(r1)
289 
        l.lwz   r8,0x18(r1)
290 
        l.lwz   r9,0x1c(r1)
291 
        l.lwz   r10,0x20(r1)
292 
        l.lwz   r11,0x24(r1)
293 
        l.lwz   r12,0x28(r1)
294 
        l.lwz   r13,0x2c(r1)
295 
        l.lwz   r14,0x30(r1)
296 
        l.lwz   r15,0x34(r1)
297 
        l.lwz   r16,0x38(r1)
298 
        l.lwz   r17,0x3c(r1)
299 
        l.lwz   r18,0x40(r1)
300 
        l.lwz   r19,0x44(r1)
301 
        l.lwz   r20,0x48(r1)
302 
        l.lwz   r21,0x4c(r1)
303 
        l.lwz   r22,0x50(r1)
304 
        l.lwz   r23,0x54(r1)
305 
        l.lwz   r24,0x58(r1)
306 
        l.lwz   r25,0x5c(r1)
307 
        l.lwz   r26,0x60(r1)
308 
        l.lwz   r27,0x64(r1)
309 
        l.lwz   r28,0x68(r1)
310 
        l.lwz   r29,0x6c(r1)
311 
        l.lwz   r30,0x70(r1)
312 
        l.lwz   r31,0x74(r1)
313 
#        l.lwz   r3,0x78(r1)
314 
 
315 
        l.mtspr r0,r0,SPR_PICSR
316 
 
317 
        l.mfspr r3,r0,SPR_ESR_BASE
318 
        l.ori   r3,r3,SPR_SR_IEE
319 
        l.mtspr r0,r3,SPR_ESR_BASE
320 
 
321 
        l.lwz   r3,0x78(r1)
322 
 
323 
        l.addi  r1,r1,128
324 
        l.rfe
325 
        l.nop
326 
 
327 817 simons 
_align:
328 
        l.addi  r1,r1,-128
329 
        l.sw    0x08(r1),r2
330 
        l.sw    0x0c(r1),r3
331 
        l.sw    0x10(r1),r4
332 
        l.sw    0x14(r1),r5
333 
        l.sw    0x18(r1),r6
334 
        l.sw    0x1c(r1),r7
335 
        l.sw    0x20(r1),r8
336 
        l.sw    0x24(r1),r9
337 
        l.sw    0x28(r1),r10
338 
        l.sw    0x2c(r1),r11
339 
        l.sw    0x30(r1),r12
340 
        l.sw    0x34(r1),r13
341 
        l.sw    0x38(r1),r14
342 
        l.sw    0x3c(r1),r15
343 
        l.sw    0x40(r1),r16
344 
        l.sw    0x44(r1),r17
345 
        l.sw    0x48(r1),r18
346 
        l.sw    0x4c(r1),r19
347 
        l.sw    0x50(r1),r20
348 
        l.sw    0x54(r1),r21
349 
        l.sw    0x58(r1),r22
350 
        l.sw    0x5c(r1),r23
351 
        l.sw    0x60(r1),r24
352 
        l.sw    0x64(r1),r25
353 
        l.sw    0x68(r1),r26
354 
        l.sw    0x6c(r1),r27
355 
        l.sw    0x70(r1),r28
356 
        l.sw    0x74(r1),r29
357 
        l.sw    0x78(r1),r30
358 
        l.sw    0x7c(r1),r31
359 
 
360 
        l.mfspr r2,r0,SPR_EEAR_BASE /* Load the efective addres */
361 
        l.mfspr r5,r0,SPR_EPCR_BASE /* Load the insn address */
362 
 
363 
        l.lwz r3,0(r5)      /* Load insn */
364 
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
365 
 
366 
        l.sfeqi r4,0x00     /* Check if the load/store insn is in delay slot */
367 
        l.bf  jmp
368 
        l.sfeqi r4,0x01
369 
        l.bf  jmp
370 
        l.sfeqi r4,0x03
371 
        l.bf  jmp
372 
        l.sfeqi r4,0x04
373 
        l.bf  jmp
374 
        l.sfeqi r4,0x11
375 
        l.bf  jr
376 
        l.sfeqi r4,0x12
377 
        l.bf  jr
378 
        l.nop
379 
        l.j 1f
380 
        l.addi  r5,r5,4     /* Increment PC to get return insn address */
381 
 
382 
jmp:
383 
        l.slli  r4,r3,6     /* Get the signed extended jump length */
384 
        l.srai  r4,r4,4
385 
 
386 
        l.lwz r3,4(r5)      /* Load the real load/store insn */
387 
 
388 
        l.add r5,r5,r4      /* Calculate jump target address */
389 
 
390 
        l.j 1f
391 
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
392 
 
393 
jr:
394 
        l.slli  r4,r3,9     /* Shift to get the reg nb */
395 
        l.andi  r4,r4,0x7c
396 
 
397 
        l.lwz r3,4(r5)    /* Load the real load/store insn */
398 
 
399 
        l.add r4,r4,r1    /* Load the jump register value from the stack */
400 
        l.lwz r5,0(r4)
401 
 
402 
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
403 
 
404 
 
405 
1:      l.mtspr r0,r5,SPR_EPCR_BASE
406 
 
407 
        l.sfeqi r4,0x26
408 
        l.bf  lhs
409 
        l.sfeqi r4,0x25
410 
        l.bf  lhz
411 
        l.sfeqi r4,0x22
412 
        l.bf  lws
413 
        l.sfeqi r4,0x21
414 
        l.bf  lwz
415 
        l.sfeqi r4,0x37
416 
        l.bf  sh
417 
        l.sfeqi r4,0x35
418 
        l.bf  sw
419 
        l.nop
420 
 
421 
1:      l.j 1b      /* I don't know what to do */
422 
        l.nop
423 
 
424 
lhs:    l.lbs r5,0(r2)
425 
        l.slli  r5,r5,8
426 
        l.lbz r6,1(r2)
427 
        l.or  r5,r5,r6
428 
        l.srli  r4,r3,19
429 
        l.andi  r4,r4,0x7c
430 
        l.add r4,r4,r1
431 
        l.j align_end
432 
        l.sw  0(r4),r5
433 
 
434 
lhz:    l.lbz r5,0(r2)
435 
        l.slli  r5,r5,8
436 
        l.lbz r6,1(r2)
437 
        l.or  r5,r5,r6
438 
        l.srli  r4,r3,19
439 
        l.andi  r4,r4,0x7c
440 
        l.add r4,r4,r1
441 
        l.j align_end
442 
        l.sw  0(r4),r5
443 
 
444 
lws:    l.lbs r5,0(r2)
445 
        l.slli  r5,r5,24
446 
        l.lbz r6,1(r2)
447 
        l.slli  r6,r6,16
448 
        l.or  r5,r5,r6
449 
        l.lbz r6,2(r2)
450 
        l.slli  r6,r6,8
451 
        l.or  r5,r5,r6
452 
        l.lbz r6,3(r2)
453 
        l.or  r5,r5,r6
454 
        l.srli  r4,r3,19
455 
        l.andi  r4,r4,0x7c
456 
        l.add r4,r4,r1
457 
        l.j align_end
458 
        l.sw  0(r4),r5
459 
 
460 
lwz:    l.lbz r5,0(r2)
461 
        l.slli  r5,r5,24
462 
        l.lbz r6,1(r2)
463 
        l.slli  r6,r6,16
464 
        l.or  r5,r5,r6
465 
        l.lbz r6,2(r2)
466 
        l.slli  r6,r6,8
467 
        l.or  r5,r5,r6
468 
        l.lbz r6,3(r2)
469 
        l.or  r5,r5,r6
470 
        l.srli  r4,r3,19
471 
        l.andi  r4,r4,0x7c
472 
        l.add r4,r4,r1
473 
        l.j align_end
474 
        l.sw  0(r4),r5
475 
 
476 
sh:
477 
        l.srli  r4,r3,9
478 
        l.andi  r4,r4,0x7c
479 
        l.add r4,r4,r1
480 
        l.lwz r5,0(r4)
481 
        l.sb  1(r2),r5
482 
        l.slli  r5,r5,8
483 
        l.j align_end
484 
        l.sb  0(r2),r5
485 
 
486 
sw:
487 
        l.srli  r4,r3,9
488 
        l.andi  r4,r4,0x7c
489 
        l.add r4,r4,r1
490 
        l.lwz r5,0(r4)
491 
        l.sb  3(r2),r5
492 
        l.slli  r5,r5,8
493 
        l.sb  2(r2),r5
494 
        l.slli  r5,r5,8
495 
        l.sb  1(r2),r5
496 
        l.slli  r5,r5,8
497 
        l.j align_end
498 
        l.sb  0(r2),r5
499 
 
500 
align_end:
501 
        l.lwz   r2,0x08(r1)
502 
        l.lwz   r3,0x0c(r1)
503 
        l.lwz   r4,0x10(r1)
504 
        l.lwz   r5,0x14(r1)
505 
        l.lwz   r6,0x18(r1)
506 
        l.lwz   r7,0x1c(r1)
507 
        l.lwz   r8,0x20(r1)
508 
        l.lwz   r9,0x24(r1)
509 
        l.lwz   r10,0x28(r1)
510 
        l.lwz   r11,0x2c(r1)
511 
        l.lwz   r12,0x30(r1)
512 
        l.lwz   r13,0x34(r1)
513 
        l.lwz   r14,0x38(r1)
514 
        l.lwz   r15,0x3c(r1)
515 
        l.lwz   r16,0x40(r1)
516 
        l.lwz   r17,0x44(r1)
517 
        l.lwz   r18,0x48(r1)
518 
        l.lwz   r19,0x4c(r1)
519 
        l.lwz   r20,0x50(r1)
520 
        l.lwz   r21,0x54(r1)
521 
        l.lwz   r22,0x58(r1)
522 
        l.lwz   r23,0x5c(r1)
523 
        l.lwz   r24,0x60(r1)
524 
        l.lwz   r25,0x64(r1)
525 
        l.lwz   r26,0x68(r1)
526 
        l.lwz   r27,0x6c(r1)
527 
        l.lwz   r28,0x70(r1)
528 
        l.lwz   r29,0x74(r1)
529 
        l.lwz   r30,0x78(r1)
530 
        l.lwz   r31,0x7c(r1)
531 
        l.addi  r1,r1,128
532 
        l.rfe
533 
 
534 809 simons 
        .section .text
535 
_lolev_ie:
536 
        l.mfspr r3,r0,SPR_SR
537 
        l.ori   r3,r3,SPR_SR_IEE
538 
        l.mtspr r0,r3,SPR_SR
539 817 simons 
        l.movhi r3,hi(ETH0_INT)
540 
  l.ori r3,r3,lo(ETH0_INT)
541 809 simons 
        l.mtspr r0,r3,SPR_PICMR
542 
 
543 
        l.jr    r9
544 
        l.nop
545 
 
546 
_lolev_idis:
547 
        l.mtspr r0,r0,SPR_PICMR
548 
 
549 
        l.jr    r9
550 
        l.nop

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