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#include "spr_defs.h"
#include "board.h"
#include "mc.h"
 
 
 
        .extern _reset_support
        .extern _eth_int
        .extern _src_beg
        .extern _dst_beg
        .extern _dst_end
        .extern _c_reset
        .extern _int_main
        .extern _crc32
 
        /* Used by global.src_addr for default value */
        .extern _src_addr
 
        .global _lolev_ie
        .global _lolev_idis
        .global _align
        .global _calc_mycrc32
        .global _mycrc32
        .global _mysize
 
        .section .stack, "aw", @nobits
.space  STACK_SIZE
_stack:
                                .section .crc
_mycrc32:
        .word   0xcccccccc
_mysize:
        .word 0xdddddddd
 
_calc_mycrc32:
        l.addi  r3,r0,0
        l.movhi r4,hi(_calc_mycrc32)
        l.ori   r4,r4,lo(_calc_mycrc32)
        l.movhi r5,hi(_mysize)
        l.ori   r5,r5,lo(_mysize)
        l.lwz   r5,0(r5)
        l.addi  r1,r1,-4
        l.sw    0(r1),r9
 
        /* unsigned long crc32 (unsigned long crc, const unsigned char *buf, unsigned long len); */
        l.jal           _crc32
        l.nop
 
        l.movhi r3,hi(_mycrc32)
        l.ori   r3,r3,lo(_mycrc32)
        l.lwz   r3,0(r3)
 
        l.xor     r11,r3,r11
        l.lwz   r9,0(r1)
        l.jr    r9
        l.addi  r1,r1,4
 
        .org 0x100
.if IN_FLASH
        .section .reset, "ax"
.else
        .section .vectors, "ax"
.endif
 
_reset:
.if IN_FLASH
        l.movhi r3,hi(MC_BASE_ADDR)
        l.ori   r3,r3,MC_BA_MASK
        l.addi  r5,r0,0x00
        l.sw    0(r3),r5
.endif
        l.movhi r3,hi(_start1)
        l.ori   r3,r3,lo(_start1)
#        l.jr    r3
        l.j _start1
 
.if IN_FLASH
        .section .vectors, "ax"
        .org 0x600
.else
        .org (0x600 - 0x100 + _reset)
.endif
 
        l.j     _align
        l.nop
 
.if IN_FLASH
        .org 0x800
.else
        .org (0x800 - 0x100 + _reset)
.endif
 
        l.j     _int_wrapper
        l.nop
 
        .section .text
_start1:
        l.nop
        l.jal   _putc
.if IN_FLASH
        l.jal   _init_mc
        l.nop
 
        /* Wait for SDRAM */
        l.addi  r3,r0,0x0000  /* igor zmanjsal iz 0x7fff na 0x0000 */
1:      l.sfeqi r3,0
        l.bnf   1b
        l.addi  r3,r3,-1
.endif
        /* Copy form flash to sram */
.if IN_FLASH
        l.movhi r3,hi(_src_beg)
        l.ori   r3,r3,lo(_src_beg)
        l.movhi r4,hi(_vec_start)
        l.ori   r4,r4,lo(_vec_start)
        l.movhi r5,hi(_vec_end)
        l.ori   r5,r5,lo(_vec_end)
        l.sub   r5,r5,r4
        l.sfeqi r5,0
        l.bf    2f
        l.nop
1:      l.lwz   r6,0(r3)
        l.sw    0(r4),r6
        l.addi  r3,r3,4
        l.addi  r4,r4,4
        l.addi  r5,r5,-4
        l.sfgtsi r5,0
        l.bf    1b
        l.nop
2:
        l.movhi r4,hi(_dst_beg)
        l.ori   r4,r4,lo(_dst_beg)
        l.movhi r5,hi(_dst_end)
        l.ori   r5,r5,lo(_dst_end)
1:      l.sfgeu r4,r5
        l.bf    1f
        l.nop
        l.lwz   r8,0(r3)
        l.sw    0(r4),r8
        l.addi  r3,r3,4
        l.bnf   1b
        l.addi  r4,r4,4
1:
        l.addi  r3,r0,0
        l.addi  r4,r0,0
3:
.endif
 
.if IC_ENABLE
  l.jal _ic_enable
  l.nop
.endif
 
.if DC_ENABLE
  l.jal _dc_enable
  l.nop
.endif
 
        l.movhi r1,hi(_stack-4)
        l.addi  r1,r1,lo(_stack-4)
  l.addi  r2,r0,-3
  l.and r1,r1,r2
 
        l.movhi r2,hi(_main)
        l.ori   r2,r2,lo(_main)
        l.jr    r2
        l.addi  r2,r0,0
 
_ic_enable:
 
        /* Flush IC */
        l.addi  r10,r0,0
        l.addi  r11,r0,IC_SIZE
1:
        l.mtspr r0,r10,SPR_ICBIR
        l.sfne  r10,r11
        l.bf    1b
        l.addi  r10,r10,16
 
        /* Enable IC */
        l.addi  r10,r0,(SPR_SR_ICE|SPR_SR_SM)
        l.mtspr r0,r10,SPR_SR
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
  l.jr  r9
  l.nop
 
_dc_enable:
 
        /* Flush DC */
        l.addi  r10,r0,0
        l.addi  r11,r0,DC_SIZE
1:
        l.mtspr r0,r10,SPR_DCBIR
        l.sfne  r10,r11
        l.bf    1b
        l.addi  r10,r10,16
 
        /* Enable DC */
        l.addi  r10,r0,(SPR_SR_DCE|SPR_SR_SM)
        l.mtspr r0,r10,SPR_SR
 
  l.jr  r9
  l.nop
 
.if IN_FLASH
_init_mc:
 
        l.movhi r3,hi(MC_BASE_ADDR)
        l.ori   r3,r3,lo(MC_BASE_ADDR)
 
        l.addi  r4,r3,MC_CSC(0)
        l.movhi r5,hi(FLASH_BASE_ADDR)
        l.srai  r5,r5,5
        l.ori   r5,r5,0x0025
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_TMS(0)
        l.movhi r5,hi(FLASH_TMS_VAL)
        l.ori   r5,r5,lo(FLASH_TMS_VAL)
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_BA_MASK
        l.addi  r5,r0,MC_MASK_VAL
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_CSR
        l.movhi r5,hi(MC_CSR_VAL)
        l.ori   r5,r5,lo(MC_CSR_VAL)
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_TMS(1)
        l.movhi r5,hi(SDRAM_TMS_VAL)
        l.ori   r5,r5,lo(SDRAM_TMS_VAL)
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_CSC(1)
        l.movhi r5,hi(SDRAM_BASE_ADDR)
        l.srai  r5,r5,5
        l.ori   r5,r5,0x0411
        l.sw    0(r4),r5
 
        l.jr    r9
        l.nop
.endif
 
_int_wrapper:
        l.addi  r1,r1,-128
 
        l.sw    0x4(r1),r2
        l.sw    0x8(r1),r4
        l.sw    0xc(r1),r5
        l.sw    0x10(r1),r6
        l.sw    0x14(r1),r7
        l.sw    0x18(r1),r8
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.sw    0x24(r1),r11
        l.sw    0x28(r1),r12
        l.sw    0x2c(r1),r13
        l.sw    0x30(r1),r14
        l.sw    0x34(r1),r15
        l.sw    0x38(r1),r16
        l.sw    0x3c(r1),r17
        l.sw    0x40(r1),r18
        l.sw    0x44(r1),r19
        l.sw    0x48(r1),r20
        l.sw    0x4c(r1),r21
        l.sw    0x50(r1),r22
        l.sw    0x54(r1),r23
        l.sw    0x58(r1),r24
        l.sw    0x5c(r1),r25
        l.sw    0x60(r1),r26
        l.sw    0x64(r1),r27
        l.sw    0x68(r1),r28
        l.sw    0x6c(r1),r29
        l.sw    0x70(r1),r30
        l.sw    0x74(r1),r31
        l.sw    0x78(r1),r3
 
        l.movhi r3,hi(_eth_int)
        l.ori   r3,r3,lo(_eth_int)
        l.jalr  r3
        l.nop
 
        l.lwz   r2,0x4(r1)
        l.lwz   r4,0x8(r1)
        l.lwz   r5,0xc(r1)
        l.lwz   r6,0x10(r1)
        l.lwz   r7,0x14(r1)
        l.lwz   r8,0x18(r1)
        l.lwz   r9,0x1c(r1)
        l.lwz   r10,0x20(r1)
        l.lwz   r11,0x24(r1)
        l.lwz   r12,0x28(r1)
        l.lwz   r13,0x2c(r1)
        l.lwz   r14,0x30(r1)
        l.lwz   r15,0x34(r1)
        l.lwz   r16,0x38(r1)
        l.lwz   r17,0x3c(r1)
        l.lwz   r18,0x40(r1)
        l.lwz   r19,0x44(r1)
        l.lwz   r20,0x48(r1)
        l.lwz   r21,0x4c(r1)
        l.lwz   r22,0x50(r1)
        l.lwz   r23,0x54(r1)
        l.lwz   r24,0x58(r1)
        l.lwz   r25,0x5c(r1)
        l.lwz   r26,0x60(r1)
        l.lwz   r27,0x64(r1)
        l.lwz   r28,0x68(r1)
        l.lwz   r29,0x6c(r1)
        l.lwz   r30,0x70(r1)
        l.lwz   r31,0x74(r1)
#        l.lwz   r3,0x78(r1)
 
        l.mtspr r0,r0,SPR_PICSR
 
        l.mfspr r3,r0,SPR_ESR_BASE
        l.ori   r3,r3,SPR_SR_IEE
        l.mtspr r0,r3,SPR_ESR_BASE
 
        l.lwz   r3,0x78(r1)
 
        l.addi  r1,r1,128
        l.rfe
        l.nop
 
_align:
        l.addi  r1,r1,-128
        l.sw    0x08(r1),r2
        l.sw    0x0c(r1),r3
        l.sw    0x10(r1),r4
        l.sw    0x14(r1),r5
        l.sw    0x18(r1),r6
        l.sw    0x1c(r1),r7
        l.sw    0x20(r1),r8
        l.sw    0x24(r1),r9
        l.sw    0x28(r1),r10
        l.sw    0x2c(r1),r11
        l.sw    0x30(r1),r12
        l.sw    0x34(r1),r13
        l.sw    0x38(r1),r14
        l.sw    0x3c(r1),r15
        l.sw    0x40(r1),r16
        l.sw    0x44(r1),r17
        l.sw    0x48(r1),r18
        l.sw    0x4c(r1),r19
        l.sw    0x50(r1),r20
        l.sw    0x54(r1),r21
        l.sw    0x58(r1),r22
        l.sw    0x5c(r1),r23
        l.sw    0x60(r1),r24
        l.sw    0x64(r1),r25
        l.sw    0x68(r1),r26
        l.sw    0x6c(r1),r27
        l.sw    0x70(r1),r28
        l.sw    0x74(r1),r29
        l.sw    0x78(r1),r30
        l.sw    0x7c(r1),r31
 
        l.mfspr r2,r0,SPR_EEAR_BASE /* Load the efective addres */
        l.mfspr r5,r0,SPR_EPCR_BASE /* Load the insn address */
 
        l.lwz r3,0(r5)      /* Load insn */
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
 
        l.sfeqi r4,0x00     /* Check if the load/store insn is in delay slot */
        l.bf  jmp
        l.sfeqi r4,0x01
        l.bf  jmp
        l.sfeqi r4,0x03
        l.bf  jmp
        l.sfeqi r4,0x04
        l.bf  jmp
        l.sfeqi r4,0x11
        l.bf  jr
        l.sfeqi r4,0x12
        l.bf  jr
        l.nop
        l.j 1f
        l.addi  r5,r5,4     /* Increment PC to get return insn address */
 
jmp:
        l.slli  r4,r3,6     /* Get the signed extended jump length */
        l.srai  r4,r4,4
 
        l.lwz r3,4(r5)      /* Load the real load/store insn */
 
        l.add r5,r5,r4      /* Calculate jump target address */
 
        l.j 1f
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
 
jr:
        l.slli  r4,r3,9     /* Shift to get the reg nb */
        l.andi  r4,r4,0x7c
 
        l.lwz r3,4(r5)    /* Load the real load/store insn */
 
        l.add r4,r4,r1    /* Load the jump register value from the stack */
        l.lwz r5,0(r4)
 
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
 
 
1:      l.mtspr r0,r5,SPR_EPCR_BASE
 
        l.sfeqi r4,0x26
        l.bf  lhs
        l.sfeqi r4,0x25
        l.bf  lhz
        l.sfeqi r4,0x22
        l.bf  lws
        l.sfeqi r4,0x21
        l.bf  lwz
        l.sfeqi r4,0x37
        l.bf  sh
        l.sfeqi r4,0x35
        l.bf  sw
        l.nop
 
1:      l.j 1b      /* I don't know what to do */
        l.nop
 
lhs:    l.lbs r5,0(r2)
        l.slli  r5,r5,8
        l.lbz r6,1(r2)
        l.or  r5,r5,r6
        l.srli  r4,r3,19
        l.andi  r4,r4,0x7c
        l.add r4,r4,r1
        l.j align_end
        l.sw  0(r4),r5
 
lhz:    l.lbz r5,0(r2)
        l.slli  r5,r5,8
        l.lbz r6,1(r2)
        l.or  r5,r5,r6
        l.srli  r4,r3,19
        l.andi  r4,r4,0x7c
        l.add r4,r4,r1
        l.j align_end
        l.sw  0(r4),r5
 
lws:    l.lbs r5,0(r2)
        l.slli  r5,r5,24
        l.lbz r6,1(r2)
        l.slli  r6,r6,16
        l.or  r5,r5,r6
        l.lbz r6,2(r2)
        l.slli  r6,r6,8
        l.or  r5,r5,r6
        l.lbz r6,3(r2)
        l.or  r5,r5,r6
        l.srli  r4,r3,19
        l.andi  r4,r4,0x7c
        l.add r4,r4,r1
        l.j align_end
        l.sw  0(r4),r5
 
lwz:    l.lbz r5,0(r2)
        l.slli  r5,r5,24
        l.lbz r6,1(r2)
        l.slli  r6,r6,16
        l.or  r5,r5,r6
        l.lbz r6,2(r2)
        l.slli  r6,r6,8
        l.or  r5,r5,r6
        l.lbz r6,3(r2)
        l.or  r5,r5,r6
        l.srli  r4,r3,19
        l.andi  r4,r4,0x7c
        l.add r4,r4,r1
        l.j align_end
        l.sw  0(r4),r5
 
sh:
        l.srli  r4,r3,9
        l.andi  r4,r4,0x7c
        l.add r4,r4,r1
        l.lwz r5,0(r4)
        l.sb  1(r2),r5
        l.slli  r5,r5,8
        l.j align_end
        l.sb  0(r2),r5
 
sw:
        l.srli  r4,r3,9
        l.andi  r4,r4,0x7c
        l.add r4,r4,r1
        l.lwz r5,0(r4)
        l.sb  3(r2),r5
        l.slli  r5,r5,8
        l.sb  2(r2),r5
        l.slli  r5,r5,8
        l.sb  1(r2),r5
        l.slli  r5,r5,8
        l.j align_end
        l.sb  0(r2),r5
 
align_end:
        l.lwz   r2,0x08(r1)
        l.lwz   r3,0x0c(r1)
        l.lwz   r4,0x10(r1)
        l.lwz   r5,0x14(r1)
        l.lwz   r6,0x18(r1)
        l.lwz   r7,0x1c(r1)
        l.lwz   r8,0x20(r1)
        l.lwz   r9,0x24(r1)
        l.lwz   r10,0x28(r1)
        l.lwz   r11,0x2c(r1)
        l.lwz   r12,0x30(r1)
        l.lwz   r13,0x34(r1)
        l.lwz   r14,0x38(r1)
        l.lwz   r15,0x3c(r1)
        l.lwz   r16,0x40(r1)
        l.lwz   r17,0x44(r1)
        l.lwz   r18,0x48(r1)
        l.lwz   r19,0x4c(r1)
        l.lwz   r20,0x50(r1)
        l.lwz   r21,0x54(r1)
        l.lwz   r22,0x58(r1)
        l.lwz   r23,0x5c(r1)
        l.lwz   r24,0x60(r1)
        l.lwz   r25,0x64(r1)
        l.lwz   r26,0x68(r1)
        l.lwz   r27,0x6c(r1)
        l.lwz   r28,0x70(r1)
        l.lwz   r29,0x74(r1)
        l.lwz   r30,0x78(r1)
        l.lwz   r31,0x7c(r1)
        l.addi  r1,r1,128
        l.rfe
 
        .section .text
_lolev_ie:
        l.mfspr r3,r0,SPR_SR
        l.ori   r3,r3,SPR_SR_IEE
        l.mtspr r0,r3,SPR_SR
        l.movhi r3,hi(ETH0_INT)
  l.ori r3,r3,lo(ETH0_INT)
        l.mtspr r0,r3,SPR_PICMR
 
        l.jr    r9
        l.nop
 
_lolev_idis:
        l.mtspr r0,r0,SPR_PICMR
 
        l.jr    r9
        l.nop

Line No.	Rev	Author	Line
1	809	simons	`#include "spr_defs.h"`
2			`#include "board.h"`
3			`#include "mc.h"`
4
5
6
7			`.extern _reset_support`
8			`.extern _eth_int`
9			`.extern _src_beg`
10			`.extern _dst_beg`
11			`.extern _dst_end`
12			`.extern _c_reset`
13			`.extern _int_main`
14	820	markom	`.extern _crc32`
15	816	markom
16			`/* Used by global.src_addr for default value */`
17			`.extern _src_addr`
18	809	simons
19			`.global _lolev_ie`
20			`.global _lolev_idis`
21	817	simons	`.global _align`
22	820	markom	`.global _calc_mycrc32`
23	822	markom	`.global _mycrc32`
24			`.global _mysize`
25	809	simons
26	817	simons	`.section .stack, "aw", @nobits`
27			`.space STACK_SIZE`
28	809	simons	`_stack:`
29	820	markom	`.section .crc`
30			`_mycrc32:`
31			`.word 0xcccccccc`
32			`_mysize:`
33			`.word 0xdddddddd`
34	809	simons
35	820	markom	`_calc_mycrc32:`
36	828	markom	`l.addi r3,r0,0`
37	820	markom	`l.movhi r4,hi(_calc_mycrc32)`
38			`l.ori r4,r4,lo(_calc_mycrc32)`
39			`l.movhi r5,hi(_mysize)`
40			`l.ori r5,r5,lo(_mysize)`
41			`l.lwz r5,0(r5)`
42	822	markom	`l.addi r1,r1,-4`
43	828	markom	`l.sw 0(r1),r9`
44	820	markom
45			`/* unsigned long crc32 (unsigned long crc, const unsigned char buf, unsigned long len); /`
46	828	markom	`l.jal _crc32`
47			`l.nop`
48	820	markom
49	828	markom	`l.movhi r3,hi(_mycrc32)`
50	820	markom	`l.ori r3,r3,lo(_mycrc32)`
51			`l.lwz r3,0(r3)`
52
53	822	markom	`l.xor r11,r3,r11`
54			`l.lwz r9,0(r1)`
55			`l.jr r9`
56			`l.addi r1,r1,4`
57
58	828	markom	`.org 0x100`
59	809	simons	`.if IN_FLASH`
60			`.section .reset, "ax"`
61			`.else`
62	817	simons	`.section .vectors, "ax"`
63	809	simons	`.endif`
64
65			`_reset:`
66			`.if IN_FLASH`
67	817	simons	`l.movhi r3,hi(MC_BASE_ADDR)`
68	809	simons	`l.ori r3,r3,MC_BA_MASK`
69			`l.addi r5,r0,0x00`
70			`l.sw 0(r3),r5`
71			`.endif`
72	824	markom	`l.movhi r3,hi(_start1)`
73			`l.ori r3,r3,lo(_start1)`
74	828	markom	`# l.jr r3`
75			`l.j _start1`
76	809	simons
77			`.if IN_FLASH`
78			`.section .vectors, "ax"`
79	824	markom	`.org 0x600`
80			`.else`
81			`.org (0x600 - 0x100 + _reset)`
82	809	simons	`.endif`
83
84	817	simons	`l.j _align`
85			`l.nop`
86
87	824	markom	`.if IN_FLASH`
88	817	simons	`.org 0x800`
89	824	markom	`.else`
90			`.org (0x800 - 0x100 + _reset)`
91			`.endif`
92	817	simons
93	809	simons	`l.j _int_wrapper`
94			`l.nop`
95
96			`.section .text`
97	824	markom	`_start1:`
98	828	markom	`l.nop`
99			`l.jal _putc`
100	809	simons	`.if IN_FLASH`
101			`l.jal _init_mc`
102			`l.nop`
103
104			`/* Wait for SDRAM */`
105			`l.addi r3,r0,0x0000 /* igor zmanjsal iz 0x7fff na 0x0000 */`
106			`1: l.sfeqi r3,0`
107			`l.bnf 1b`
108			`l.addi r3,r3,-1`
109			`.endif`
110	817	simons	`/* Copy form flash to sram */`
111	809	simons	`.if IN_FLASH`
112			`l.movhi r3,hi(_src_beg)`
113			`l.ori r3,r3,lo(_src_beg)`
114			`l.movhi r4,hi(_vec_start)`
115			`l.ori r4,r4,lo(_vec_start)`
116			`l.movhi r5,hi(_vec_end)`
117			`l.ori r5,r5,lo(_vec_end)`
118			`l.sub r5,r5,r4`
119			`l.sfeqi r5,0`
120			`l.bf 2f`
121			`l.nop`
122			`1: l.lwz r6,0(r3)`
123			`l.sw 0(r4),r6`
124			`l.addi r3,r3,4`
125			`l.addi r4,r4,4`
126			`l.addi r5,r5,-4`
127			`l.sfgtsi r5,0`
128	817	simons	`l.bf 1b`
129	809	simons	`l.nop`
130			`2:`
131			`l.movhi r4,hi(_dst_beg)`
132			`l.ori r4,r4,lo(_dst_beg)`
133			`l.movhi r5,hi(_dst_end)`
134			`l.ori r5,r5,lo(_dst_end)`
135			`1: l.sfgeu r4,r5`
136			`l.bf 1f`
137			`l.nop`
138			`l.lwz r8,0(r3)`
139			`l.sw 0(r4),r8`
140			`l.addi r3,r3,4`
141			`l.bnf 1b`
142			`l.addi r4,r4,4`
143			`1:`
144			`l.addi r3,r0,0`
145			`l.addi r4,r0,0`
146			`3:`
147			`.endif`
148
149			`.if IC_ENABLE`
150	817	simons	`l.jal _ic_enable`
151			`l.nop`
152	809	simons	`.endif`
153
154			`.if DC_ENABLE`
155	817	simons	`l.jal _dc_enable`
156			`l.nop`
157	809	simons	`.endif`
158
159			`l.movhi r1,hi(_stack-4)`
160			`l.addi r1,r1,lo(_stack-4)`
161	817	simons	`l.addi r2,r0,-3`
162			`l.and r1,r1,r2`
163	809	simons
164			`l.movhi r2,hi(_main)`
165			`l.ori r2,r2,lo(_main)`
166			`l.jr r2`
167			`l.addi r2,r0,0`
168
169			`_ic_enable:`
170
171			`/* Flush IC */`
172			`l.addi r10,r0,0`
173			`l.addi r11,r0,IC_SIZE`
174			`1:`
175			`l.mtspr r0,r10,SPR_ICBIR`
176			`l.sfne r10,r11`
177			`l.bf 1b`
178			`l.addi r10,r10,16`
179
180			`/* Enable IC */`
181			`l.addi r10,r0,(SPR_SR_ICE\|SPR_SR_SM)`
182			`l.mtspr r0,r10,SPR_SR`
183			`l.nop`
184			`l.nop`
185			`l.nop`
186			`l.nop`
187			`l.nop`
188
189	817	simons	`l.jr r9`
190			`l.nop`
191	809	simons
192			`_dc_enable:`
193
194			`/* Flush DC */`
195			`l.addi r10,r0,0`
196			`l.addi r11,r0,DC_SIZE`
197			`1:`
198			`l.mtspr r0,r10,SPR_DCBIR`
199			`l.sfne r10,r11`
200			`l.bf 1b`
201			`l.addi r10,r10,16`
202
203			`/* Enable DC */`
204			`l.addi r10,r0,(SPR_SR_DCE\|SPR_SR_SM)`
205			`l.mtspr r0,r10,SPR_SR`
206
207	817	simons	`l.jr r9`
208			`l.nop`
209	809	simons
210			`.if IN_FLASH`
211			`_init_mc:`
212
213	817	simons	`l.movhi r3,hi(MC_BASE_ADDR)`
214			`l.ori r3,r3,lo(MC_BASE_ADDR)`
215	809	simons
216			`l.addi r4,r3,MC_CSC(0)`
217	817	simons	`l.movhi r5,hi(FLASH_BASE_ADDR)`
218	809	simons	`l.srai r5,r5,5`
219			`l.ori r5,r5,0x0025`
220			`l.sw 0(r4),r5`
221
222			`l.addi r4,r3,MC_TMS(0)`
223			`l.movhi r5,hi(FLASH_TMS_VAL)`
224			`l.ori r5,r5,lo(FLASH_TMS_VAL)`
225			`l.sw 0(r4),r5`
226
227			`l.addi r4,r3,MC_BA_MASK`
228			`l.addi r5,r0,MC_MASK_VAL`
229			`l.sw 0(r4),r5`
230
231			`l.addi r4,r3,MC_CSR`
232			`l.movhi r5,hi(MC_CSR_VAL)`
233			`l.ori r5,r5,lo(MC_CSR_VAL)`
234			`l.sw 0(r4),r5`
235
236			`l.addi r4,r3,MC_TMS(1)`
237			`l.movhi r5,hi(SDRAM_TMS_VAL)`
238			`l.ori r5,r5,lo(SDRAM_TMS_VAL)`
239			`l.sw 0(r4),r5`
240
241			`l.addi r4,r3,MC_CSC(1)`
242	817	simons	`l.movhi r5,hi(SDRAM_BASE_ADDR)`
243	809	simons	`l.srai r5,r5,5`
244			`l.ori r5,r5,0x0411`
245			`l.sw 0(r4),r5`
246
247			`l.jr r9`
248			`l.nop`
249			`.endif`
250
251			`_int_wrapper:`
252			`l.addi r1,r1,-128`
253
254			`l.sw 0x4(r1),r2`
255			`l.sw 0x8(r1),r4`
256			`l.sw 0xc(r1),r5`
257			`l.sw 0x10(r1),r6`
258			`l.sw 0x14(r1),r7`
259			`l.sw 0x18(r1),r8`
260			`l.sw 0x1c(r1),r9`
261			`l.sw 0x20(r1),r10`
262			`l.sw 0x24(r1),r11`
263			`l.sw 0x28(r1),r12`
264			`l.sw 0x2c(r1),r13`
265			`l.sw 0x30(r1),r14`
266			`l.sw 0x34(r1),r15`
267			`l.sw 0x38(r1),r16`
268			`l.sw 0x3c(r1),r17`
269			`l.sw 0x40(r1),r18`
270			`l.sw 0x44(r1),r19`
271			`l.sw 0x48(r1),r20`
272			`l.sw 0x4c(r1),r21`
273			`l.sw 0x50(r1),r22`
274			`l.sw 0x54(r1),r23`
275			`l.sw 0x58(r1),r24`
276			`l.sw 0x5c(r1),r25`
277			`l.sw 0x60(r1),r26`
278			`l.sw 0x64(r1),r27`
279			`l.sw 0x68(r1),r28`
280			`l.sw 0x6c(r1),r29`
281			`l.sw 0x70(r1),r30`
282			`l.sw 0x74(r1),r31`
283			`l.sw 0x78(r1),r3`
284
285			`l.movhi r3,hi(_eth_int)`
286			`l.ori r3,r3,lo(_eth_int)`
287			`l.jalr r3`
288			`l.nop`
289
290			`l.lwz r2,0x4(r1)`
291			`l.lwz r4,0x8(r1)`
292			`l.lwz r5,0xc(r1)`
293			`l.lwz r6,0x10(r1)`
294			`l.lwz r7,0x14(r1)`
295			`l.lwz r8,0x18(r1)`
296			`l.lwz r9,0x1c(r1)`
297			`l.lwz r10,0x20(r1)`
298			`l.lwz r11,0x24(r1)`
299			`l.lwz r12,0x28(r1)`
300			`l.lwz r13,0x2c(r1)`
301			`l.lwz r14,0x30(r1)`
302			`l.lwz r15,0x34(r1)`
303			`l.lwz r16,0x38(r1)`
304			`l.lwz r17,0x3c(r1)`
305			`l.lwz r18,0x40(r1)`
306			`l.lwz r19,0x44(r1)`
307			`l.lwz r20,0x48(r1)`
308			`l.lwz r21,0x4c(r1)`
309			`l.lwz r22,0x50(r1)`
310			`l.lwz r23,0x54(r1)`
311			`l.lwz r24,0x58(r1)`
312			`l.lwz r25,0x5c(r1)`
313			`l.lwz r26,0x60(r1)`
314			`l.lwz r27,0x64(r1)`
315			`l.lwz r28,0x68(r1)`
316			`l.lwz r29,0x6c(r1)`
317			`l.lwz r30,0x70(r1)`
318			`l.lwz r31,0x74(r1)`
319			`# l.lwz r3,0x78(r1)`
320
321			`l.mtspr r0,r0,SPR_PICSR`
322
323			`l.mfspr r3,r0,SPR_ESR_BASE`
324			`l.ori r3,r3,SPR_SR_IEE`
325			`l.mtspr r0,r3,SPR_ESR_BASE`
326
327			`l.lwz r3,0x78(r1)`
328
329			`l.addi r1,r1,128`
330			`l.rfe`
331			`l.nop`
332
333	817	simons	`_align:`
334			`l.addi r1,r1,-128`
335			`l.sw 0x08(r1),r2`
336			`l.sw 0x0c(r1),r3`
337			`l.sw 0x10(r1),r4`
338			`l.sw 0x14(r1),r5`
339			`l.sw 0x18(r1),r6`
340			`l.sw 0x1c(r1),r7`
341			`l.sw 0x20(r1),r8`
342			`l.sw 0x24(r1),r9`
343			`l.sw 0x28(r1),r10`
344			`l.sw 0x2c(r1),r11`
345			`l.sw 0x30(r1),r12`
346			`l.sw 0x34(r1),r13`
347			`l.sw 0x38(r1),r14`
348			`l.sw 0x3c(r1),r15`
349			`l.sw 0x40(r1),r16`
350			`l.sw 0x44(r1),r17`
351			`l.sw 0x48(r1),r18`
352			`l.sw 0x4c(r1),r19`
353			`l.sw 0x50(r1),r20`
354			`l.sw 0x54(r1),r21`
355			`l.sw 0x58(r1),r22`
356			`l.sw 0x5c(r1),r23`
357			`l.sw 0x60(r1),r24`
358			`l.sw 0x64(r1),r25`
359			`l.sw 0x68(r1),r26`
360			`l.sw 0x6c(r1),r27`
361			`l.sw 0x70(r1),r28`
362			`l.sw 0x74(r1),r29`
363			`l.sw 0x78(r1),r30`
364			`l.sw 0x7c(r1),r31`
365
366			`l.mfspr r2,r0,SPR_EEAR_BASE /* Load the efective addres */`
367			`l.mfspr r5,r0,SPR_EPCR_BASE /* Load the insn address */`
368
369			`l.lwz r3,0(r5) /* Load insn */`
370			`l.srli r4,r3,26 /* Shift left to get the insn opcode */`
371
372			`l.sfeqi r4,0x00 /* Check if the load/store insn is in delay slot */`
373			`l.bf jmp`
374			`l.sfeqi r4,0x01`
375			`l.bf jmp`
376			`l.sfeqi r4,0x03`
377			`l.bf jmp`
378			`l.sfeqi r4,0x04`
379			`l.bf jmp`
380			`l.sfeqi r4,0x11`
381			`l.bf jr`
382			`l.sfeqi r4,0x12`
383			`l.bf jr`
384			`l.nop`
385			`l.j 1f`
386			`l.addi r5,r5,4 /* Increment PC to get return insn address */`
387
388			`jmp:`
389			`l.slli r4,r3,6 /* Get the signed extended jump length */`
390			`l.srai r4,r4,4`
391
392			`l.lwz r3,4(r5) /* Load the real load/store insn */`
393
394			`l.add r5,r5,r4 /* Calculate jump target address */`
395
396			`l.j 1f`
397			`l.srli r4,r3,26 /* Shift left to get the insn opcode */`
398
399			`jr:`
400			`l.slli r4,r3,9 /* Shift to get the reg nb */`
401			`l.andi r4,r4,0x7c`
402
403			`l.lwz r3,4(r5) /* Load the real load/store insn */`
404
405			`l.add r4,r4,r1 /* Load the jump register value from the stack */`
406			`l.lwz r5,0(r4)`
407
408			`l.srli r4,r3,26 /* Shift left to get the insn opcode */`
409
410
411			`1: l.mtspr r0,r5,SPR_EPCR_BASE`
412
413			`l.sfeqi r4,0x26`
414			`l.bf lhs`
415			`l.sfeqi r4,0x25`
416			`l.bf lhz`
417			`l.sfeqi r4,0x22`
418			`l.bf lws`
419			`l.sfeqi r4,0x21`
420			`l.bf lwz`
421			`l.sfeqi r4,0x37`
422			`l.bf sh`
423			`l.sfeqi r4,0x35`
424			`l.bf sw`
425			`l.nop`
426
427			`1: l.j 1b /* I don't know what to do */`
428			`l.nop`
429
430			`lhs: l.lbs r5,0(r2)`
431			`l.slli r5,r5,8`
432			`l.lbz r6,1(r2)`
433			`l.or r5,r5,r6`
434			`l.srli r4,r3,19`
435			`l.andi r4,r4,0x7c`
436			`l.add r4,r4,r1`
437			`l.j align_end`
438			`l.sw 0(r4),r5`
439
440			`lhz: l.lbz r5,0(r2)`
441			`l.slli r5,r5,8`
442			`l.lbz r6,1(r2)`
443			`l.or r5,r5,r6`
444			`l.srli r4,r3,19`
445			`l.andi r4,r4,0x7c`
446			`l.add r4,r4,r1`
447			`l.j align_end`
448			`l.sw 0(r4),r5`
449
450			`lws: l.lbs r5,0(r2)`
451			`l.slli r5,r5,24`
452			`l.lbz r6,1(r2)`
453			`l.slli r6,r6,16`
454			`l.or r5,r5,r6`
455			`l.lbz r6,2(r2)`
456			`l.slli r6,r6,8`
457			`l.or r5,r5,r6`
458			`l.lbz r6,3(r2)`
459			`l.or r5,r5,r6`
460			`l.srli r4,r3,19`
461			`l.andi r4,r4,0x7c`
462			`l.add r4,r4,r1`
463			`l.j align_end`
464			`l.sw 0(r4),r5`
465
466			`lwz: l.lbz r5,0(r2)`
467			`l.slli r5,r5,24`
468			`l.lbz r6,1(r2)`
469			`l.slli r6,r6,16`
470			`l.or r5,r5,r6`
471			`l.lbz r6,2(r2)`
472			`l.slli r6,r6,8`
473			`l.or r5,r5,r6`
474			`l.lbz r6,3(r2)`
475			`l.or r5,r5,r6`
476			`l.srli r4,r3,19`
477			`l.andi r4,r4,0x7c`
478			`l.add r4,r4,r1`
479			`l.j align_end`
480			`l.sw 0(r4),r5`
481
482			`sh:`
483			`l.srli r4,r3,9`
484			`l.andi r4,r4,0x7c`
485			`l.add r4,r4,r1`
486			`l.lwz r5,0(r4)`
487			`l.sb 1(r2),r5`
488			`l.slli r5,r5,8`
489			`l.j align_end`
490			`l.sb 0(r2),r5`
491
492			`sw:`
493			`l.srli r4,r3,9`
494			`l.andi r4,r4,0x7c`
495			`l.add r4,r4,r1`
496			`l.lwz r5,0(r4)`
497			`l.sb 3(r2),r5`
498			`l.slli r5,r5,8`
499			`l.sb 2(r2),r5`
500			`l.slli r5,r5,8`

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